diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-07-26 06:17:10 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-07-26 06:17:10 +0000 |
| commit | c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c (patch) | |
| tree | 53c0ebd122fe369cc08b4ed3bf885ba39e9a07f1 /os/hal/ports/STM32/STM32L0xx | |
| parent | b05e7e8c4464bda8fecd21ff80086a34edf9292c (diff) | |
| download | ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.tar.gz ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.tar.bz2 ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.zip | |
More STM32L0xx support files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8104 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c | 265 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h | 114 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/hal_lld.c | 14 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/hal_lld.h | 168 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/platform.mk | 31 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 96 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 345 |
7 files changed, 838 insertions, 195 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c new file mode 100644 index 000000000..36731f9bb --- /dev/null +++ b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c @@ -0,0 +1,265 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/ext_lld_isr.c
+ * @brief STM32L0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0]...EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 0) | (1 << 1));
+ EXTI->PR = pr;
+ if (pr & (1 << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+ if (pr & (1 << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2]...EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 2) | (1 << 3));
+ EXTI->PR = pr;
+ if (pr & (1 << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+ if (pr & (1 << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
+ (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
+ (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15));
+ EXTI->PR = pr;
+ if (pr & (1 << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+ if (pr & (1 << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1 << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1 << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1 << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1 << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+ if (pr & (1 << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1 << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1 << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1 << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1 << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1 << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & (1 << 16);
+ EXTI->PR = pr;
+ if (pr & (1 << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 17) | (1 << 19) | (1 << 20));
+ EXTI->PR = pr;
+ if (pr & (1 << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1 << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1 << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[20],EXTI[21] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 21) | (1 << 22));
+ EXTI->PR = pr;
+ if (pr & (1 << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1 << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(STM32_EXTI_LINE01_NUMBER,
+ STM32_EXT_EXTI0_1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE23_NUMBER,
+ STM32_EXT_EXTI2_3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER,
+ STM32_EXT_EXTI4_15_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE16_NUMBER,
+ STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE171920_NUMBER,
+ STM32_EXT_EXTI17_20_IRQ_PRIORITY);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be enabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+ }
+#else
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(STM32_EXTI_LINE01_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE23_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE16_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE2122_NUMBER);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be disabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+ }
+#else
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h new file mode 100644 index 000000000..646ef092d --- /dev/null +++ b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.h @@ -0,0 +1,114 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/ext_lld_isr.h
+ * @brief STM32L0xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef _EXT_LLD_ISR_H_
+#define _EXT_LLD_ISR_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief EXTI0..1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI2..3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI4..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI16 (PVD) interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI17,19,20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI21,22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void ext_lld_exti_irq_enable(void);
+ void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* _EXT_LLD_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c index b30686505..70865b9de 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c @@ -22,8 +22,6 @@ * @{
*/
-/* TODO: LSEBYP like in F3. Disable HSI16 if not used.*/
-
#include "hal.h"
/*===========================================================================*/
@@ -180,6 +178,13 @@ void stm32_clock_init(void) { /* LSE activation, have to unlock the register.*/
if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
PWR->CR |= PWR_CR_DBP;
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->CSR |= STM32_LSEDRV | RCC_CSR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->CSR |= STM32_LSEDRV;
+#endif
RCC->CSR |= RCC_CSR_LSEON;
PWR->CR &= ~PWR_CR_DBP;
}
@@ -212,14 +217,15 @@ void stm32_clock_init(void) { while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
-#endif /* STM32_NO_INIT */
/* Peripherals clock sources setup.*/
- RCC->CCIPR = STM32_HSI48SEL;
+ RCC->CCIPR = STM32_HSI48SEL | STM32_LPTIM1CLK | STM32_I2C1CLK |
+ STM32_LPUART1CLK | STM32_USART2CLK | STM32_USART1CLK;
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+#endif /* STM32_NO_INIT */
}
/** @} */
diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index d68299aa1..1b776eea4 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -233,8 +233,8 @@ #define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
#define STM32_USART1SEL_HSI16 (2 << 0) /**< USART1 clock is HSI16. */
#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 clock is LSE. */
-#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 clock source mask. */
+#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 clock source mask. */
#define STM32_USART2SEL_APB (0 << 2) /**< USART2 clock is APB. */
#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 clock is SYSCLK. */
#define STM32_USART2SEL_HSI16 (2 << 2) /**< USART2 clock is HSI16. */
@@ -251,10 +251,11 @@ #define STM32_I2C1SEL_SYSCLK (1 << 12) /**< I2C1 clock is SYSCLK. */
#define STM32_I2C1SEL_HSI16 (2 << 12) /**< I2C1 clock is HSI16. */
-#define STM32_I2C3SEL_MASK (3 << 16) /**< I2C3 clock source mask. */
-#define STM32_I2C3SEL_APB (0 << 16) /**< I2C3 clock is APB. */
-#define STM32_I2C3SEL_SYSCLK (1 << 16) /**< I2C3 clock is SYSCLK. */
-#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 clock is HSI16. */
+#define STM32_LPTIM1SEL_MASK (3 << 18) /**< LPTIM1 clock source mask. */
+#define STM32_LPTIM1SEL_APB (0 << 18) /**< LPTIM1 clock is APB. */
+#define STM32_LPTIM1SEL_SYSCLK (1 << 18) /**< LPTIM1 clock is SYSCLK. */
+#define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 clock is HSI16. */
+#define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 clock is LSE. */
#define STM32_HSI48SEL_MASK (1 << 27) /**< HSI48SEL clock source mask.*/
#define STM32_HSI48SEL_USBPLL (0 << 27) /**< USB48 clock is PLL/2. */
@@ -273,7 +274,7 @@ * @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT FALSE
+#define STM32_NO_INIT FALSE
#endif
/**
@@ -283,70 +284,70 @@ * the maximum voltage.
*/
#if !defined(STM32_VOS) || defined(__DOXYGEN__)
-#define STM32_VOS STM32_VOS_1P8
+#define STM32_VOS STM32_VOS_1P8
#endif
/**
* @brief Enables or disables the programmable voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE FALSE
+#define STM32_PVD_ENABLE FALSE
#endif
/**
* @brief Sets voltage level for programmable voltage detector.
*/
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS STM32_PLS_LEV0
+#define STM32_PLS STM32_PLS_LEV0
#endif
/**
* @brief Enables or disables the HSI16 clock source.
*/
#if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI16_ENABLED TRUE
+#define STM32_HSI16_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED FALSE
+#define STM32_HSE_ENABLED FALSE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
#endif
/**
* @brief ADC clock setting.
*/
#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
-#define STM32_ADC_CLOCK_ENABLED TRUE
+#define STM32_ADC_CLOCK_ENABLED TRUE
#endif
/**
* @brief USB clock setting.
*/
#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_ENABLED TRUE
+#define STM32_USB_CLOCK_ENABLED TRUE
#endif
/**
* @brief MSI frequency setting.
*/
#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
-#define STM32_MSIRANGE STM32_MSIRANGE_2M
+#define STM32_MSIRANGE STM32_MSIRANGE_2M
#endif
/**
@@ -357,7 +358,7 @@ * the internal 16MHz HSI clock.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW STM32_SW_PLL
+#define STM32_SW STM32_SW_PLL
#endif
/**
@@ -368,7 +369,7 @@ * the internal 16MHz HSI clock.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC STM32_PLLSRC_HSI16
+#define STM32_PLLSRC STM32_PLLSRC_HSI16
#endif
/**
@@ -378,7 +379,7 @@ * the internal 16MHz HSI clock.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE 4
+#define STM32_PLLMUL_VALUE 4
#endif
/**
@@ -388,7 +389,7 @@ * the internal 16MHz HSI clock.
*/
#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLDIV_VALUE 2
+#define STM32_PLLDIV_VALUE 2
#endif
/**
@@ -397,56 +398,91 @@ * the internal 16MHz HSI clock.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_HPRE STM32_HPRE_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1 STM32_PPRE1_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV1
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_PPRE2 STM32_PPRE2_DIV1
#endif
/**
* @brief MCO clock source.
*/
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief MCO divider setting.
*/
#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
-#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
#endif
/**
* @brief RTC/LCD clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCSEL STM32_RTCSEL_LSI
#endif
/**
* @brief HSE divider toward RTC setting.
*/
#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
-#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#define STM32_RTCPRE STM32_RTCPRE_DIV2
+#endif
+
+/**
+ * @brief USART1 clock source.
+ */
+#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__)
+#define STM32_USART1SEL STM32_USART1SEL_APB
+#endif
+
+/**
+ * @brief USART2 clock source.
+ */
+#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__)
+#define STM32_USART2SEL STM32_USART2SEL_APB
+#endif
+
+/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_APB
+#endif
+
+/**
+ * @brief I2C clock source.
+ */
+#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
+#define STM32_I2C1SEL STM32_I2C1SEL_APB
+#endif
+
+/**
+ * @brief LPTIM1 clock source.
+ */
+#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__)
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_APB
#endif
/**
* @bief USB/RNG clock source.
*/
#if !defined(STM32_HSI48SEL) || defined(__DOXYGEN__)
-#define STM32_HSI48SEL STM32_HSI48SEL_HSI48
+#define STM32_HSI48SEL STM32_HSI48SEL_HSI48
#endif
/** @} */
@@ -952,6 +988,79 @@ #endif
/**
+ * @brief USART1 frequency.
+ */
+#if STM32_USART1SEL == STM32_USART1SEL_APB
+#define STM32_USART1CLK STM32_PCLK2
+#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
+#define STM32_USART1CLK STM32_SYSCLK
+#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
+#define STM32_USART1CLK STM32_HSI16CLK
+#elif STM32_USART1SEL == STM32_USART1SEL_LSE
+#define STM32_USART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief USART2 frequency.
+ */
+#if STM32_USART2SEL == STM32_USART2SEL_APB
+#define STM32_USART2CLK STM32_PCLK2
+#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
+#define STM32_USART2CLK STM32_SYSCLK
+#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
+#define STM32_USART2CLK STM32_HSI16CLK
+#elif STM32_USART2SEL == STM32_USART2SEL_LSE
+#define STM32_USART2CLK STM32_LSECLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief LPUART1 frequency.
+ */
+#if STM32_LPUART1SEL == STM32_LPUART1SEL_APB
+#define STM32_LPUART1CLK STM32_PCLK2
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART1CLK STM32_SYSCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+#define STM32_LPUART1CLK STM32_HSI16CLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+#define STM32_LPUART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
+ * @brief I2C1 frequency.
+ */
+#if STM32_I2C1SEL == STM32_I2C1SEL_APB
+#define STM32_I2C1CLK STM32_PCLK2
+#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
+#define STM32_I2C1CLK STM32_SYSCLK
+#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
+#define STM32_I2C1CLK STM32_HSI16CLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief LPTIM1 frequency.
+ */
+#if STM32_LPTIM1SEL == STM32_LPTIM1SEL_APB
+#define STM32_LPTIM1CLK STM32_PCLK2
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_SYSCLK
+#define STM32_LPTIM1CLK STM32_SYSCLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
+#define STM32_LPTIM1CLK STM32_HSI16CLK
+#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
+#define STM32_LPTIM1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPTIM1 clock"
+#endif
+
+/**
* @brief USB/RNG frequency.
*/
#if (STM32_HSI48SEL == STM32_HSI48SEL_HSI48) || defined(__DOXYGEN__)
@@ -1005,8 +1114,7 @@ /* Various helpers.*/
#include "nvic.h"
-//#include "stm32_isr.h"
-//#include "stm32_dma.h"
+#include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus
diff --git a/os/hal/ports/STM32/STM32L0xx/platform.mk b/os/hal/ports/STM32/STM32L0xx/platform.mk index 2f99f0e01..4b6a6e811 100644 --- a/os/hal/ports/STM32/STM32L0xx/platform.mk +++ b/os/hal/ports/STM32/STM32L0xx/platform.mk @@ -4,21 +4,21 @@ HALCONF := $(strip $(shell cat halconf.h | egrep -e "define")) PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
-ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
- $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/stm32_dma.c \
-PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/adc_lld.c
-endif
-ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
-PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \
- $(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c
-endif
ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c
endif
+ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c
+endif
ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
endif
+ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c
+endif
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c
endif
@@ -29,7 +29,7 @@ ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c
endif
ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
-PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c
endif
ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
@@ -51,17 +51,17 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c endif
else
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/hal_lld.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/can_lld.c \
- $(CHIBIOS)/os/hal/ports/STM32/LLD/ext_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
- $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1/spi_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
@@ -75,11 +75,14 @@ endif PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/STM32L0xx \
$(CHIBIOS)/os/hal/ports/STM32/LLD \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2 \
- $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 60270a447..892cd1c9b 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -268,7 +268,6 @@ */
/**
* @brief Enables the PWR interface clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
@@ -278,7 +277,6 @@ /**
* @brief Disables PWR interface clock.
- * @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
@@ -432,138 +430,80 @@ * @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
-
-/**
- * @brief Enables the TIM3 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
-
-/**
- * @brief Disables the TIM3 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
-
-/**
- * @brief Resets the TIM3 peripheral.
- *
- * @api
- */
-#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
-
/**
- * @brief Enables the TIM4 peripheral clock.
+ * @brief Enables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Disables the TIM4 peripheral clock.
+ * @brief Disables the TIM6 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
/**
- * @brief Resets the TIM4 peripheral.
+ * @brief Resets the TIM6 peripheral.
*
* @api
*/
-#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
/**
- * @brief Enables the TIM9 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Enables the TIM21 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
+#define rccEnableTIM21(lp) rccEnableAPB2(RCC_APB2ENR_TIM21EN, lp)
/**
- * @brief Disables the TIM9 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the TIM21 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
+#define rccDisableTIM21(lp) rccDisableAPB2(RCC_APB2ENR_TIM21EN, lp)
/**
- * @brief Resets the TIM9 peripheral.
+ * @brief Resets the TIM21 peripheral.
*
* @api
*/
-#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
+#define rccResetTIM21() rccResetAPB2(RCC_APB2RSTR_TIM21RST)
/**
- * @brief Enables the TIM10 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Enables the TIM22 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
+#define rccEnableTIM22(lp) rccEnableAPB2(RCC_APB2ENR_TIM22EN, lp)
/**
- * @brief Disables the TIM10 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
+ * @brief Disables the TIM22 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
-#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+#define rccDisableTIM22(lp) rccDisableAPB2(RCC_APB2ENR_TIM22EN, lp)
/**
- * @brief Resets the TIM10 peripheral.
+ * @brief Resets the TIM22 peripheral.
*
* @api
*/
-#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
-
-/**
- * @brief Enables the TIM10 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
-
-/**
- * @brief Disables the TIM11 peripheral clock.
- * @note The @p lp parameter is ignored in this family.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
-
-/**
- * @brief Resets the TIM11 peripheral.
- *
- * @api
- */
-#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
-
+#define rccResetTIM22() rccResetAPB2(RCC_APB2RSTR_TIM22RST)
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 44c6f1c81..515dc5616 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -41,6 +41,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -56,16 +65,22 @@ #define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_CHANNELS 23
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -85,12 +100,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -106,12 +131,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -119,23 +150,44 @@ #define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -154,15 +206,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -195,6 +260,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -205,23 +279,43 @@ /* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC_DAC1_CH1_DMA_STREAM 0
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
#define STM32_HAS_DAC1_CH2 FALSE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -241,12 +335,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -262,12 +366,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -280,18 +390,26 @@ #define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -310,15 +428,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -330,6 +461,10 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
@@ -355,6 +490,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -365,23 +509,45 @@ /* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_DAC_DAC1_CH1_DMA_STREAM 0
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
#define STM32_HAS_DAC1_CH2 FALSE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -401,12 +567,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -422,12 +598,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -440,18 +622,26 @@ #define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -470,15 +660,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -490,6 +693,10 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
|