diff options
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 345 |
1 files changed, 276 insertions, 69 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 44c6f1c81..515dc5616 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -41,6 +41,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -56,16 +65,22 @@ #define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_CHANNELS 23
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -85,12 +100,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -106,12 +131,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -119,23 +150,44 @@ #define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS 4
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -154,15 +206,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -195,6 +260,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -205,23 +279,43 @@ /* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
-#define STM32_DAC_DAC1_CH1_DMA_STREAM 0
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
#define STM32_HAS_DAC1_CH2 FALSE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -241,12 +335,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -262,12 +366,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -280,18 +390,26 @@ #define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -310,15 +428,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -330,6 +461,10 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
@@ -355,6 +490,15 @@ /* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
+#define STM32_ADC_SUPPORTS_PRESCALER TRUE
+#define STM32_ADC_SUPPORTS_OVERSAMPLING TRUE
+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE
+#define STM32_ADC1_HANDLER Vector70
+#define STM32_ADC1_NUMBER 12
+#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
+ STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN 0x00000000
+
#define STM32_HAS_ADC2 FALSE
#define STM32_HAS_ADC3 FALSE
#define STM32_HAS_ADC4 FALSE
@@ -365,23 +509,45 @@ /* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 FALSE
-#define STM32_DAC_DAC1_CH1_DMA_STREAM 0
+#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_DAC1_CH1_DMA_CHN 0x00000090
#define STM32_HAS_DAC1_CH2 FALSE
#define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/
-#define STM32_ADVANCED_DMA FALSE
-#define STM32_HAS_DMA1 TRUE
-#define STM32_HAS_DMA2 FALSE
-#define STM32_DMA_STREAMS 5
+#define STM32_ADVANCED_DMA TRUE
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector64
+#define STM32_DMA1_CH23_HANDLER Vector68
+#define STM32_DMA1_CH4567_HANDLER Vector6C
+#define STM32_DMA1_CH1_NUMBER 9
+#define STM32_DMA1_CH23_NUMBER 10
+#define STM32_DMA1_CH4567_NUMBER 11
+
+#define STM32_DMA2_NUM_CHANNELS 0
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
+#define STM32_EXTI_NUM_LINES 23
+#define STM32_EXTI_IMR_MASK 0xFF840000U
+
+#define STM32_EXTI_LINE01_HANDLER Vector54
+#define STM32_EXTI_LINE23_HANDLER Vector58
+#define STM32_EXTI_LINE4_15_HANDLER Vector5C
+#define STM32_EXTI_LINE16_HANDLER Vector44
+#define STM32_EXTI_LINE171920_HANDLER Vector48
+#define STM32_EXTI_LINE2122_HANDLER Vector70
+
+#define STM32_EXTI_LINE01_NUMBER 5
+#define STM32_EXTI_LINE23_NUMBER 6
+#define STM32_EXTI_LINE4_15_NUMBER 7
+#define STM32_EXTI_LINE16_NUMBER 1
+#define STM32_EXTI_LINE171920_NUMBER 2
+#define STM32_EXTI_LINE2122_NUMBER 12
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -401,12 +567,22 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM 0
-#define STM32_I2C_I2C1_TX_DMA_STREAM 0
+#define STM32_I2C1_GLOBAL_HANDLER Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER 23
+#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C1_RX_DMA_CHN 0x06000600
+#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_HAS_I2C2 TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM 0
-#define STM32_I2C_I2C2_TX_DMA_STREAM 0
+#define STM32_I2C2_GLOBAL_HANDLER VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER 24
+#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_I2C2_RX_DMA_CHN 0x00070000
+#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_HAS_I2C3 FALSE
@@ -422,12 +598,18 @@ /* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM 0
-#define STM32_SPI_SPI1_TX_DMA_STREAM 0
+#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_SPI1_RX_DMA_CHN 0x00000010
+#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_HAS_SPI2 TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM 0
-#define STM32_SPI_SPI2_TX_DMA_STREAM 0
+#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_SPI2_RX_DMA_CHN 0x00202000
+#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_HAS_SPI3 FALSE
#define STM32_HAS_SPI4 FALSE
@@ -440,18 +622,26 @@ #define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
+#define STM32_TIM2_HANDLER Vector7C
+#define STM32_TIM2_NUMBER 15
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
-
-#define STM32_HAS_TIM20 TRUE
-#define STM32_TIM20_IS_32BITS FALSE
-#define STM32_TIM20_CHANNELS 4
+#define STM32_TIM6_HANDLER Vector84
+#define STM32_TIM6_NUMBER 17
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
-#define STM32_TIM21_CHANNELS 4
+#define STM32_TIM21_CHANNELS 2
+#define STM32_TIM21_HANDLER Vector90
+#define STM32_TIM21_NUMBER 20
+
+#define STM32_HAS_TIM22 TRUE
+#define STM32_TIM22_IS_32BITS FALSE
+#define STM32_TIM22_CHANNELS 2
+#define STM32_TIM22_HANDLER Vector98
+#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
@@ -470,15 +660,28 @@ #define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM 0
-#define STM32_UART_USART1_TX_DMA_STREAM 0
+#define STM32_USART1_HANDLER VectorAC
+#define STM32_USART1_NUMBER 27
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
+ STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00030300
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
+ STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_HAS_USART2 TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM 0
-#define STM32_UART_USART2_TX_DMA_STREAM 0
+#define STM32_USART2_HANDLER VectorB0
+#define STM32_USART2_NUMBER 28
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
+ STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00440000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
+ STM32_DMA_STREAM_ID_MSK(1, 7)
+#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
@@ -490,6 +693,10 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE
#define STM32_USB_PMA_SIZE 1024
#define STM32_USB_HAS_BCDR TRUE
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
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