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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-03 23:22:48 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-03 23:22:48 +0000 |
| commit | 98acc95556666584892b655b0bd1e1b44fc12780 (patch) | |
| tree | c180e8d60c10f203436fd311c6a0ab35123cf792 /os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | |
| parent | a374e159feade020715a895fee28b49602ace451 (diff) | |
| download | ChibiOS-98acc95556666584892b655b0bd1e1b44fc12780.tar.gz ChibiOS-98acc95556666584892b655b0bd1e1b44fc12780.tar.bz2 ChibiOS-98acc95556666584892b655b0bd1e1b44fc12780.zip | |
Extended STM32L0xx support
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9408 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 18967a588..5396fe1b1 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -345,6 +345,31 @@ * @api
*/
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+
+/**
+ * @brief Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Disables the I2C3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
/** @} */
/**
@@ -430,6 +455,7 @@ * @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
/**
* @brief Enables the TIM6 peripheral clock.
*
@@ -456,6 +482,31 @@ #define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
* @brief Enables the TIM21 peripheral clock.
*
* @param[in] lp low power enable flag
@@ -586,6 +637,56 @@ #define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1ENR_USART4EN)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1ENR_USART5EN)
+
+/**
* @brief Enables the LPUART1 peripheral clock.
*
* @param[in] lp low power enable flag
|