From 98acc95556666584892b655b0bd1e1b44fc12780 Mon Sep 17 00:00:00 2001
From: Rocco Marco Guglielmi <roccomarco.guglielmi@live.com>
Date: Tue, 3 May 2016 23:22:48 +0000
Subject: Extended STM32L0xx support

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9408 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 101 +++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

(limited to 'os/hal/ports/STM32/STM32L0xx/stm32_rcc.h')

diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
index 18967a588..5396fe1b1 100644
--- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
@@ -345,6 +345,31 @@
  * @api
  */
 #define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+
+/**
+ * @brief   Enables the I2C3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief   Disables the I2C3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp)
+
+/**
+ * @brief   Resets the I2C3 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
 /** @} */
 
 /**
@@ -430,6 +455,7 @@
  * @api
  */
 #define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
 /**
  * @brief   Enables the TIM6 peripheral clock.
  *
@@ -455,6 +481,31 @@
  */
 #define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
 
+/**
+ * @brief   Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief   Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief   Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
 /**
  * @brief   Enables the TIM21 peripheral clock.
  *
@@ -585,6 +636,56 @@
  */
 #define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
 
+/**
+ * @brief   Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief   Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_USART4EN, lp)
+
+/**
+ * @brief   Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1ENR_USART4EN)
+
+/**
+ * @brief   Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief   Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_USART5EN, lp)
+
+/**
+ * @brief   Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1ENR_USART5EN)
+
 /**
  * @brief   Enables the LPUART1 peripheral clock.
  *
-- 
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