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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-07-26 06:17:10 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2015-07-26 06:17:10 +0000 |
| commit | c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c (patch) | |
| tree | 53c0ebd122fe369cc08b4ed3bf885ba39e9a07f1 /os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c | |
| parent | b05e7e8c4464bda8fecd21ff80086a34edf9292c (diff) | |
| download | ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.tar.gz ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.tar.bz2 ChibiOS-c96f0b2bbf7c911a5d23d6c9920f1c6f4d766c8c.zip | |
More STM32L0xx support files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8104 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c | 265 |
1 files changed, 265 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c new file mode 100644 index 000000000..36731f9bb --- /dev/null +++ b/os/hal/ports/STM32/STM32L0xx/ext_lld_isr.c @@ -0,0 +1,265 @@ +/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file STM32L0xx/ext_lld_isr.c
+ * @brief STM32L0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EXTI[0]...EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE01_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 0) | (1 << 1));
+ EXTI->PR = pr;
+ if (pr & (1 << 0))
+ EXTD1.config->channels[0].cb(&EXTD1, 0);
+ if (pr & (1 << 1))
+ EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[2]...EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE23_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 2) | (1 << 3));
+ EXTI->PR = pr;
+ if (pr & (1 << 2))
+ EXTD1.config->channels[2].cb(&EXTD1, 2);
+ if (pr & (1 << 3))
+ EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE4_15_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
+ (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
+ (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15));
+ EXTI->PR = pr;
+ if (pr & (1 << 4))
+ EXTD1.config->channels[4].cb(&EXTD1, 4);
+ if (pr & (1 << 5))
+ EXTD1.config->channels[5].cb(&EXTD1, 5);
+ if (pr & (1 << 6))
+ EXTD1.config->channels[6].cb(&EXTD1, 6);
+ if (pr & (1 << 7))
+ EXTD1.config->channels[7].cb(&EXTD1, 7);
+ if (pr & (1 << 8))
+ EXTD1.config->channels[8].cb(&EXTD1, 8);
+ if (pr & (1 << 9))
+ EXTD1.config->channels[9].cb(&EXTD1, 9);
+ if (pr & (1 << 10))
+ EXTD1.config->channels[10].cb(&EXTD1, 10);
+ if (pr & (1 << 11))
+ EXTD1.config->channels[11].cb(&EXTD1, 11);
+ if (pr & (1 << 12))
+ EXTD1.config->channels[12].cb(&EXTD1, 12);
+ if (pr & (1 << 13))
+ EXTD1.config->channels[13].cb(&EXTD1, 13);
+ if (pr & (1 << 14))
+ EXTD1.config->channels[14].cb(&EXTD1, 14);
+ if (pr & (1 << 15))
+ EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE16_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & (1 << 16);
+ EXTI->PR = pr;
+ if (pr & (1 << 16))
+ EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC, CSS).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE171920_HANDLER) {
+ uint32_t pr;
+
+ OSAL_IRQ_PROLOGUE();
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 17) | (1 << 19) | (1 << 20));
+ EXTI->PR = pr;
+ if (pr & (1 << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1 << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1 << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+/**
+ * @brief EXTI[20],EXTI[21] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_EXTI_LINE2122_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 21) | (1 << 22));
+ EXTI->PR = pr;
+ if (pr & (1 << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1 << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+ nvicEnableVector(STM32_EXTI_LINE01_NUMBER,
+ STM32_EXT_EXTI0_1_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE23_NUMBER,
+ STM32_EXT_EXTI2_3_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE4_15_NUMBER,
+ STM32_EXT_EXTI4_15_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE16_NUMBER,
+ STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(STM32_EXTI_LINE171920_NUMBER,
+ STM32_EXT_EXTI17_20_IRQ_PRIORITY);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be enabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+ }
+#else
+ nvicEnableVector(STM32_EXTI_LINE2122_NUMBER,
+ STM32_EXT_EXTI21_22_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+ nvicDisableVector(STM32_EXTI_LINE01_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE23_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE4_15_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE16_NUMBER);
+ nvicDisableVector(STM32_EXTI_LINE2122_NUMBER);
+#if HAL_USE_ADC
+ /* If the ADC is not working then the vector can be disabled.*/
+ if (ADCD1.state == ADC_STOP) {
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+ }
+#else
+ nvicDisableVector(STM32_EXTI_LINE171920_NUMBER);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
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