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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-11-21 13:56:20 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-11-21 13:56:20 +0000 |
| commit | af649428322234d8816efc0d8ace6c4f481d8250 (patch) | |
| tree | 373b3cdea94f482b92680ef382cb0ddccbd4b5c6 /os/hal/ports/STM32/STM32F7xx | |
| parent | 2c5ca8e4ad494e8cbc9b36dede48dc0a9b47691b (diff) | |
| download | ChibiOS-af649428322234d8816efc0d8ace6c4f481d8250.tar.gz ChibiOS-af649428322234d8816efc0d8ace6c4f481d8250.tar.bz2 ChibiOS-af649428322234d8816efc0d8ace6c4f481d8250.zip | |
Added CAN3 support to the STM32 CANv1 driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9942 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 25 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 12 |
2 files changed, 37 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index d55e4afa5..27e52e3a4 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -522,6 +522,31 @@ * @api
*/
#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST)
+
+/**
+ * @brief Resets the CAN3 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST)
+
+/**
+ * @brief Enables the CAN3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp)
+
+/**
+ * @brief Disables the CAN3 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN3(lp) rccDisableAPB1(RCC_APB1ENR_CAN3EN, lp)
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index 30a361151..ff06fe86e 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -86,6 +86,18 @@ #define STM32_CAN2_RX1_NUMBER 65
#define STM32_CAN2_SCE_NUMBER 66
+#define STM32_CAN3_MAX_FILTERS 14
+
+#define STM32_HAS_CAN3 TRUE
+#define STM32_CAN3_TX_HANDLER Vector1E0
+#define STM32_CAN3_RX0_HANDLER Vector1E4
+#define STM32_CAN3_RX1_HANDLER Vector1E8
+#define STM32_CAN3_SCE_HANDLER Vector1EC
+#define STM32_CAN3_TX_NUMBER 104
+#define STM32_CAN3_RX0_NUMBER 105
+#define STM32_CAN3_RX1_NUMBER 106
+#define STM32_CAN3_SCE_NUMBER 107
+
/* DAC attributes.*/
#define STM32_HAS_DAC1_CH1 TRUE
#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|