Added F413 board, demo and revised HAL code, to be tested.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12031 110e8d01-0319-4d1e-a829-52ad28d1bb01

3 files changed, 111 insertions, 885 deletions

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 542e08879..1cfa9c49c 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -256,9 +256,15 @@ void stm32_clock_init(void) {
 #endif /* STM32_ACTIVATE_PLLSAI */

 

   /* Other clock-related settings (dividers, MCO etc).*/

+#if !defined(STM32F413xx)

   RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

               STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |

               STM32_HPRE;

+#else

+  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

+                              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |

+              STM32_HPRE;

+#endif

 

 #if STM32_HAS_RCC_DCKCFGR

   /* DCKCFGR register initialization, note, must take care of the _OFF

@@ -271,7 +277,8 @@ void stm32_clock_init(void) {
 #if STM32_SAI1SEL != STM32_SAI1SEL_OFF

     dckcfgr |= STM32_SAI1SEL;

 #endif

-#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF

+#if (STM32_ACTIVATE_PLLSAI == TRUE) &&                                      \

+    (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF)

     dckcfgr |= STM32_PLLSAIDIVR;

 #endif

 #if defined(STM32F469xx) || defined(STM32F479xx)

@@ -279,9 +286,15 @@ void stm32_clock_init(void) {
      DCKCFGR register.*/

     dckcfgr |= STM32_CK48MSEL;

 #endif

+#if !defined(STM32F413xx)

     RCC->DCKCFGR = dckcfgr |

                    STM32_TIMPRE | STM32_PLLSAIDIVR |

                    STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;

+#else

+    RCC->DCKCFGR = dckcfgr |

+                   STM32_TIMPRE |

+                   STM32_PLLDIVR | STM32_PLLI2SDIVR;

+#endif

   }

 #endif

 

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
index e075816c8..531984060 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -43,8 +43,6 @@
 #ifndef HAL_LLD_TYPE1_H

 #define HAL_LLD_TYPE1_H

 

-#include "stm32_registry.h"

-

 /*===========================================================================*/

 /* Driver constants.                                                         */

 /*===========================================================================*/

@@ -1026,8 +1024,8 @@
 #endif /* !defined(STM32F4XX) */

 

 /**

- * @brief   Maximum frequency thresholds and wait states for flash access.

- * @note    The values are valid for 2.7V to 3.6V supply range.

+ * @name    Maximum frequency thresholds and wait states for flash access.

+ * @{

  */

 #if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \

     defined(STM32F40_41xxx)  || defined(STM32F446xx)     ||                 \

@@ -1253,6 +1251,7 @@
 #error "invalid VDD voltage specified"

 #endif

 #endif /* STM32F2XX */

+/** @} */

 

 /*

  * HSI related checks.

@@ -1283,6 +1282,11 @@
 #error "HSI not enabled, required by STM32_I2SSRC"

 #endif

 

+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLI2S) &&                          \

+    (STM32_PLLSRC == STM32_PLLSRC_HSI)

+#error "HSI not enabled, required by STM32_I2SSRC"

+#endif

+

 #if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) ||                             \

      (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) &&                            \

      (STM32_PLLSRC == STM32_PLLSRC_HSI)

@@ -1341,6 +1345,11 @@
 #error "HSE not enabled, required by STM32_I2SSRC"

 #endif

 

+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) &&                          \

+    (STM32_PLLSRC == STM32_PLLSRC_HSE)

+#error "HSE not enabled, required by STM32_PLLI2SSRC"

+#endif

+

 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV

 #error "HSE not enabled, required by STM32_RTCSEL"

 #endif

@@ -1741,7 +1750,7 @@
 #if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)

 #if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)

 #define STM32_PLLI2SCLKIN           (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)

-#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN

+#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN

 #define STM32_PLLI2SCLKIN           (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)

 #else

 #error "invalid STM32_PLLI2SSRC value specified"

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
index 5bf326b92..607d3e7ab 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
@@ -15,7 +15,7 @@
 */

 

 /**

- * @file    STM32F4xx/hal_lld.h

+ * @file    STM32F4xx/hal_lld_type2.h

  * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver header.

  * @pre     This module requires the following macros to be defined in the

  *          @p board.h file:

@@ -26,24 +26,15 @@
  *          - STM32_VDD (as hundredths of Volt).

  *          .

  *          One of the following macros must also be defined:

- *          - STM32F2XX for High-performance STM32F2 devices.

- *          - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,

- *            STM32F446xx for High-performance STM32F4 devices of

- *            Foundation line.

- *          - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx

- *            for High-performance STM32F4 devices of Access line.

- *          - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx, 

- *            STM32F479xx for High-performance STM32F4 devices of Advanced line.

+ *          - STM32F413xx for High-performance STM32F4 devices of Access line.

  *          .

  *

  * @addtogroup HAL

  * @{

  */

 

-#ifndef HAL_LLD_H

-#define HAL_LLD_H

-

-#include "stm32_registry.h"

+#ifndef HAL_LLD_TYPE2_H

+#define HAL_LLD_TYPE2_H

 

 /*===========================================================================*/

 /* Driver constants.                                                         */

@@ -58,66 +49,9 @@
  * @name    Platform identification macros

  * @{

  */

-#if defined(STM32F205xx) || defined(__DOXYGEN__)

-#define PLATFORM_NAME           "STM32F205 High Performance"

-

-#elif defined(STM32F207xx)

-#define PLATFORM_NAME           "STM32F207 High Performance"

-

-#elif defined(STM32F215xx)

-#define PLATFORM_NAME           "STM32F215 High Performance"

-

-#elif defined(STM32F217xx)

-#define PLATFORM_NAME           "STM32F217 High Performance"

-

-#elif defined(STM32F401xx)

-#define PLATFORM_NAME           "STM32F401 High Performance with DSP and FPU"

-

-#elif defined(STM32F405xx)

-#define PLATFORM_NAME           "STM32F405 High Performance with DSP and FPU"

-

-#elif defined(STM32F407xx)

-#define PLATFORM_NAME           "STM32F407 High Performance with DSP and FPU"

-

-#elif defined(STM32F410xx)

-#define PLATFORM_NAME           "STM32F410 High Performance with DSP and FPU"

-

-#elif defined(STM32F411xx)

-#define PLATFORM_NAME           "STM32F411 High Performance with DSP and FPU"

-

-#elif defined(STM32F412xx)

-#define PLATFORM_NAME           "STM32F412 High Performance with DSP and FPU"

-

-#elif defined(STM32F413xx)

+#if defined(STM32F413xx)

 #define PLATFORM_NAME           "STM32F413 High Performance with DSP and FPU"

 

-#elif defined(STM32F415xx)

-#define PLATFORM_NAME           "STM32F415 High Performance with DSP and FPU"

-

-#elif defined(STM32F417xx)

-#define PLATFORM_NAME           "STM32F417 High Performance with DSP and FPU"

-

-#elif defined(STM32F427xx)

-#define PLATFORM_NAME           "STM32F427 High Performance with DSP and FPU"

-

-#elif defined(STM32F429xx)

-#define PLATFORM_NAME           "STM32F429 High Performance with DSP and FPU"

-

-#elif defined(STM32F437xx)

-#define PLATFORM_NAME           "STM32F437 High Performance with DSP and FPU"

-

-#elif defined(STM32F439xx)

-#define PLATFORM_NAME           "STM32F439 High Performance with DSP and FPU"

-

-#elif defined(STM32F446xx)

-#define PLATFORM_NAME           "STM32F446 High Performance with DSP and FPU"

-

-#elif defined(STM32F469xx)

-#define PLATFORM_NAME           "STM32F469 High Performance with DSP and FPU"

-

-#elif defined(STM32F479xx)

-#define PLATFORM_NAME           "STM32F479 High Performance with DSP and FPU"

-

 #else

 #error "STM32F2xx/F4xx device not specified"

 #endif

@@ -127,13 +61,12 @@
  * @name    Absolute Maximum Ratings

  * @{

  */

-#if defined(STM32F427xx) || defined(STM32F437xx) ||                         \

-    defined(STM32F429xx) || defined(STM32F439xx) ||                         \

-    defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)

+

+#if defined(STM32F413xx) || defined(__DOXYGEN__)

 /**

  * @brief   Absolute maximum system clock.

  */

-#define STM32_SYSCLK_MAX        180000000

+#define STM32_SYSCLK_MAX        100000000

 

 /**

  * @brief   Maximum HSE clock frequency.

@@ -151,7 +84,7 @@
 #define STM32_HSECLK_MIN        4000000

 

 /**

- * @brief   Minimum HSE clock frequency.

+ * @brief   Minimum HSE clock frequency using an external source.

  */

 #define STM32_HSECLK_BYP_MIN    1000000

 

@@ -161,7 +94,7 @@
 #define STM32_LSECLK_MAX        32768

 

 /**

- * @brief   Maximum LSE clock frequency.

+ * @brief   Maximum LSE clock frequency using an external source.

  */

 #define STM32_LSECLK_BYP_MAX    1000000

 

@@ -188,12 +121,12 @@
 /**

  * @brief   Minimum PLLs VCO clock frequency.

  */

-#define STM32_PLLVCO_MIN        192000000

+#define STM32_PLLVCO_MIN        100000000

 

 /**

  * @brief   Maximum PLL output clock frequency.

  */

-#define STM32_PLLOUT_MAX        180000000

+#define STM32_PLLOUT_MAX        100000000

 

 /**

  * @brief   Minimum PLL output clock frequency.

@@ -201,133 +134,20 @@
 #define STM32_PLLOUT_MIN        24000000

 

 /**

- * @brief   Maximum PLLI2S output clock frequency.

- */

-#define STM32_PLLI2SOUT_MAX     216000000

-

-/**

- * @brief   Maximum PLLSAI output clock frequency.

- */

-#define STM32_PLLSAIOUT_MAX     216000000

-

-/**

  * @brief   Maximum APB1 clock frequency.

  */

-#define STM32_PCLK1_MAX         (STM32_PLLOUT_MAX / 4)

+#define STM32_PCLK1_MAX         50000000

 

 /**

  * @brief   Maximum APB2 clock frequency.

  */

-#define STM32_PCLK2_MAX         (STM32_PLLOUT_MAX / 2)

+#define STM32_PCLK2_MAX         100000000

 

 /**

  * @brief   Maximum SPI/I2S clock frequency.

  */

-#define STM32_SPII2S_MAX        45000000

-#endif

-

-#if defined(STM32F40_41xxx)

-#define STM32_SYSCLK_MAX        168000000

-#define STM32_HSECLK_MAX        26000000

-#define STM32_HSECLK_BYP_MAX    50000000

-#define STM32_HSECLK_MIN        4000000

-#define STM32_HSECLK_BYP_MIN    1000000

-#define STM32_LSECLK_MAX        32768

-#define STM32_LSECLK_BYP_MAX    1000000

-#define STM32_LSECLK_MIN        32768

-#define STM32_PLLIN_MAX         2100000

-#define STM32_PLLIN_MIN         950000

-#define STM32_PLLVCO_MAX        432000000

-#define STM32_PLLVCO_MIN        192000000

-#define STM32_PLLOUT_MAX        168000000

-#define STM32_PLLOUT_MIN        24000000

-#define STM32_PCLK1_MAX         42000000

-#define STM32_PCLK2_MAX         84000000

-#define STM32_SPII2S_MAX        42000000

-#endif

-

-#if defined(STM32F401xx)

-#define STM32_SYSCLK_MAX        84000000

-#define STM32_HSECLK_MAX        26000000

-#define STM32_HSECLK_BYP_MAX    50000000

-#define STM32_HSECLK_MIN        4000000

-#define STM32_HSECLK_BYP_MIN    1000000

-#define STM32_LSECLK_MAX        32768

-#define STM32_LSECLK_BYP_MAX    1000000

-#define STM32_LSECLK_MIN        32768

-#define STM32_PLLIN_MAX         2100000

-#define STM32_PLLIN_MIN         950000

-#define STM32_PLLVCO_MAX        432000000

-#define STM32_PLLVCO_MIN        192000000

-#define STM32_PLLOUT_MAX        84000000

-#define STM32_PLLOUT_MIN        24000000

-#define STM32_PCLK1_MAX         42000000

-#define STM32_PCLK2_MAX         84000000

-#define STM32_SPII2S_MAX        42000000

-#endif

-

-#if defined(STM32F410xx) || defined(STM32F411xx) ||                         \

-    defined(STM32F412xx) || defined(STM32F413xx)

-#define STM32_SYSCLK_MAX        100000000

-#define STM32_HSECLK_MAX        26000000

-#define STM32_HSECLK_BYP_MAX    50000000

-#define STM32_HSECLK_MIN        4000000

-#define STM32_HSECLK_BYP_MIN    1000000

-#define STM32_LSECLK_MAX        32768

-#define STM32_LSECLK_BYP_MAX    1000000

-#define STM32_LSECLK_MIN        32768

-#define STM32_PLLIN_MAX         2100000

-#define STM32_PLLIN_MIN         950000

-#define STM32_PLLVCO_MAX        432000000

-#define STM32_PLLVCO_MIN        100000000

-#define STM32_PLLOUT_MAX        100000000

-#define STM32_PLLOUT_MIN        24000000

-#define STM32_PCLK1_MAX         50000000

-#define STM32_PCLK2_MAX         100000000

 #define STM32_SPII2S_MAX        50000000

 #endif

-

-#if defined(STM32F446xx)

-#define STM32_SYSCLK_MAX        180000000

-#define STM32_HSECLK_MAX        26000000

-#define STM32_HSECLK_BYP_MAX    50000000

-#define STM32_HSECLK_MIN        4000000

-#define STM32_HSECLK_BYP_MIN    1000000

-#define STM32_LSECLK_MAX        32768

-#define STM32_LSECLK_BYP_MAX    1000000

-#define STM32_LSECLK_MIN        32768

-#define STM32_PLLIN_MAX         2100000

-#define STM32_PLLIN_MIN         950000

-#define STM32_PLLVCO_MAX        432000000

-#define STM32_PLLVCO_MIN        100000000

-#define STM32_PLLOUT_MAX        180000000

-#define STM32_PLLOUT_MIN        12500000

-#define STM32_PLLI2SOUT_MAX     216000000

-#define STM32_PLLSAIOUT_MAX     216000000

-#define STM32_PCLK1_MAX         (STM32_PLLOUT_MAX / 4)

-#define STM32_PCLK2_MAX         (STM32_PLLOUT_MAX / 2)

-#define STM32_SPII2S_MAX        45000000

-#endif

-

-#if defined(STM32F2XX)

-#define STM32_SYSCLK_MAX        120000000

-#define STM32_HSECLK_MAX        26000000

-#define STM32_HSECLK_BYP_MAX    26000000

-#define STM32_HSECLK_MIN        1000000

-#define STM32_HSECLK_BYP_MIN    1000000

-#define STM32_LSECLK_MAX        32768

-#define STM32_LSECLK_BYP_MAX    1000000

-#define STM32_LSECLK_MIN        32768

-#define STM32_PLLIN_MAX         2000000

-#define STM32_PLLIN_MIN         950000

-#define STM32_PLLVCO_MAX        432000000

-#define STM32_PLLVCO_MIN        192000000

-#define STM32_PLLOUT_MAX        120000000

-#define STM32_PLLOUT_MIN        24000000

-#define STM32_PCLK1_MAX         30000000

-#define STM32_PCLK2_MAX         60000000

-#define STM32_SPII2S_MAX        30000000

-#endif

 /** @} */

 

 /**

@@ -412,10 +232,6 @@
 #define STM32_MCO1SEL_HSE       (2 << 21)   /**< HSE clock on MCO1 pin.     */

 #define STM32_MCO1SEL_PLL       (3 << 21)   /**< PLL clock on MCO1 pin.     */

 

-#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2CSRC mask.               */

-#define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */

-#define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */

-

 #define STM32_MCO1PRE_MASK      (7 << 24)   /**< MCO1PRE mask.              */

 #define STM32_MCO1PRE_DIV1      (0 << 24)   /**< MCO1 divided by 1.         */

 #define STM32_MCO1PRE_DIV2      (4 << 24)   /**< MCO1 divided by 2.         */

@@ -442,11 +258,6 @@
  */

 #define STM32_PLLI2SM_MASK      (31 << 0)   /**< PLLI2SM mask.              */

 #define STM32_PLLI2SN_MASK      (511 << 6)  /**< PLLI2SN mask.              */

-#define STM32_PLLI2SP_MASK      (3 << 16)   /**< PLLI2SP mask.              */

-#define STM32_PLLI2SP_DIV2      (0 << 16)   /**< PLLI2S clock divided by 2. */

-#define STM32_PLLI2SP_DIV4      (1 << 16)   /**< PLLI2S clock divided by 4. */

-#define STM32_PLLI2SP_DIV6      (2 << 16)   /**< PLLI2S clock divided by 6. */

-#define STM32_PLLI2SP_DIV8      (3 << 16)   /**< PLLI2S clock divided by 8. */

 #define STM32_PLLI2SSRC_MASK    (1 << 22)   /**< PLLI2SSRC mask.            */

 #define STM32_PLLI2SSRC_PLLSRC  (0 << 22)   /**< PLLI2SSRC is selected PLL

                                                  source.                    */

@@ -456,21 +267,6 @@
 /** @} */

 

 /**

- * @name    RCC_PLLSAICFGR register bits definitions

- * @{

- */

-#define STM32_PLLSAIM_MASK      (31 << 0)   /**< PLLSAIM mask.              */

-#define STM32_PLLSAIN_MASK      (511 << 6)  /**< PLLSAIN mask.              */

-#define STM32_PLLSAIP_MASK      (3 << 16)   /**< PLLSAIP mask.              */

-#define STM32_PLLSAIP_DIV2      (0 << 16)   /**< PLLSAI clock divided by 2. */

-#define STM32_PLLSAIP_DIV4      (1 << 16)   /**< PLLSAI clock divided by 4. */

-#define STM32_PLLSAIP_DIV6      (2 << 16)   /**< PLLSAI clock divided by 6. */

-#define STM32_PLLSAIP_DIV8      (3 << 16)   /**< PLLSAI clock divided by 8. */

-#define STM32_PLLSAIQ_MASK      (15 << 24)  /**< PLLSAIQ mask.              */

-#define STM32_PLLSAIR_MASK      (7 << 28)   /**< PLLSAIR mask.              */

-/** @} */

-

-/**

  * @name    RCC_BDCR register bits definitions

  * @{

  */

@@ -485,20 +281,8 @@
  * @name    RCC_DCKCFGR register bits definitions

  * @{

  */

-#if !defined(STM32F413xx) || defined(_DOXYGEN__)

-#define STM32_PLLI2SDIVQ_MASK   (31 << 0)   /**< PLLI2SDIVQ mask.           */

-#define STM32_PLLSAIDIVQ_MASK   (31 << 8)   /**< PLLSAIDIVQ mask.           */

-#else

-#define STM32_PLLI2SDIVR_MASK   (31 << 0)

-#define STM32_PLLSAIDIVR_MASK   (31 << 8)

-#endif

-

-#define STM32_PLLSAIDIVR_MASK   (3 << 16)   /**< PLLSAIDIVR mask.           */

-#define STM32_PLLSAIDIVR_DIV2   (0 << 16)   /**< LCD_CLK is R divided by 2. */

-#define STM32_PLLSAIDIVR_DIV4   (1 << 16)   /**< LCD_CLK is R divided by 4. */

-#define STM32_PLLSAIDIVR_DIV8   (2 << 16)   /**< LCD_CLK is R divided by 8. */

-#define STM32_PLLSAIDIVR_DIV16  (3 << 16)   /**< LCD_CLK is R divided by 16.*/

-#define STM32_PLLSAIDIVR_OFF    0xFFFFFFFFU /**< LCD CLK is not required.   */

+#define STM32_PLLI2SDIVR_MASK   (31 << 0)   /**< PLLI2SDIVR mask.           */

+#define STM32_PLLDIVR_MASK      (31 << 8)   /**< PLLDIVR mask.              */

 

 #define STM32_SAI1SEL_MASK      (3 << 20)   /**< SAI1SEL mask.              */

 #define STM32_SAI1SEL_PLLSAI    (0 << 20)   /**< SAI1 source is PLLSAI.     */

@@ -527,38 +311,24 @@
 #define STM32_I2S2SEL_AFIN      (1 << 27)   /**< I2S2 source is AF Input.   */

 #define STM32_I2S2SEL_MCO1      (2 << 27)   /**< I2S2 source is MCO1.       */

 #define STM32_I2S2SEL_OFF       0xFFFFFFFFU /**< I2S2 clock is not required.*/

-

-#define STM32_DSISEL_MASK       (1 << 28)   /**< DSISEL mask.               */

-#define STM32_DSISEL_PHY        (0 << 28)   /**< DSI source is DSI-PSY.     */

-#define STM32_DSISEL_PLLR       (1 << 28)   /**< DSI source is PLLR.        */

 /** @} */

 

 /**

  * @name    RCC_DCKCFGR2 register bits definitions

  * @{

  */

-#define STM32_I2C1SEL_MASK      (3 << 22)   /**< I2C1SEL mask.              */

-#define STM32_I2C1SEL_PCLK1     (0 << 22)   /**< I2C1 source is APB/PCLK1.  */

-#define STM32_I2C1SEL_SYSCLK    (1 << 22)   /**< I2C1 source is SYSCLK.     */

-#define STM32_I2C1SEL_HSI       (2 << 22)   /**< I2C1 source is HSI.        */

-

-#define STM32_CECSEL_MASK       (1 << 26)   /**< CECSEL mask.               */

-#define STM32_CECSEL_LSE        (0 << 26)   /**< CEC source is LSE.         */

-#define STM32_CECSEL_HSIDIV488  (1 << 26)   /**< CEC source is HSI/488.     */

+#define STM32_I2CFMP1SEL_MASK   (3 << 22)   /**< I2CFMP1SEL mask.              */

+#define STM32_I2CFMP1SEL_PCLK1  (0 << 22)   /**< I2C1 source is APB/PCLK1.  */

+#define STM32_I2CFMP1SEL_SYSCLK (1 << 22)   /**< I2C1 source is SYSCLK.     */

+#define STM32_I2CFMP1SEL_HSI    (2 << 22)   /**< I2C1 source is HSI.        */

 

 #define STM32_CK48MSEL_MASK     (1 << 27)   /**< CK48MSEL mask.             */

 #define STM32_CK48MSEL_PLL      (0 << 27)   /**< PLL48CLK source is PLL.    */

-#define STM32_CK48MSEL_PLLALT   (1 << 27)   /**< PLL48CLK source is PLLSAI

-                                                 or PLLI2S depending on

-                                                 device.                    */

+#define STM32_CK48MSEL_PLLI2S   (1 << 27)   /**< PLL48CLK source is PLLI2S. */

 

-#define STM32_SDMMCSEL_MASK     (1 << 28)   /**< SDMMCSEL mask.             */

-#define STM32_SDMMCSEL_PLL48CLK (0 << 28)   /**< SDMMC source is PLL48CLK.  */

-#define STM32_SDMMCSEL_SYSCLK   (1 << 28)   /**< SDMMC source is SYSCLK.    */

-

-#define STM32_SPDIFSEL_MASK     (1 << 29)   /**< SPDIFSEL mask.             */

-#define STM32_SPDIFSEL_PLLI2S   (0 << 29)   /**< SPDIF source is PLLI2S.    */

-#define STM32_SPDIFSEL_PLL      (1 << 29)   /**< SPDIF source is PLL.       */

+#define STM32_SDIOSEL_MASK      (1 << 28)   /**< SDIOSEL mask.              */

+#define STM32_SDIOSEL_PLL48CLK  (0 << 28)   /**< SDIO source is PLL48CLK.   */

+#define STM32_SDIOSEL_SYSCLK    (1 << 28)   /**< SDIO source is SYSCLK.     */

 

 #define STM32_LPTIM1SEL_MASK    (3 << 30)   /**< LPTIM1 mask.               */

 #define STM32_LPTIM1SEL_APB     (0 << 30)   /**< LPTIM1 source is APB.      */

@@ -649,7 +419,6 @@
 #define STM32_SW                    STM32_SW_PLL

 #endif

 

-#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /**

  * @brief   Clock source for the PLLs.

  * @note    This setting has only effect if the PLL is selected as the

@@ -674,141 +443,87 @@
 /**

  * @brief   PLLN multiplier value.

  * @note    The allowed values are 192..432.

- * @note    The default value is calculated for a 168MHz system clock from

+ * @note    The default value is calculated for a 96MHz system clock from

  *          an external 8MHz HSE clock.

  */

 #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLN_VALUE            336

+#define STM32_PLLN_VALUE            384

 #endif

 

 /**

  * @brief   PLLP divider value.

  * @note    The allowed values are 2, 4, 6, 8.

- * @note    The default value is calculated for a 168MHz system clock from

+ * @note    The default value is calculated for a 96MHz system clock from

  *          an external 8MHz HSE clock.

  */

 #if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLP_VALUE            2

+#define STM32_PLLP_VALUE            4

 #endif

 

 /**

  * @brief   PLLQ multiplier value.

  * @note    The allowed values are 2..15.

- * @note    The default value is calculated for a 168MHz system clock from

- *          an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLQ_VALUE            7

-#endif

-

-/**

- * @brief   PLLR divider value.

- * @note    The allowed values are 2..7.

  * @note    The default value is calculated for a 96MHz system clock from

  *          an external 8MHz HSE clock.

  */

-#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLR_VALUE             4

-#endif

-

-#else /* !defined(STM32F4XX) */

-/**

- * @brief   Clock source for the PLLs.

- * @note    This setting has only effect if the PLL is selected as the

- *          system clock source.

- * @note    The default value is calculated for a 120MHz system clock from

- *          an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)

-#define STM32_PLLSRC                STM32_PLLSRC_HSE

-#endif

-

-/**

- * @brief   PLLM divider value.

- * @note    The allowed values are 2..63.

- * @note    The default value is calculated for a 120MHz system clock from

- *          an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLM_VALUE            8

+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLQ_VALUE            8

 #endif

 

 /**

- * @brief   PLLN multiplier value.

- * @note    The allowed values are 192..432.

- * @note    The default value is calculated for a 120MHz system clock from

- *          an external 8MHz HSE clock.

+ * @brief   AHB prescaler value.

  */

-#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLN_VALUE            240

+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)

+#define STM32_HPRE                  STM32_HPRE_DIV1

 #endif

 

 /**

- * @brief   PLLP divider value.

- * @note    The allowed values are 2, 4, 6, 8.

- * @note    The default value is calculated for a 120MHz system clock from

- *          an external 8MHz HSE clock.

+ * @brief   APB1 prescaler value.

  */

-#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLP_VALUE            2

+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)

+#define STM32_PPRE1                 STM32_PPRE1_DIV4

 #endif

 

 /**

- * @brief   PLLQ multiplier value.

- * @note    The allowed values are 2..15.

- * @note    The default value is calculated for a 120MHz system clock from

- *          an external 8MHz HSE clock.

+ * @brief   APB2 prescaler value.

  */

-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLQ_VALUE            5

-#endif

-#endif /* !defined(STM32F4XX) */

-

-/**

- * @brief   I2S clock source (post-PLL).

- * @note    Not all devices have this setting, it is alternative to

- *          @p STM32_PLLI2SSRC.

-  */

-#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)

-#define STM32_I2SSRC                STM32_I2SSRC_CKIN

+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)

+#define STM32_PPRE2                 STM32_PPRE2_DIV2

 #endif

 

 /**

  * @brief   I2S clock source (pre-PLL).

- * @note    Not all devices have this setting, it is alternative to

- *          @p STM32_I2SSRC.

  */

 #if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)

-#define STM32_PLLI2SSRC             STM32_PLLI2SSRC_CKIN

+#define STM32_PLLI2SSRC             STM32_PLLI2SSRC_PLLSRC

 #endif

 

 /**

  * @brief   I2S external clock value, zero if not present.

- * @note    Not all devices have this setting.

  */

 #if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)

 #define STM32_I2SCKIN_VALUE         0

 #endif

 

 /**

- * @brief   PLLI2SN multiplier value.

- * @note    The allowed values are 192..432, except for

- *          STM32F446 where values are 50...432.

+ * @brief   PLLI2SM divider value.

+ * @note    The allowed values are 2..63.

  * @note    The default value is calculated for a 96MHz I2S clock 

  *          output from an external 8MHz HSE clock.

  */

-#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SN_VALUE         192

+#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLI2SM_VALUE         8

 #endif

 

 /**

- * @brief   PLLI2SM divider value.

- * @note    The allowed values are 2..63.

+ * @brief   PLLI2SN multiplier value.

+ * @note    The allowed values are 192..432, except for

+ *          STM32F446 where values are 50...432.

  * @note    The default value is calculated for a 96MHz I2S clock 

  *          output from an external 8MHz HSE clock.

  */

-#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SM_VALUE         4

+#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLI2SN_VALUE         192

 #endif

 

 /**

@@ -822,14 +537,6 @@
 #endif

 

 /**

- * @brief   PLLI2SP divider value.

- * @note    The allowed values are 2, 4, 6 and 8.

- */

-#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SP_VALUE         4

-#endif

-

-/**

  * @brief   PLLI2SQ divider value.

  * @note    The allowed values are 2..15.

  */

@@ -838,80 +545,19 @@
 #endif

 

 /**

- * @brief   PLLI2SDIVQ divider value (SAI clock divider).

+ * @brief   PLLI2SDIVR divider value (SAI clock divider).

  * @note    The allowed values are 1..32.

  */

-#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SDIVQ_VALUE      1

-#endif

-

-/**

- * @brief   PLLSAIM value.

- * @note    The allowed values are 2..63.

- * @note    The default value is calculated for a 96MHz SAI clock

- *          output from an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIM_VALUE         4

+#if !defined(STM32_PLLI2SDIVR_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLI2SDIVR_VALUE      1

 #endif

 

 /**

- * @brief   PLLSAIN value.

- * @note    The allowed values are 50..432.

- * @note    The default value is calculated for a 96MHz SAI clock

- *          output from an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIN_VALUE         192

-#endif

-

-/**

- * @brief   PLLSAIM value.

- * @note    The allowed values are 2..63.

- * @note    The default value is calculated for a 96MHz SAI clock

- *          output from an external 8MHz HSE clock.

- */

-#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIM_VALUE         4

-#endif

-

-/**

- * @brief   PLLSAIR value.

- * @note    The allowed values are 2..7.

- */

-#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIR_VALUE         4

-#endif

-

-/**

- * @brief   PLLSAIP divider value.

- * @note    The allowed values are 2, 4, 6 and 8.

- */

-#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIP_VALUE         8

-#endif

-

-/**

- * @brief   PLLSAIQ value.

- * @note    The allowed values are 2..15.

- */

-#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIQ_VALUE         4

-#endif

-

-/**

- * @brief   PLLSAIDIVR divider value (SAI clock divider).

- */

-#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)

-#define STM32_PLLSAIDIVR            STM32_PLLSAIDIVR_OFF

-#endif

-

-/**

- * @brief   PLLSAIDIVQ divider value (LCD clock divider).

+ * @brief   PLLDIVR divider value (SAI clock divider).

  * @note    The allowed values are 1..32.

  */

-#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)

-#define STM32_PLLSAIDIVQ_VALUE      1

+#if !defined(STM32_PLLDIVR_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLDIVR_VALUE         1

 #endif

 

 /**

@@ -945,27 +591,6 @@
 #endif

 

 /**

- * @brief   AHB prescaler value.

- */

-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)

-#define STM32_HPRE                  STM32_HPRE_DIV1

-#endif

-

-/**

- * @brief   APB1 prescaler value.

- */

-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)

-#define STM32_PPRE1                 STM32_PPRE1_DIV4

-#endif

-

-/**

- * @brief   APB2 prescaler value.

- */

-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)

-#define STM32_PPRE2                 STM32_PPRE2_DIV2

-#endif

-

-/**

  * @brief   RTC clock source.

  */

 #if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)

@@ -1016,7 +641,6 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if defined(STM32F4XX) || defined(__DOXYGEN__)

 /*

  * Configuration-related checks.

  */

@@ -1024,67 +648,15 @@
 #error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"

 #endif

 

-#else /* !defined(STM32F4XX) */

-/*

- * Configuration-related checks.

- */

-#if !defined(STM32F2xx_MCUCONF)

-#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"

+#if defined(STM32F413xx) && !defined(STM32F413_MCUCONF)

+#error "Using a wrong mcuconf.h file, STM32F413_MCUCONF not defined"

 #endif

-#endif /* !defined(STM32F4XX) */

 

 /**

- * @brief   Maximum frequency thresholds and wait states for flash access.

- * @note    The values are valid for 2.7V to 3.6V supply range.

+ * @name    Maximum frequency thresholds and wait states for flash access.

+ * @{

  */

-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \

-    defined(STM32F40_41xxx)  || defined(STM32F446xx)     ||                 \

-    defined(STM32F469_479xx) || defined(__DOXYGEN__)

-#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)

-#define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         60000000

-#define STM32_2WS_THRESHOLD         90000000

-#define STM32_3WS_THRESHOLD         120000000

-#define STM32_4WS_THRESHOLD         150000000

-#define STM32_5WS_THRESHOLD         180000000

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

-#define STM32_0WS_THRESHOLD         24000000

-#define STM32_1WS_THRESHOLD         48000000

-#define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         96000000

-#define STM32_4WS_THRESHOLD         120000000

-#define STM32_5WS_THRESHOLD         144000000

-#define STM32_6WS_THRESHOLD         168000000

-#define STM32_7WS_THRESHOLD         180000000

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

-#define STM32_0WS_THRESHOLD         22000000

-#define STM32_1WS_THRESHOLD         44000000

-#define STM32_2WS_THRESHOLD         66000000

-#define STM32_3WS_THRESHOLD         88000000

-#define STM32_4WS_THRESHOLD         110000000

-#define STM32_5WS_THRESHOLD         132000000

-#define STM32_6WS_THRESHOLD         154000000

-#define STM32_7WS_THRESHOLD         176000000

-#define STM32_8WS_THRESHOLD         180000000

-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

-#define STM32_0WS_THRESHOLD         20000000

-#define STM32_1WS_THRESHOLD         40000000

-#define STM32_2WS_THRESHOLD         60000000

-#define STM32_3WS_THRESHOLD         80000000

-#define STM32_4WS_THRESHOLD         100000000

-#define STM32_5WS_THRESHOLD         120000000

-#define STM32_6WS_THRESHOLD         140000000

-#define STM32_7WS_THRESHOLD         168000000

-#define STM32_8WS_THRESHOLD         0

-#else

-#error "invalid VDD voltage specified"

-#endif

-

-#elif defined(STM32F413xx)

+#if defined(STM32F413xx)

 #if (STM32_VDD >= 270) && (STM32_VDD <= 360)

 #define STM32_0WS_THRESHOLD         25000000

 #define STM32_1WS_THRESHOLD         50000000

@@ -1128,184 +700,8 @@
 #else

 #error "invalid VDD voltage specified"

 #endif

-

-#elif defined(STM32F412xx)

-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

-#define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         64000000

-#define STM32_2WS_THRESHOLD         90000000

-#define STM32_3WS_THRESHOLD         100000000

-#define STM32_4WS_THRESHOLD         0

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

-#define STM32_0WS_THRESHOLD         24000000

-#define STM32_1WS_THRESHOLD         48000000

-#define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         96000000

-#define STM32_4WS_THRESHOLD         100000000

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

-#define STM32_0WS_THRESHOLD         18000000

-#define STM32_1WS_THRESHOLD         36000000

-#define STM32_2WS_THRESHOLD         54000000

-#define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         90000000

-#define STM32_5WS_THRESHOLD         100000000

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 170) && (STM32_VDD < 210)

-#define STM32_0WS_THRESHOLD         16000000

-#define STM32_1WS_THRESHOLD         32000000

-#define STM32_2WS_THRESHOLD         48000000

-#define STM32_3WS_THRESHOLD         64000000

-#define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         96000000

-#define STM32_6WS_THRESHOLD         100000000

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#else

-#error "invalid VDD voltage specified"

-#endif

-

-#elif defined(STM32F410xx) || defined(STM32F411xx)

-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

-#define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         64000000

-#define STM32_2WS_THRESHOLD         90000000

-#define STM32_3WS_THRESHOLD         100000000

-#define STM32_4WS_THRESHOLD         0

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

-#define STM32_0WS_THRESHOLD         24000000

-#define STM32_1WS_THRESHOLD         48000000

-#define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         96000000

-#define STM32_4WS_THRESHOLD         100000000

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

-#define STM32_0WS_THRESHOLD         18000000

-#define STM32_1WS_THRESHOLD         36000000

-#define STM32_2WS_THRESHOLD         54000000

-#define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         90000000

-#define STM32_5WS_THRESHOLD         100000000

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 171) && (STM32_VDD < 210)

-#define STM32_0WS_THRESHOLD         16000000

-#define STM32_1WS_THRESHOLD         32000000

-#define STM32_2WS_THRESHOLD         48000000

-#define STM32_3WS_THRESHOLD         64000000

-#define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         96000000

-#define STM32_6WS_THRESHOLD         100000000

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#else

-#error "invalid VDD voltage specified"

-#endif

-

-

-#elif defined(STM32F401xx)

-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

-#define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         60000000

-#define STM32_2WS_THRESHOLD         84000000

-#define STM32_3WS_THRESHOLD         0

-#define STM32_4WS_THRESHOLD         0

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

-#define STM32_0WS_THRESHOLD         24000000

-#define STM32_1WS_THRESHOLD         48000000

-#define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         84000000

-#define STM32_4WS_THRESHOLD         0

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

-#define STM32_0WS_THRESHOLD         18000000

-#define STM32_1WS_THRESHOLD         36000000

-#define STM32_2WS_THRESHOLD         54000000

-#define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         84000000

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

-#define STM32_0WS_THRESHOLD         16000000

-#define STM32_1WS_THRESHOLD         32000000

-#define STM32_2WS_THRESHOLD         48000000

-#define STM32_3WS_THRESHOLD         64000000

-#define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         84000000

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#define STM32_8WS_THRESHOLD         0

-#else

-#error "invalid VDD voltage specified"

-#endif

-

-#else /* STM32F2XX */

-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

-#define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         60000000

-#define STM32_2WS_THRESHOLD         90000000

-#define STM32_3WS_THRESHOLD         120000000

-#define STM32_4WS_THRESHOLD         0

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

-#define STM32_0WS_THRESHOLD         24000000

-#define STM32_1WS_THRESHOLD         48000000

-#define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         96000000

-#define STM32_4WS_THRESHOLD         120000000

-#define STM32_5WS_THRESHOLD         0

-#define STM32_6WS_THRESHOLD         0

-#define STM32_7WS_THRESHOLD         0

-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

-#define STM32_0WS_THRESHOLD         18000000

-#define STM32_1WS_THRESHOLD         36000000

-#define STM32_2WS_THRESHOLD         54000000

-#define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         90000000

-#define STM32_5WS_THRESHOLD         108000000

-#define STM32_6WS_THRESHOLD         120000000

-#define STM32_7WS_THRESHOLD         0

-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

-#define STM32_0WS_THRESHOLD         16000000

-#define STM32_1WS_THRESHOLD         32000000

-#define STM32_2WS_THRESHOLD         48000000

-#define STM32_3WS_THRESHOLD         64000000

-#define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         96000000

-#define STM32_6WS_THRESHOLD         112000000

-#define STM32_7WS_THRESHOLD         120000000

-#else

-#error "invalid VDD voltage specified"

-#endif

-#endif /* STM32F2XX */

+#endif /* defined(STM32F413xx) */

+/** @} */

 

 /*

  * HSI related checks.

@@ -1331,7 +727,7 @@
 #error "HSI not enabled, required by STM32_MCO2SEL"

 #endif

 

-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \

+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLI2S) &&                          \

     (STM32_PLLSRC == STM32_PLLSRC_HSI)

 #error "HSI not enabled, required by STM32_I2SSRC"

 #endif

@@ -1389,9 +785,9 @@
 #error "HSE not enabled, required by STM32_MCO2SEL"

 #endif

 

-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) &&                                \

+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) &&                          \

     (STM32_PLLSRC == STM32_PLLSRC_HSE)

-#error "HSE not enabled, required by STM32_I2SSRC"

+#error "HSE not enabled, required by STM32_PLLI2SSRC"

 #endif

 

 #if STM32_RTCSEL == STM32_RTCSEL_HSEDIV

@@ -1520,13 +916,13 @@
 #endif

 

 /**

- * @brief   STM32_PLLR field.

+ * @brief   STM32_PLLDIVR_VALUE field.

  */

-#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 7)) ||                 \

+#if ((STM32_PLLDIVR_VALUE >= 1) && (STM32_PLLDIVR_VALUE <= 32)) ||          \

     defined(__DOXYGEN__)

-#define STM32_PLLR                  (STM32_PLLR_VALUE << 28)

+#define STM32_PLLDIVR               ((STM32_PLLDIVR_VALUE - 1) << 8)

 #else

-#error "invalid STM32_PLLR_VALUE value specified"

+#error "invalid STM32_PLLDIVR_VALUE value specified"

 #endif

 

 /**

@@ -1574,41 +970,7 @@
 #endif

 

 /* Calculating VOS settings, it is different for each sub-platform.*/

-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) ||                 \

-    defined(STM32F446xx)     || defined(STM32F469_479xx) ||                 \

-    defined(__DOXYGEN__)

-#if STM32_SYSCLK <= 120000000

-#define STM32_VOS                   STM32_VOS_SCALE3

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-#elif STM32_SYSCLK <= 144000000

-#define STM32_VOS                   STM32_VOS_SCALE2

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-#elif STM32_SYSCLK <= 168000000

-#define STM32_VOS                   STM32_VOS_SCALE1

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-#else

-#define STM32_VOS                   STM32_VOS_SCALE1

-#define STM32_OVERDRIVE_REQUIRED    TRUE

-#endif

-

-#elif defined(STM32F40_41xxx)

-#if STM32_SYSCLK <= 144000000

-#define STM32_VOS                   STM32_VOS_SCALE2

-#else

-#define STM32_VOS                   STM32_VOS_SCALE1

-#endif

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-

-#elif defined(STM32F401xx)

-#if STM32_SYSCLK <= 60000000

-#define STM32_VOS                   STM32_VOS_SCALE3

-#else

-#define STM32_VOS                   STM32_VOS_SCALE2

-#endif

-#define STM32_OVERDRIVE_REQUIRED    FALSE

-

-#elif defined(STM32F410xx) || defined(STM32F411xx) ||                       \

-      defined(STM32F412xx) || defined(STM32F413xx)

+#if defined(STM32F413xx)

 #if STM32_SYSCLK <= 64000000

 #define STM32_VOS                   STM32_VOS_SCALE3

 #elif STM32_SYSCLK <= 84000000

@@ -1617,9 +979,6 @@
 #define STM32_VOS                   STM32_VOS_SCALE1

 #endif

 #define STM32_OVERDRIVE_REQUIRED    FALSE

-

-#else /* STM32F2XX */

-#define STM32_OVERDRIVE_REQUIRED    FALSE

 #endif

 

 /**

@@ -1709,8 +1068,7 @@
      (STM32_CLOCK48_REQUIRED &&                                             \

       (STM32_HAS_RCC_CK48MSEL &&                                            \

        STM32_RCC_CK48MSEL_USES_I2S &&                                       \

-       (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                        \

-      (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                              \

+       (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S)) ||                        \

       (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) ||                            \

       (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) ||                          \

     defined(__DOXYGEN__)

@@ -1744,21 +1102,6 @@
 #endif

 

 /**

- * @brief   STM32_PLLI2SP field.

- */

-#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLI2SP               STM32_PLLI2SP_DIV2

-#elif STM32_PLLI2SP_VALUE == 4

-#define STM32_PLLI2SP               STM32_PLLI2SP_DIV4

-#elif STM32_PLLI2SP_VALUE == 6

-#define STM32_PLLI2SP               STM32_PLLI2SP_DIV6

-#elif STM32_PLLI2SP_VALUE == 8

-#define STM32_PLLI2SP               STM32_PLLI2SP_DIV8

-#else

-#error "invalid STM32_PLLI2SP_VALUE value specified"

-#endif

-

-/**

  * @brief   STM32_PLLI2SQ field.

  */

 #if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) ||          \

@@ -1769,23 +1112,23 @@
 #endif

 

 /**

- * @brief   STM32_PLLI2SDIVQ field.

+ * @brief   STM32_PLLI2SR field.

  */

-#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) ||    \

+#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \

     defined(__DOXYGEN__)

-#define STM32_PLLI2SDIVQ            ((STM32_PLLI2SQ_VALUE - 1) << 0)

+#define STM32_PLLI2SR               (STM32_PLLI2SR_VALUE << 28)

 #else

-#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"

+#error "invalid STM32_PLLI2SR_VALUE value specified"

 #endif

 

 /**

- * @brief   STM32_PLLI2SR field.

+ * @brief   STM32_PLLI2SDIVR field.

  */

-#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \

+#if ((STM32_PLLI2SDIVR_VALUE >= 1) && (STM32_PLLI2SDIVR_VALUE <= 32)) ||    \

     defined(__DOXYGEN__)

-#define STM32_PLLI2SR               (STM32_PLLI2SR_VALUE << 28)

+#define STM32_PLLI2SDIVR            ((STM32_PLLI2SR_VALUE - 1) << 0)

 #else

-#error "invalid STM32_PLLI2SR_VALUE value specified"

+#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"

 #endif

 

 /**

@@ -1794,7 +1137,7 @@
 #if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)

 #if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)

 #define STM32_PLLI2SCLKIN           (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)

-#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN

+#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN

 #define STM32_PLLI2SCLKIN           (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)

 #else

 #error "invalid STM32_PLLI2SSRC value specified"

@@ -1817,11 +1160,6 @@
 #endif

 

 /**

- * @brief   PLLI2S P output clock frequency.

- */

-#define STM32_PLLI2S_P_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)

-

-/**

  * @brief   PLLI2S Q output clock frequency.

  */

 #define STM32_PLLI2S_Q_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)

@@ -1831,145 +1169,11 @@
  */

 #define STM32_PLLI2S_R_CLKOUT       (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)

 

-/*

- * PLLSAI enable check.

- */

-#if (STM32_HAS_RCC_PLLSAI &&                                                \

-     (STM32_CLOCK48_REQUIRED &&                                             \

-      (STM32_HAS_RCC_CK48MSEL &&                                            \

-       !STM32_RCC_CK48MSEL_USES_I2S &&                                      \

-       (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                        \

-      (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                              \

-      (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) ||                            \

-      (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) ||                          \

-      (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) ||                         \

-    defined(__DOXYGEN__)

 /**

  * @brief   PLLSAI activation flag.

+ * @note    Always FALSE, there is no PLLSAI.

  */

-#define STM32_ACTIVATE_PLLSAI       TRUE

-#else

 #define STM32_ACTIVATE_PLLSAI       FALSE

-#endif

-

-/**

- * @brief   STM32_PLLSAIM field.

- */

-#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) ||          \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIM               (STM32_PLLSAIM_VALUE << 0)

-#else

-#error "invalid STM32_PLLSAIM_VALUE value specified"

-#endif

-

-/**

- * @brief   STM32_PLLSAIN field.

- */

-#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) ||        \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIN               (STM32_PLLSAIN_VALUE << 6)

-#else

-#error "invalid STM32_PLLSAIN_VALUE value specified"

-#endif

-

-/**

- * @brief   STM32_PLLSAIQ field.

- */

-#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) ||          \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIQ               (STM32_PLLSAIQ_VALUE << 24)

-#else

-#error "invalid STM32_PLLSAIQ_VALUE value specified"

-#endif

-

-/**

- * @brief   STM32_PLLSAIDIVQ_VALUE field.

- */

-#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) ||    \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIDIVQ            ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)

-#else

-#error "invalid STM32_PLLSAIDIVQ_VALUE value specified"

-#endif

-

-/**

- * @brief   STM32_PLLSAIR field.

- */

-#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) ||           \

-    defined(__DOXYGEN__)

-#define STM32_PLLSAIR               (STM32_PLLSAIR_VALUE << 28)

-#else

-#error "invalid STM32_PLLSAIR_VALUE value specified"

-#endif

-

-/**

- * @brief   STM32_PLLSAIP field.

- */

-

-#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)

-#define STM32_PLLSAIP               STM32_PLLSAIP_DIV2

-

-#elif STM32_PLLSAIP_VALUE == 4

-#define STM32_PLLSAIP               STM32_PLLSAIP_DIV4

-

-#elif STM32_PLLSAIP_VALUE == 6

-#define STM32_PLLSAIP               STM32_PLLSAIP_DIV6

-

-#elif STM32_PLLSAIP_VALUE == 8

-#define STM32_PLLSAIP               STM32_PLLSAIP_DIV8

-

-#else

-#error "invalid STM32_PLLSAIP_VALUE value specified"

-#endif

-

-/**

- * @brief   PLLSAI input clock frequency.

- */

-#if defined(STM32F446xx)

-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

-#define STM32_PLLSAICLKIN           (STM32_HSECLK / STM32_PLLSAIM_VALUE)

-#elif STM32_PLLSRC == STM32_PLLSRC_HSI

-#define STM32_PLLSAICLKIN           (STM32_HSICLK / STM32_PLLSAIM_VALUE)

-#else

-#error "invalid STM32_PLLSRC value specified"

-#endif

-#else /* !defined(STM32F446xx) */

-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

-#define STM32_PLLSAICLKIN           (STM32_HSECLK / STM32_PLLM_VALUE)

-#elif STM32_PLLSRC == STM32_PLLSRC_HSI

-#define STM32_PLLSAICLKIN           (STM32_HSICLK / STM32_PLLM_VALUE)

-#else

-#error "invalid STM32_PLLSRC value specified"

-#endif

-#endif /* defined(STM32F446xx) */

-

-/**

- * @brief   PLLSAI VCO frequency.

- */

-#define STM32_PLLSAIVCO             (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE)

-

-/*

- * PLLSAI VCO frequency range check.

- */

-#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) ||                                 \

-    (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)

-#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"

-#endif

-

-/**

- * @brief   PLLSAI P output clock frequency.

- */

-#define STM32_PLLSAI_P_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)

-

-/**

- * @brief   PLLSAI Q output clock frequency.

- */

-#define STM32_PLLSAI_Q_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)

-

-/**

- * @brief   PLLSAI R output clock frequency.

- */

-#define STM32_PLLSAI_R_CLKOUT       (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)

 

 /**

  * @brief   MCO1 divider clock.

@@ -2099,7 +1303,7 @@
 #if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)

 #if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)

 #define STM32_PLL48CLK              (STM32_PLLVCO / STM32_PLLQ_VALUE)

-#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT

+#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S

 #if STM32_RCC_CK48MSEL_USES_I2S

 #define STM32_PLL48CLK              STM32_PLLI2S_Q_CLKOUT

 #else

@@ -2244,6 +1448,6 @@ extern "C" {
 }

 #endif

 

-#endif /* HAL_LLD_H */

+#endif /* HAL_LLD_TYPE2_H */

 

 /** @} */