diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-14 11:08:58 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-14 11:08:58 +0000 |
| commit | a1085e2da95727b9edf3e4ba982001d755b101f3 (patch) | |
| tree | 989e45debfe1e02038b652989b664c4f7c34e25f | |
| parent | a4fa6c20411b4d5664ccf151f403a72d7e5bb4cc (diff) | |
| download | ChibiOS-a1085e2da95727b9edf3e4ba982001d755b101f3.tar.gz ChibiOS-a1085e2da95727b9edf3e4ba982001d755b101f3.tar.bz2 ChibiOS-a1085e2da95727b9edf3e4ba982001d755b101f3.zip | |
Added F413 board, demo and revised HAL code, to be tested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12031 110e8d01-0319-4d1e-a829-52ad28d1bb01
19 files changed, 5551 insertions, 888 deletions
diff --git a/demos/STM32/RT-STM32F412ZG-NUCLEO144/.cproject b/demos/STM32/RT-STM32F412ZG-NUCLEO144/.cproject index c087bd223..bff293b5b 100644 --- a/demos/STM32/RT-STM32F412ZG-NUCLEO144/.cproject +++ b/demos/STM32/RT-STM32F412ZG-NUCLEO144/.cproject @@ -37,7 +37,7 @@ </cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
- <project id="RT-STM32F429-DISCOVERY.null.1703860681" name="ARMCM4-STM32F407-DISCOVERY-ALT"/>
+ <project id="RT-STM32F413ZH-NUCLEO144Y.null.1703860681" name="ARMCM4-STM32F407-DISCOVERY-ALT"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
@@ -48,7 +48,7 @@ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Default">
- <resource resourceType="PROJECT" workspacePath="/RT-STM32F429-DISCOVERY"/>
+ <resource resourceType="PROJECT" workspacePath="/RT-STM32F413ZH-NUCLEO144Y"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/.cproject b/demos/STM32/RT-STM32F413ZH-NUCLEO144/.cproject new file mode 100644 index 000000000..bff293b5b --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/.cproject @@ -0,0 +1,55 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="0.114656749">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="0.114656749" moduleId="org.eclipse.cdt.core.settings" name="Default">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.VCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildProperties="" description="" id="0.114656749" name="Default" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+ <folderInfo id="0.114656749." name="/" resourcePath="">
+ <toolChain id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861" name="No ToolChain" resourceTypeBasedDiscovery="false" superClass="org.eclipse.cdt.build.core.prefbase.toolchain">
+ <targetPlatform id="org.eclipse.cdt.build.core.prefbase.toolchain.1182750861.169007201" name=""/>
+ <builder autoBuildTarget="all" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="org.eclipse.cdt.build.core.settings.default.builder.579570726" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.settings.default.builder"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.libs.2143276802" name="holder for library settings" superClass="org.eclipse.cdt.build.core.settings.holder.libs"/>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1873650595" name="Assembly" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.1337802279" languageId="org.eclipse.cdt.core.assembly" languageName="Assembly" sourceContentType="org.eclipse.cdt.core.asmSource" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1707090075" name="GNU C++" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.338985256" languageId="org.eclipse.cdt.core.g++" languageName="GNU C++" sourceContentType="org.eclipse.cdt.core.cxxSource,org.eclipse.cdt.core.cxxHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ <tool id="org.eclipse.cdt.build.core.settings.holder.1165165914" name="GNU C" superClass="org.eclipse.cdt.build.core.settings.holder">
+ <inputType id="org.eclipse.cdt.build.core.settings.holder.inType.714476670" languageId="org.eclipse.cdt.core.gcc" languageName="GNU C" sourceContentType="org.eclipse.cdt.core.cSource,org.eclipse.cdt.core.cHeader" superClass="org.eclipse.cdt.build.core.settings.holder.inType"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="RT-STM32F413ZH-NUCLEO144Y.null.1703860681" name="ARMCM4-STM32F407-DISCOVERY-ALT"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="0.114656749">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Default">
+ <resource resourceType="PROJECT" workspacePath="/RT-STM32F413ZH-NUCLEO144Y"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/.project b/demos/STM32/RT-STM32F413ZH-NUCLEO144/.project new file mode 100644 index 000000000..93900de09 --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/.project @@ -0,0 +1,95 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>RT-STM32F413ZH-NUCLEO144</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>?name?</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildArguments</key>
+ <value>-j1</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.buildCommand</key>
+ <value>make</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.contents</key>
+ <value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>true</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>board</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os/hal/boards/ST_NUCLEO144_F413ZH</locationURI>
+ </link>
+ <link>
+ <name>os</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/os</locationURI>
+ </link>
+ <link>
+ <name>test</name>
+ <type>2</type>
+ <locationURI>CHIBIOS/test</locationURI>
+ </link>
+ </linkedResources>
+</projectDescription>
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/Makefile b/demos/STM32/RT-STM32F413ZH-NUCLEO144/Makefile new file mode 100644 index 000000000..83515f7fc --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/Makefile @@ -0,0 +1,214 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# Linker extra options here.
+ifeq ($(USE_LDOPT),)
+ USE_LDOPT =
+endif
+
+# Enable this if you want link time optimizations (LTO)
+ifeq ($(USE_LTO),)
+ USE_LTO = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+# If enabled, this option makes the build process faster by not compiling
+# modules not used in the current configuration.
+ifeq ($(USE_SMART_BUILD),)
+ USE_SMART_BUILD = yes
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Stack size to be allocated to the Cortex-M process stack. This stack is
+# the stack used by the main() thread.
+ifeq ($(USE_PROCESS_STACKSIZE),)
+ USE_PROCESS_STACKSIZE = 0x400
+endif
+
+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
+# stack is used for processing interrupts and exceptions.
+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
+ USE_EXCEPTIONS_STACKSIZE = 0x400
+endif
+
+# Enables the use of FPU (no, softfp, hard).
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../..
+# Licensing files.
+include $(CHIBIOS)/os/license/license.mk
+# Startup files.
+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
+# HAL-OSAL files (optional).
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F413ZH/board.mk
+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
+# RTOS files (optional).
+include $(CHIBIOS)/os/rt/rt.mk
+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
+# Other files (optional).
+include $(CHIBIOS)/test/lib/test.mk
+include $(CHIBIOS)/test/rt/rt_test.mk
+include $(CHIBIOS)/test/oslib/oslib_test.mk
+include $(CHIBIOS)/os/hal/lib/streams/streams.mk
+
+# Define linker script file here
+LDSCRIPT= $(STARTUPLD)/STM32F413xH.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(ALLCSRC) \
+ $(TESTSRC) \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC = $(ALLCPPSRC)
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(ALLASMSRC)
+ASMXSRC = $(ALLXASMSRC)
+
+INCDIR = $(ALLINC) $(TESTINC)
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+AR = $(TRGT)ar
+OD = $(TRGT)objdump
+SZ = $(TRGT)size
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra -Wundef
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
+include $(RULESPATH)/rules.mk
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/chconf.h b/demos/STM32/RT-STM32F413ZH-NUCLEO144/chconf.h new file mode 100644 index 000000000..aea2de97d --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/chconf.h @@ -0,0 +1,615 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef CHCONF_H
+#define CHCONF_H
+
+#define _CHIBIOS_RT_CONF_
+#define _CHIBIOS_RT_CONF_VER_5_0_
+
+/*===========================================================================*/
+/**
+ * @name System timers settings
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System time counter resolution.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_ST_RESOLUTION 32
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#define CH_CFG_ST_FREQUENCY 10000
+
+/**
+ * @brief Time intervals data size.
+ * @note Allowed values are 16, 32 or 64 bits.
+ */
+#define CH_CFG_INTERVALS_SIZE 32
+
+/**
+ * @brief Time types data size.
+ * @note Allowed values are 16 or 32 bits.
+ */
+#define CH_CFG_TIME_TYPES_SIZE 32
+
+/**
+ * @brief Time delta constant for the tick-less mode.
+ * @note If this value is zero then the system uses the classic
+ * periodic tick. This value represents the minimum number
+ * of ticks that is safe to specify in a timeout directive.
+ * The value one is not valid, timeouts are rounded up to
+ * this value.
+ */
+#define CH_CFG_ST_TIMEDELTA 2
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ * @note The round robin preemption is not supported in tickless mode and
+ * must be set to zero in that case.
+ */
+#define CH_CFG_TIME_QUANTUM 0
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_CFG_USE_MEMCORE.
+ */
+#define CH_CFG_MEMCORE_SIZE 0
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread. The application @p main()
+ * function becomes the idle thread and must implement an
+ * infinite loop.
+ */
+#define CH_CFG_NO_IDLE_THREAD FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_OPTIMIZE_SPEED TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Time Measurement APIs.
+ * @details If enabled then the time measurement APIs are included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_TM TRUE
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_REGISTRY TRUE
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_WAITEXIT TRUE
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_SEMAPHORES TRUE
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MUTEXES TRUE
+
+/**
+ * @brief Enables recursive behavior on mutexes.
+ * @note Recursive mutexes are heavier and have an increased
+ * memory footprint.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MUTEXES.
+ */
+#define CH_CFG_USE_CONDVARS TRUE
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_CONDVARS.
+ */
+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_EVENTS TRUE
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_EVENTS.
+ */
+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MESSAGES TRUE
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special
+ * requirements.
+ * @note Requires @p CH_CFG_USE_MESSAGES.
+ */
+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
+ */
+#define CH_CFG_USE_MAILBOXES TRUE
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMCORE TRUE
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
+ * @p CH_CFG_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#define CH_CFG_USE_HEAP TRUE
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_MEMPOOLS TRUE
+
+/**
+ * @brief Objects FIFOs APIs.
+ * @details If enabled then the objects FIFOs APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#define CH_CFG_USE_OBJ_FIFOS TRUE
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_CFG_USE_WAITEXIT.
+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
+ */
+#define CH_CFG_USE_DYNAMIC TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Objects factory options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Objects Factory APIs.
+ * @details If enabled then the objects factory APIs are included in the
+ * kernel.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_CFG_USE_FACTORY TRUE
+
+/**
+ * @brief Maximum length for object names.
+ * @details If the specified length is zero then the name is stored by
+ * pointer but this could have unintended side effects.
+ */
+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
+
+/**
+ * @brief Enables the registry of generic objects.
+ */
+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
+
+/**
+ * @brief Enables factory for generic buffers.
+ */
+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
+
+/**
+ * @brief Enables factory for semaphores.
+ */
+#define CH_CFG_FACTORY_SEMAPHORES TRUE
+
+/**
+ * @brief Enables factory for mailboxes.
+ */
+#define CH_CFG_FACTORY_MAILBOXES TRUE
+
+/**
+ * @brief Enables factory for objects FIFOs.
+ */
+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, kernel statistics.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_STATISTICS FALSE
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_CHECKS FALSE
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_ENABLE_ASSERTS FALSE
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the trace buffer is activated.
+ *
+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
+
+/**
+ * @brief Trace buffer entries.
+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
+ */
+#define CH_DBG_TRACE_BUFFER_SIZE 128
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#define CH_DBG_FILL_THREADS FALSE
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p thread_t structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p FALSE.
+ * @note This debug option is not currently compatible with the
+ * tickless mode.
+ */
+#define CH_DBG_THREADS_PROFILING FALSE
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System structure extension.
+ * @details User fields added to the end of the @p ch_system_t structure.
+ */
+#define CH_CFG_SYSTEM_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief System initialization hook.
+ * @details User initialization code added to the @p chSysInit() function
+ * just before interrupts are enabled globally.
+ */
+#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p thread_t structure.
+ */
+#define CH_CFG_THREAD_EXTRA_FIELDS \
+ /* Add threads custom fields here.*/
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ */
+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* Context switch code here.*/ \
+}
+
+/**
+ * @brief ISR enter hook.
+ */
+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
+ /* IRQ prologue code here.*/ \
+}
+
+/**
+ * @brief ISR exit hook.
+ */
+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
+ /* IRQ epilogue code here.*/ \
+}
+
+/**
+ * @brief Idle thread enter hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to activate a power saving mode.
+ */
+#define CH_CFG_IDLE_ENTER_HOOK() { \
+ /* Idle-enter code here.*/ \
+}
+
+/**
+ * @brief Idle thread leave hook.
+ * @note This hook is invoked within a critical zone, no OS functions
+ * should be invoked from here.
+ * @note This macro can be used to deactivate a power saving mode.
+ */
+#define CH_CFG_IDLE_LEAVE_HOOK() { \
+ /* Idle-leave code here.*/ \
+}
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#define CH_CFG_IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#define CH_CFG_SYSTEM_TICK_HOOK() { \
+ /* System tick event code here.*/ \
+}
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
+ /* System halt code here.*/ \
+}
+
+/**
+ * @brief Trace hook.
+ * @details This hook is invoked each time a new record is written in the
+ * trace buffer.
+ */
+#define CH_CFG_TRACE_HOOK(tep) { \
+ /* Trace code here.*/ \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* CHCONF_H */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/halconf.h b/demos/STM32/RT-STM32F413ZH-NUCLEO144/halconf.h new file mode 100644 index 000000000..82602b403 --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/halconf.h @@ -0,0 +1,388 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef HALCONF_H
+#define HALCONF_H
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the DAC subsystem.
+ */
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+#define HAL_USE_DAC FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the I2S subsystem.
+ */
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+#define HAL_USE_I2S FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the QSPI subsystem.
+ */
+#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
+#define HAL_USE_QSPI FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/**
+ * @brief Enables the WDG subsystem.
+ */
+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+#define HAL_USE_WDG FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+#define MAC_USE_ZERO_COPY FALSE
+#endif
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 16 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SERIAL_USB driver related setting. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial over USB buffers size.
+ * @details Configuration parameter, the buffer size must be a multiple of
+ * the USB data endpoint maximum packet size.
+ * @note The default is 256 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_SIZE 256
+#endif
+
+/**
+ * @brief Serial over USB number of buffers.
+ * @note The default is 2 buffers.
+ */
+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+#define SERIAL_USB_BUFFERS_NUMBER 2
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* UART driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+#define UART_USE_WAIT FALSE
+#endif
+
+/**
+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define UART_USE_MUTUAL_EXCLUSION FALSE
+#endif
+
+/*===========================================================================*/
+/* USB driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+#define USB_USE_WAIT FALSE
+#endif
+
+#endif /* HALCONF_H */
+
+/** @} */
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/main.c b/demos/STM32/RT-STM32F413ZH-NUCLEO144/main.c new file mode 100644 index 000000000..8cfc7fc38 --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/main.c @@ -0,0 +1,83 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "rt_test_root.h"
+#include "oslib_test_root.h"
+
+/*
+ * This is a periodic thread that does absolutely nothing except flashing
+ * a LED.
+ */
+static THD_WORKING_AREA(waThread1, 128);
+static THD_FUNCTION(Thread1, arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (true) {
+ palSetLine(LINE_LED1);
+ chThdSleepMilliseconds(50);
+ palSetLine(LINE_LED2);
+ chThdSleepMilliseconds(50);
+ palSetLine(LINE_LED3);
+ chThdSleepMilliseconds(200);
+ palClearLine(LINE_LED1);
+ chThdSleepMilliseconds(50);
+ palClearLine(LINE_LED2);
+ chThdSleepMilliseconds(50);
+ palClearLine(LINE_LED3);
+ chThdSleepMilliseconds(200);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the serial driver 3 using the driver default configuration.
+ */
+ sdStart(&SD3, NULL);
+
+ /*
+ * Creates the example thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO + 1, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing except
+ * sleeping in a loop and check the button state.
+ */
+ while (true) {
+ if (palReadLine(LINE_BUTTON)) {
+ test_execute((BaseSequentialStream *)&SD3, &rt_test_suite);
+ test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite);
+ }
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h new file mode 100644 index 000000000..2243a48a2 --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/mcuconf.h @@ -0,0 +1,281 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32F4xx_MCUCONF
+#define STM32F413_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_BKPRAM_ENABLE FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 384
+#define STM32_PLLP_VALUE 4
+#define STM32_PLLQ_VALUE 8
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
+#define STM32_I2SCKIN_VALUE 0
+#define STM32_PLLI2SM_VALUE 8
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SQ_VALUE 4
+#define STM32_PLLI2SDIVR_VALUE 1
+#define STM32_PLLDIVR_VALUE 1
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
+#define STM32_TIMPRE STM32_TIMPRE_PCLK
+#define STM32_CK48MSEL STM32_CK48MSEL_PLL
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI16_PRIORITY 6
+#define STM32_IRQ_EXTI17_PRIORITY 15
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_PRIORITY 6
+#define STM32_IRQ_EXTI21_PRIORITY 15
+#define STM32_IRQ_EXTI22_PRIORITY 15
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM9 FALSE
+#define STM32_GPT_USE_TIM11 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM9_IRQ_PRIORITY 7
+#define STM32_GPT_TIM11_IRQ_PRIORITY 7
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * I2S driver system settings.
+ */
+#define STM32_I2S_USE_SPI2 FALSE
+#define STM32_I2S_USE_SPI3 FALSE
+#define STM32_I2S_SPI2_IRQ_PRIORITY 10
+#define STM32_I2S_SPI3_IRQ_PRIORITY 10
+#define STM32_I2S_SPI2_DMA_PRIORITY 1
+#define STM32_I2S_SPI3_DMA_PRIORITY 1
+#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM9 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM9_IRQ_PRIORITY 7
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM9_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 TRUE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_USE_SPI4 FALSE
+#define STM32_SPI_USE_SPI5 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART6_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 FALSE
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
+#define STM32_USB_OTG_THREAD_STACK_SIZE 128
+#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+#endif /* MCUCONF_H */
diff --git a/demos/STM32/RT-STM32F413ZH-NUCLEO144/readme.txt b/demos/STM32/RT-STM32F413ZH-NUCLEO144/readme.txt new file mode 100644 index 000000000..0fac7fcb6 --- /dev/null +++ b/demos/STM32/RT-STM32F413ZH-NUCLEO144/readme.txt @@ -0,0 +1,28 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M4 STM32F413. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an STM32 Nucleo144-F413ZH board.
+
+** The Demo **
+
+The demo flashes the board LEDs using a thread, by pressing the button located
+on the board the test procedure is activated with output on the serial port
+SD3 (USART3, mapped on STLink v2-1 Virtual COM Port).
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO. just modify the TRGT line in the makefile in order to use
+different GCC toolchains.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distributed
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld new file mode 100644 index 000000000..2add531ec --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F413xH.ld @@ -0,0 +1,86 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32F413xH memory setup.
+ * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ */
+MEMORY
+{
+ flash0 : org = 0x08000000, len = 1536k /* Program memory */
+ flash1 : org = 0x1FFF7800, len = 528 /* OTP memory */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20000000, len = 320k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20000000, len = 256k /* SRAM1 */
+ ram2 : org = 0x20040000, len = 64k /* SRAM2 */
+ ram3 : org = 0x00000000, len = 0
+ ram4 : org = 0x10000000, len = 64k /* CCM SRAM2 */
+ ram5 : org = 0x00000000, len = 0
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
+}
+
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash0);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash0);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash0);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+ of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+ the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h b/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h index 377c0dc11..1fa5e8c47 100644 --- a/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h +++ b/os/common/startup/ARMCMx/devices/STM32F4xx/cmparams.h @@ -52,7 +52,12 @@ !defined(STM32F429xx) && !defined(STM32F439xx) && \
!defined(STM32F401xC) && !defined(STM32F401xE) && \
!defined(STM32F410Cx) && !defined(STM32F410Rx) && \
- !defined(STM32F411xE) && !defined(STM32F446xx) && \
+ !defined(STM32F410Tx) && \
+ !defined(STM32F411xE) && \
+ !defined(STM32F412Cx) && !defined(STM32F412Rx) && \
+ !defined(STM32F412Vx) && !defined(STM32F412Zx) && \
+ !defined(STM32F413xx) && \
+ !defined(STM32F446xx) && \
!defined(STM32F469xx) && !defined(STM32F479xx)
#include "board.h"
#endif
diff --git a/os/hal/boards/ST_NUCLEO144_F413ZH/board.c b/os/hal/boards/ST_NUCLEO144_F413ZH/board.c new file mode 100644 index 000000000..5ee0873d7 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO144_F413ZH/board.c @@ -0,0 +1,266 @@ +/*
+ ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+ gpio_setup_t PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+ gpio_setup_t PKData;
+#endif
+} gpio_config_t;
+
+/**
+ * @brief STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
+#endif
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB1(STM32_GPIO_EN_MASK);
+ rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+ gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+ gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
+ */
+void __early_init(void) {
+
+ stm32_gpio_init();
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+
+}
diff --git a/os/hal/boards/ST_NUCLEO144_F413ZH/board.h b/os/hal/boards/ST_NUCLEO144_F413ZH/board.h new file mode 100644 index 000000000..4d98736bf --- /dev/null +++ b/os/hal/boards/ST_NUCLEO144_F413ZH/board.h @@ -0,0 +1,1844 @@ +/*
+ ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*
+ * Setup for STMicroelectronics STM32 Nucleo144-F413ZH board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO144_F413ZH
+#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F413ZH"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0U
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+#define STM32_HSE_BYPASS
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300U
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F413xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_ZIO_D32 0U
+#define GPIOA_TIM2_CH1 0U
+#define GPIOA_PIN1 1U
+#define GPIOA_ZIO_A8 2U
+#define GPIOA_ADC1_IN2 2U
+#define GPIOA_ARD_A0 3U
+#define GPIOA_ADC1_IN3 3U
+#define GPIOA_ZIO_D24 4U
+#define GPIOA_SPI3_NSS 4U
+#define GPIOA_ARD_D13 5U
+#define GPIOA_SPI1_SCK 5U
+#define GPIOA_ARD_D12 6U
+#define GPIOA_SPI1_MISO 6U
+#define GPIOA_ARD_D11 7U
+#define GPIOA_SPI1_MOSI 7U
+#define GPIOA_ZIO_D71 7U
+#define GPIOA_USB_SOF 8U
+#define GPIOA_USB_VBUS 9U
+#define GPIOA_USB_ID 10U
+#define GPIOA_USB_DM 11U
+#define GPIOA_USB_DP 12U
+#define GPIOA_SWDIO 13U
+#define GPIOA_SWCLK 14U
+#define GPIOA_ZIO_D20 15U
+#define GPIOA_I2S3_WS 15U
+
+#define GPIOB_ZIO_D33 0U
+#define GPIOB_TIM3_CH3 0U
+#define GPIOB_LED1 0U
+#define GPIOB_ZIO_A6 1U
+#define GPIOB_ADC1_IN9 1U
+#define GPIOB_ZIO_D27 2U
+#define GPIOB_QUADSPI_CLK 2U
+#define GPIOB_ZIO_D23 3U
+#define GPIOB_I2S3_CK 3U
+#define GPIOB_ZIO_D25 4U
+#define GPIOB_SPI3_MISO 4U
+#define GPIOB_ZIO_D22 5U
+#define GPIOB_I2S3_SD 5U
+#define GPIOB_ZIO_D26 6U
+#define GPIOB_QUADSPI_BK1_NCS 6U
+#define GPIOB_LED2 7U
+#define GPIOB_ARD_D15 8U
+#define GPIOB_I2C1_SCL 8U
+#define GPIOB_ARD_D14 9U
+#define GPIOB_I2C1_SDA 9U
+#define GPIOB_ZIO_D36 10U
+#define GPIOB_TIM2_CH3 10U
+#define GPIOB_ZIO_D35 11U
+#define GPIOB_TIM2_CH4 11U
+#define GPIOB_ZIO_D19 12U
+#define GPIOB_I2S2_WS 12U
+#define GPIOB_ZIO_D18 13U
+#define GPIOB_I2S2_CK 13U
+#define GPIOB_LED3 14U
+#define GPIOB_ZIO_D17 15U
+#define GPIOB_I2S2_SD 15U
+
+#define GPIOC_ARD_A1 0U
+#define GPIOC_ADC1_IN10 0U
+#define GPIOC_ARD_A3 1U
+#define GPIOC_ADC1_IN11 1U
+#define GPIOC_ZIO_A7 2U
+#define GPIOC_ADC1_IN12 2U
+#define GPIOC_ARD_A2 3U
+#define GPIOC_ADC1_IN13 3U
+#define GPIOC_ARD_A4 4U
+#define GPIOC_ADC1_IN14 4U
+#define GPIOC_ARD_A5 5U
+#define GPIOC_ADC1_IN15 5U
+#define GPIOC_ZIO_D16 6U
+#define GPIOC_I2S2_MCK 6U
+#define GPIOC_ZIO_D21 7U
+#define GPIOC_I2S3_MCK 7U
+#define GPIOC_ZIO_D43 8U
+#define GPIOC_SDMMC_D0 8U
+#define GPIOC_ZIO_D44 9U
+#define GPIOC_SDMMC_D1 9U
+#define GPIOC_ZIO_D45 10U
+#define GPIOC_SDMMC_D2 10U
+#define GPIOC_ZIO_D46 11U
+#define GPIOC_SDMMC_D3 11U
+#define GPIOC_ZIO_D47 12U
+#define GPIOC_SDMMC_CK 12U
+#define GPIOC_BUTTON 13U
+#define GPIOC_OSC32_IN 14U
+#define GPIOC_OSC32_OUT 15U
+
+#define GPIOD_ZIO_D67 0U
+#define GPIOD_CAN1_RX 0U
+#define GPIOD_ZIO_D66 1U
+#define GPIOD_CAN1_TX 1U
+#define GPIOD_ZIO_D48 2U
+#define GPIOD_SDMMC_CMD 2U
+#define GPIOD_ZIO_D55 3U
+#define GPIOD_USART2_CTS 3U
+#define GPIOD_ZIO_D54 4U
+#define GPIOD_USART2_RTS 4U
+#define GPIOD_ZIO_D53 5U
+#define GPIOD_USART2_TX 5U
+#define GPIOD_ZIO_D52 6U
+#define GPIOD_USART2_RX 6U
+#define GPIOD_ZIO_D51 7U
+#define GPIOD_USART2_SCLK 7U
+#define GPIOD_USART3_RX 8U
+#define GPIOD_STLK_RX 8U
+#define GPIOD_USART3_TX 9U
+#define GPIOD_STLK_TX 9U
+#define GPIOD_PIN10 10U
+#define GPIOD_ZIO_D30 11U
+#define GPIOD_QUADSPI_BK1_IO0 11U
+#define GPIOD_ZIO_D29 12U
+#define GPIOD_QUADSPI_BK1_IO1 12U
+#define GPIOD_ZIO_D28 13U
+#define GPIOD_QUADSPI_BK1_IO3 13U
+#define GPIOD_ARD_D10 14U
+#define GPIOD_SPI1_NSS 14U
+#define GPIOD_ARD_D9 15U
+#define GPIOD_TIM4_CH4 15U
+
+#define GPIOE_ZIO_D34 0U
+#define GPIOE_TIM4_ETR 0U
+#define GPIOE_PIN1 1U
+#define GPIOE_ZIO_D31 2U
+#define GPIOE_ZIO_D56 2U
+#define GPIOE_QUADSPI_BK1_IO2 2U
+#define GPIOE_ZIO_D60 3U
+#define GPIOE_SAI1_SD_B 3U
+#define GPIOE_ZIO_D57 4U
+#define GPIOE_SAI1_FS_A 4U
+#define GPIOE_ZIO_D58 5U
+#define GPIOE_SAI1_SCK_A 5U
+#define GPIOE_ZIO_D59 6U
+#define GPIOE_SAI1_SD_A 6U
+#define GPIOE_ZIO_D41 7U
+#define GPIOE_TIM1_ETR 7U
+#define GPIOE_ZIO_D42 8U
+#define GPIOE_TIM1_CH1N 8U
+#define GPIOE_ARD_D6 9U
+#define GPIOE_TIM1_CH1 9U
+#define GPIOE_ZIO_D40 10U
+#define GPIOE_TIM1_CH2N 10U
+#define GPIOE_ARD_D5 11U
+#define GPIOE_TIM1_CH2 11U
+#define GPIOE_ZIO_D39 12U
+#define GPIOE_TIM1_CH3N 12U
+#define GPIOE_ARD_D3 13U
+#define GPIOE_TIM1_CH3 13U
+#define GPIOE_ZIO_D38 14U
+#define GPIOE_ZIO_D37 15U
+#define GPIOE_TIM1_BKIN1 15U
+
+#define GPIOF_ZIO_D68 0U
+#define GPIOF_I2C2_SDA 0U
+#define GPIOF_ZIO_D69 1U
+#define GPIOF_I2C2_SCL 1U
+#define GPIOF_ZIO_D70 2U
+#define GPIOF_I2C2_SMBA 2U
+#define GPIOF_PIN3 3U
+#define GPIOF_PIN4 4U
+#define GPIOF_PIN5 5U
+#define GPIOF_PIN6 6U
+#define GPIOF_ZIO_D62 7U
+#define GPIOF_SAI1_MCLK_B 7U
+#define GPIOF_ZIO_D61 8U
+#define GPIOF_SAI1_SCK_B 8U
+#define GPIOF_ZIO_D63 9U
+#define GPIOF_SAI1_FS_B 9U
+#define GPIOF_PIN10 10U
+#define GPIOF_PIN11 11U
+#define GPIOF_ARD_D8 12U
+#define GPIOF_ARD_D7 13U
+#define GPIOF_ARD_D4 14U
+#define GPIOF_ARD_D2 15U
+
+#define GPIOG_ZIO_D65 0U
+#define GPIOG_ZIO_D64 1U
+#define GPIOG_ZIO_D49 2U
+#define GPIOG_ZIO_D50 3U
+#define GPIOG_PIN4 4U
+#define GPIOG_PIN5 5U
+#define GPIOG_USB_GPIO_OUT 6U
+#define GPIOG_USB_GPIO_IN 7U
+#define GPIOG_PIN8 8U
+#define GPIOG_ARD_D0 9U
+#define GPIOG_USART6_RX 9U
+#define GPIOG_PIN10 10U
+#define GPIOG_PIN11 11U
+#define GPIOG_PIN12 12U
+#define GPIOG_PIN13 13U
+#define GPIOG_ARD_D1 14U
+#define GPIOG_USART6_TX 14U
+#define GPIOG_PIN15 15U
+
+#define GPIOH_OSC_IN 0U
+#define GPIOH_OSC_OUT 1U
+#define GPIOH_PIN2 2U
+#define GPIOH_PIN3 3U
+#define GPIOH_PIN4 4U
+#define GPIOH_PIN5 5U
+#define GPIOH_PIN6 6U
+#define GPIOH_PIN7 7U
+#define GPIOH_PIN8 8U
+#define GPIOH_PIN9 9U
+#define GPIOH_PIN10 10U
+#define GPIOH_PIN11 11U
+#define GPIOH_PIN12 12U
+#define GPIOH_PIN13 13U
+#define GPIOH_PIN14 14U
+#define GPIOH_PIN15 15U
+
+#define GPIOI_PIN0 0U
+#define GPIOI_PIN1 1U
+#define GPIOI_PIN2 2U
+#define GPIOI_PIN3 3U
+#define GPIOI_PIN4 4U
+#define GPIOI_PIN5 5U
+#define GPIOI_PIN6 6U
+#define GPIOI_PIN7 7U
+#define GPIOI_PIN8 8U
+#define GPIOI_PIN9 9U
+#define GPIOI_PIN10 10U
+#define GPIOI_PIN11 11U
+#define GPIOI_PIN12 12U
+#define GPIOI_PIN13 13U
+#define GPIOI_PIN14 14U
+#define GPIOI_PIN15 15U
+
+#define GPIOJ_PIN0 0U
+#define GPIOJ_PIN1 1U
+#define GPIOJ_PIN2 2U
+#define GPIOJ_PIN3 3U
+#define GPIOJ_PIN4 4U
+#define GPIOJ_PIN5 5U
+#define GPIOJ_PIN6 6U
+#define GPIOJ_PIN7 7U
+#define GPIOJ_PIN8 8U
+#define GPIOJ_PIN9 9U
+#define GPIOJ_PIN10 10U
+#define GPIOJ_PIN11 11U
+#define GPIOJ_PIN12 12U
+#define GPIOJ_PIN13 13U
+#define GPIOJ_PIN14 14U
+#define GPIOJ_PIN15 15U
+
+#define GPIOK_PIN0 0U
+#define GPIOK_PIN1 1U
+#define GPIOK_PIN2 2U
+#define GPIOK_PIN3 3U
+#define GPIOK_PIN4 4U
+#define GPIOK_PIN5 5U
+#define GPIOK_PIN6 6U
+#define GPIOK_PIN7 7U
+#define GPIOK_PIN8 8U
+#define GPIOK_PIN9 9U
+#define GPIOK_PIN10 10U
+#define GPIOK_PIN11 11U
+#define GPIOK_PIN12 12U
+#define GPIOK_PIN13 13U
+#define GPIOK_PIN14 14U
+#define GPIOK_PIN15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U)
+#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U)
+#define LINE_ZIO_A8 PAL_LINE(GPIOA, 2U)
+#define LINE_ADC1_IN2 PAL_LINE(GPIOA, 2U)
+#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U)
+#define LINE_ADC1_IN3 PAL_LINE(GPIOA, 3U)
+#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U)
+#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U)
+#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U)
+#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U)
+#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U)
+#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U)
+#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U)
+#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U)
+#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U)
+#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)
+#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)
+#define LINE_USB_ID PAL_LINE(GPIOA, 10U)
+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U)
+#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U)
+#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U)
+#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U)
+#define LINE_LED1 PAL_LINE(GPIOB, 0U)
+#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U)
+#define LINE_ADC1_IN9 PAL_LINE(GPIOB, 1U)
+#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U)
+#define LINE_QUADSPI_CLK PAL_LINE(GPIOB, 2U)
+#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U)
+#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U)
+#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U)
+#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U)
+#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U)
+#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U)
+#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U)
+#define LINE_QUADSPI_BK1_NCS PAL_LINE(GPIOB, 6U)
+#define LINE_LED2 PAL_LINE(GPIOB, 7U)
+#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U)
+#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U)
+#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U)
+#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U)
+#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U)
+#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U)
+#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U)
+#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U)
+#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U)
+#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U)
+#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U)
+#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U)
+#define LINE_LED3 PAL_LINE(GPIOB, 14U)
+#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U)
+#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U)
+#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U)
+#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U)
+#define LINE_ARD_A3 PAL_LINE(GPIOC, 1U)
+#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U)
+#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U)
+#define LINE_ADC1_IN12 PAL_LINE(GPIOC, 2U)
+#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U)
+#define LINE_ADC1_IN13 PAL_LINE(GPIOC, 3U)
+#define LINE_ARD_A4 PAL_LINE(GPIOC, 4U)
+#define LINE_ADC1_IN14 PAL_LINE(GPIOC, 4U)
+#define LINE_ARD_A5 PAL_LINE(GPIOC, 5U)
+#define LINE_ADC1_IN15 PAL_LINE(GPIOC, 5U)
+#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U)
+#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U)
+#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U)
+#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U)
+#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U)
+#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U)
+#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U)
+#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U)
+#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U)
+#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U)
+#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U)
+#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U)
+#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U)
+#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U)
+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
+#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U)
+#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U)
+#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U)
+#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U)
+#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U)
+#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U)
+#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U)
+#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U)
+#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U)
+#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U)
+#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U)
+#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U)
+#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U)
+#define LINE_USART2_TX PAL_LINE(GPIOD, 5U)
+#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U)
+#define LINE_USART2_RX PAL_LINE(GPIOD, 6U)
+#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U)
+#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U)
+#define LINE_USART3_RX PAL_LINE(GPIOD, 8U)
+#define LINE_STLK_RX PAL_LINE(GPIOD, 8U)
+#define LINE_USART3_TX PAL_LINE(GPIOD, 9U)
+#define LINE_STLK_TX PAL_LINE(GPIOD, 9U)
+#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U)
+#define LINE_QUADSPI_BK1_IO0 PAL_LINE(GPIOD, 11U)
+#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U)
+#define LINE_QUADSPI_BK1_IO1 PAL_LINE(GPIOD, 12U)
+#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U)
+#define LINE_QUADSPI_BK1_IO3 PAL_LINE(GPIOD, 13U)
+#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U)
+#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U)
+#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U)
+#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U)
+#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U)
+#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U)
+#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U)
+#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U)
+#define LINE_QUADSPI_BK1_IO2 PAL_LINE(GPIOE, 2U)
+#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U)
+#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U)
+#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U)
+#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U)
+#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U)
+#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U)
+#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U)
+#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U)
+#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U)
+#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U)
+#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U)
+#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U)
+#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U)
+#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U)
+#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U)
+#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U)
+#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U)
+#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U)
+#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U)
+#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U)
+#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U)
+#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U)
+#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U)
+#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U)
+#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U)
+#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U)
+#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U)
+#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U)
+#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U)
+#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U)
+#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U)
+#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U)
+#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U)
+#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U)
+#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U)
+#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U)
+#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U)
+#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U)
+#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U)
+#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U)
+#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U)
+#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U)
+#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U)
+#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U)
+#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U)
+#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U)
+#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U)
+#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U)
+#define LINE_USART6_RX PAL_LINE(GPIOG, 9U)
+#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U)
+#define LINE_USART6_TX PAL_LINE(GPIOG, 14U)
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - ZIO_D32 TIM2_CH1 (input pullup).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - ZIO_A8 ADC1_IN2 (input pullup).
+ * PA3 - ARD_A0 ADC1_IN3 (input pullup).
+ * PA4 - ZIO_D24 SPI3_NSS (input pullup).
+ * PA5 - ARD_D13 SPI1_SCK (input pullup).
+ * PA6 - ARD_D12 SPI1_MISO (input pullup).
+ * PA7 - ARD_D11 SPI1_MOSI ZIO_D71 (input pullup).
+ * PA8 - USB_SOF (alternate 10).
+ * PA9 - USB_VBUS (analog).
+ * PA10 - USB_ID (alternate 10).
+ * PA11 - USB_DM (alternate 10).
+ * PA12 - USB_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - ZIO_D20 I2S3_WS (alternate 6).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_ZIO_A8) | \
+ PIN_MODE_INPUT(GPIOA_ARD_A0) | \
+ PIN_MODE_INPUT(GPIOA_ZIO_D24) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D13) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D12) | \
+ PIN_MODE_INPUT(GPIOA_ARD_D11) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \
+ PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ZIO_D20))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ZIO_A8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \
+ PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOA_ZIO_A8) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \
+ PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \
+ PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_ID) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DM) | \
+ PIN_OSPEED_HIGH(GPIOA_USB_DP) | \
+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
+ PIN_OSPEED_HIGH(GPIOA_ZIO_D20))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_ZIO_A8) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \
+ PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \
+ PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_ZIO_D20))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_ZIO_A8) | \
+ PIN_ODR_HIGH(GPIOA_ARD_A0) | \
+ PIN_ODR_HIGH(GPIOA_ZIO_D24) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D13) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D12) | \
+ PIN_ODR_HIGH(GPIOA_ARD_D11) | \
+ PIN_ODR_HIGH(GPIOA_USB_SOF) | \
+ PIN_ODR_HIGH(GPIOA_USB_VBUS) | \
+ PIN_ODR_HIGH(GPIOA_USB_ID) | \
+ PIN_ODR_HIGH(GPIOA_USB_DM) | \
+ PIN_ODR_HIGH(GPIOA_USB_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_ZIO_D20))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOA_ZIO_A8, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
+ PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
+ PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
+ PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \
+ PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
+ PIN_AFIO_AF(GPIOA_ZIO_D20, 6U))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum).
+ * PB1 - ZIO_A6 ADC1_IN9 (input pullup).
+ * PB2 - ZIO_D27 QUADSPI_CLK (input pullup).
+ * PB3 - ZIO_D23 I2S3_CK (input pullup).
+ * PB4 - ZIO_D25 SPI3_MISO (input pullup).
+ * PB5 - ZIO_D22 I2S3_SD (input pullup).
+ * PB6 - ZIO_D26 QUADSPI_BK1_NCS (input pullup).
+ * PB7 - LED2 (output pushpull maximum).
+ * PB8 - ARD_D15 I2C1_SCL (input pullup).
+ * PB9 - ARD_D14 I2C1_SDA (input pullup).
+ * PB10 - ZIO_D36 TIM2_CH3 (input pullup).
+ * PB11 - ZIO_D35 TIM2_CH4 (input pullup).
+ * PB12 - ZIO_D19 I2S2_WS (input pullup).
+ * PB13 - ZIO_D18 I2S2_CK (input pullup).
+ * PB14 - LED3 (output pushpull maximum).
+ * PB15 - ZIO_D17 I2S2_SD (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_A6) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D27) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D23) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D25) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D22) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D26) | \
+ PIN_MODE_OUTPUT(GPIOB_LED2) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D15) | \
+ PIN_MODE_INPUT(GPIOB_ARD_D14) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D36) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D35) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D19) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D18) | \
+ PIN_MODE_OUTPUT(GPIOB_LED3) | \
+ PIN_MODE_INPUT(GPIOB_ZIO_D17))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D23) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D18) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D27) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D23) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D26) | \
+ PIN_OSPEED_HIGH(GPIOB_LED2) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \
+ PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D18) | \
+ PIN_OSPEED_HIGH(GPIOB_LED3) | \
+ PIN_OSPEED_HIGH(GPIOB_ZIO_D17))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D23) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED2) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \
+ PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D18) | \
+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \
+ PIN_PUPDR_PULLUP(GPIOB_ZIO_D17))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_A6) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D27) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D23) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D25) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D22) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D26) | \
+ PIN_ODR_LOW(GPIOB_LED2) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D15) | \
+ PIN_ODR_HIGH(GPIOB_ARD_D14) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D36) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D35) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D19) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D18) | \
+ PIN_ODR_LOW(GPIOB_LED3) | \
+ PIN_ODR_HIGH(GPIOB_ZIO_D17))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \
+ PIN_AFIO_AF(GPIOB_LED2, 0U))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
+ PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D18, 0U) | \
+ PIN_AFIO_AF(GPIOB_LED3, 0U) | \
+ PIN_AFIO_AF(GPIOB_ZIO_D17, 0U))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ARD_A1 ADC1_IN10 (input pullup).
+ * PC1 - ARD_A3 ADC1_IN11 (input pullup).
+ * PC2 - ZIO_A7 ADC1_IN12 (input pullup).
+ * PC3 - ARD_A2 ADC1_IN13 (input pullup).
+ * PC4 - ARD_A4 ADC1_IN14 (input pullup).
+ * PC5 - ARD_A5 ADC1_IN15 (input pullup).
+ * PC6 - ZIO_D16 I2S2_MCK (input pullup).
+ * PC7 - ZIO_D21 I2S3_MCK (input pullup).
+ * PC8 - ZIO_D43 SDMMC_D0 (input pullup).
+ * PC9 - ZIO_D44 SDMMC_D1 (input pullup).
+ * PC10 - ZIO_D45 SDMMC_D2 (input pullup).
+ * PC11 - ZIO_D46 SDMMC_D3 (input pullup).
+ * PC12 - ZIO_D47 SDMMC_CK (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - OSC32_IN (input floating).
+ * PC15 - OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A3) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_A7) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A2) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A4) | \
+ PIN_MODE_INPUT(GPIOC_ARD_A5) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D16) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D21) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D43) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D44) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D45) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D46) | \
+ PIN_MODE_INPUT(GPIOC_ZIO_D47) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \
+ PIN_OSPEED_VERYLOW(GPIOC_ARD_A3) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \
+ PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \
+ PIN_OSPEED_VERYLOW(GPIOC_ARD_A4) | \
+ PIN_OSPEED_VERYLOW(GPIOC_ARD_A5) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \
+ PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \
+ PIN_OSPEED_HIGH(GPIOC_BUTTON) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A3) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \
+ PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \
+ PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \
+ PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A3) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_A7) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A2) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A4) | \
+ PIN_ODR_HIGH(GPIOC_ARD_A5) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D16) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D21) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D43) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D44) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D45) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D46) | \
+ PIN_ODR_HIGH(GPIOC_ZIO_D47) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
+ PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A3, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
+ PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D21, 0U))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \
+ PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
+ PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - ZIO_D67 CAN1_RX (input pullup).
+ * PD1 - ZIO_D66 CAN1_TX (input pullup).
+ * PD2 - ZIO_D48 SDMMC_CMD (input pullup).
+ * PD3 - ZIO_D55 USART2_CTS (input pullup).
+ * PD4 - ZIO_D54 USART2_RTS (input pullup).
+ * PD5 - ZIO_D53 USART2_TX (input pullup).
+ * PD6 - ZIO_D52 USART2_RX (input pullup).
+ * PD7 - ZIO_D51 USART2_SCLK (input pullup).
+ * PD8 - USART3_RX STLK_RX (alternate 7).
+ * PD9 - USART3_TX STLK_TX (alternate 7).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - ZIO_D30 QUADSPI_BK1_IO0 (input pullup).
+ * PD12 - ZIO_D29 QUADSPI_BK1_IO1 (input pullup).
+ * PD13 - ZIO_D28 QUADSPI_BK1_IO3 (input pullup).
+ * PD14 - ARD_D10 SPI1_NSS (input pullup).
+ * PD15 - ARD_D9 TIM4_CH4 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D66) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D48) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D55) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D54) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D53) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D52) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D51) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D30) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D29) | \
+ PIN_MODE_INPUT(GPIOD_ZIO_D28) | \
+ PIN_MODE_INPUT(GPIOD_ARD_D10) | \
+ PIN_MODE_INPUT(GPIOD_ARD_D9))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \
+ PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \
+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D30) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D29) | \
+ PIN_OSPEED_HIGH(GPIOD_ZIO_D28) | \
+ PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \
+ PIN_OSPEED_HIGH(GPIOD_ARD_D9))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \
+ PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \
+ PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \
+ PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \
+ PIN_PUPDR_PULLUP(GPIOD_ARD_D9))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D66) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D48) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D55) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D54) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D53) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D52) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D51) | \
+ PIN_ODR_HIGH(GPIOD_USART3_RX) | \
+ PIN_ODR_HIGH(GPIOD_USART3_TX) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D30) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D29) | \
+ PIN_ODR_HIGH(GPIOD_ZIO_D28) | \
+ PIN_ODR_HIGH(GPIOD_ARD_D10) | \
+ PIN_ODR_HIGH(GPIOD_ARD_D9))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D51, 0U))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \
+ PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \
+ PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \
+ PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \
+ PIN_AFIO_AF(GPIOD_ARD_D9, 0U))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - ZIO_D34 TIM4_ETR (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - ZIO_D31 ZIO_D56 QUADSPI_BK1_IO2(input pullup).
+ * PE3 - ZIO_D60 SAI1_SD_B (input pullup).
+ * PE4 - ZIO_D57 SAI1_FS_A (input pullup).
+ * PE5 - ZIO_D58 SAI1_SCK_A (input pullup).
+ * PE6 - ZIO_D59 SAI1_SD_A (input pullup).
+ * PE7 - ZIO_D41 TIM1_ETR (input pullup).
+ * PE8 - ZIO_D42 TIM1_CH1N (input pullup).
+ * PE9 - ARD_D6 TIM1_CH1 (input pullup).
+ * PE10 - ZIO_D40 TIM1_CH2N (input pullup).
+ * PE11 - ARD_D5 TIM1_CH2 (input pullup).
+ * PE12 - ZIO_D39 TIM1_CH3N (input pullup).
+ * PE13 - ARD_D3 TIM1_CH3 (input pullup).
+ * PE14 - ZIO_D38 (input pullup).
+ * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D31) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D60) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D57) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D58) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D59) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D41) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D42) | \
+ PIN_MODE_INPUT(GPIOE_ARD_D6) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D40) | \
+ PIN_MODE_INPUT(GPIOE_ARD_D5) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D39) | \
+ PIN_MODE_INPUT(GPIOE_ARD_D3) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D38) | \
+ PIN_MODE_INPUT(GPIOE_ZIO_D37))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \
+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \
+ PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \
+ PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \
+ PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \
+ PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \
+ PIN_OSPEED_HIGH(GPIOE_ZIO_D37))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \
+ PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \
+ PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \
+ PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \
+ PIN_PUPDR_PULLUP(GPIOE_ZIO_D37))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D31) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D60) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D57) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D58) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D59) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D41) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D42) | \
+ PIN_ODR_HIGH(GPIOE_ARD_D6) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D40) | \
+ PIN_ODR_HIGH(GPIOE_ARD_D5) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D39) | \
+ PIN_ODR_HIGH(GPIOE_ARD_D3) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D38) | \
+ PIN_ODR_HIGH(GPIOE_ZIO_D37))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D41, 0U))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \
+ PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \
+ PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \
+ PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \
+ PIN_AFIO_AF(GPIOE_ZIO_D37, 0U))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - ZIO_D68 I2C2_SDA (input pullup).
+ * PF1 - ZIO_D69 I2C2_SCL (input pullup).
+ * PF2 - ZIO_D70 I2C2_SMBA (input pullup).
+ * PF3 - PIN3 (input pullup).
+ * PF4 - PIN4 (input pullup).
+ * PF5 - PIN5 (input pullup).
+ * PF6 - PIN6 (input pullup).
+ * PF7 - ZIO_D62 SAI1_MCLK_B (input pullup).
+ * PF8 - ZIO_D61 SAI1_SCK_B (input pullup).
+ * PF9 - ZIO_D63 SAI1_FS_B (input pullup).
+ * PF10 - PIN10 (input pullup).
+ * PF11 - PIN11 (input pullup).
+ * PF12 - ARD_D8 (input pullup).
+ * PF13 - ARD_D7 (input pullup).
+ * PF14 - ARD_D4 (input pullup).
+ * PF15 - ARD_D2 (input pullup).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \
+ PIN_MODE_INPUT(GPIOF_ZIO_D69) | \
+ PIN_MODE_INPUT(GPIOF_ZIO_D70) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_ZIO_D62) | \
+ PIN_MODE_INPUT(GPIOF_ZIO_D61) | \
+ PIN_MODE_INPUT(GPIOF_ZIO_D63) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_ARD_D8) | \
+ PIN_MODE_INPUT(GPIOF_ARD_D7) | \
+ PIN_MODE_INPUT(GPIOF_ARD_D4) | \
+ PIN_MODE_INPUT(GPIOF_ARD_D2))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D62) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D61) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D63) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \
+ PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \
+ PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN3) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN4) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
+ PIN_OSPEED_HIGH(GPIOF_ZIO_D62) | \
+ PIN_OSPEED_HIGH(GPIOF_ZIO_D61) | \
+ PIN_OSPEED_HIGH(GPIOF_ZIO_D63) | \
+ PIN_OSPEED_HIGH(GPIOF_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \
+ PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \
+ PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \
+ PIN_OSPEED_VERYLOW(GPIOF_ARD_D2))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \
+ PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \
+ PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOF_ZIO_D62) | \
+ PIN_PUPDR_PULLUP(GPIOF_ZIO_D61) | \
+ PIN_PUPDR_PULLUP(GPIOF_ZIO_D63) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \
+ PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \
+ PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \
+ PIN_PUPDR_PULLUP(GPIOF_ARD_D2))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \
+ PIN_ODR_HIGH(GPIOF_ZIO_D69) | \
+ PIN_ODR_HIGH(GPIOF_ZIO_D70) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_ZIO_D62) | \
+ PIN_ODR_HIGH(GPIOF_ZIO_D61) | \
+ PIN_ODR_HIGH(GPIOF_ZIO_D63) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_ARD_D8) | \
+ PIN_ODR_HIGH(GPIOF_ARD_D7) | \
+ PIN_ODR_HIGH(GPIOF_ARD_D4) | \
+ PIN_ODR_HIGH(GPIOF_ARD_D2))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \
+ PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \
+ PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOF_ZIO_D62, 0U))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0U) | \
+ PIN_AFIO_AF(GPIOF_ZIO_D63, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \
+ PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \
+ PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \
+ PIN_AFIO_AF(GPIOF_ARD_D2, 0U))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - ZIO_D65 (input pullup).
+ * PG1 - ZIO_D64 (input pullup).
+ * PG2 - ZIO_D49 (input pullup).
+ * PG3 - ZIO_D50 (input pullup).
+ * PG4 - PIN4 (input pullup).
+ * PG5 - PIN5 (input pullup).
+ * PG6 - USB_GPIO_OUT (output pushpull maximum).
+ * PG7 - USB_GPIO_IN (input pullup).
+ * PG8 - PIN8 (input pullup).
+ * PG9 - ARD_D0 USART6_RX (input pullup).
+ * PG10 - PIN10 (input pullup).
+ * PG11 - PIN11 (input pullup).
+ * PG12 - PIN12 (input pullup).
+ * PG13 - PIN13 (input pullup).
+ * PG14 - ARD_D1 USART6_TX (input pullup).
+ * PG15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_ZIO_D65) | \
+ PIN_MODE_INPUT(GPIOG_ZIO_D64) | \
+ PIN_MODE_INPUT(GPIOG_ZIO_D49) | \
+ PIN_MODE_INPUT(GPIOG_ZIO_D50) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_OUTPUT(GPIOG_USB_GPIO_OUT) | \
+ PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_ARD_D0) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_ARD_D1) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_ZIO_D65) | \
+ PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \
+ PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \
+ PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \
+ PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \
+ PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \
+ PIN_OSPEED_HIGH(GPIOG_ARD_D0) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
+ PIN_OSPEED_HIGH(GPIOG_ARD_D1) | \
+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \
+ PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \
+ PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \
+ PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \
+ PIN_ODR_HIGH(GPIOG_ZIO_D64) | \
+ PIN_ODR_HIGH(GPIOG_ZIO_D49) | \
+ PIN_ODR_HIGH(GPIOG_ZIO_D50) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \
+ PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_ARD_D0) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_ARD_D1) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \
+ PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \
+ PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \
+ PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input pullup).
+ * PH3 - PIN3 (input pullup).
+ * PH4 - PIN4 (input pullup).
+ * PH5 - PIN5 (input pullup).
+ * PH6 - PIN6 (input pullup).
+ * PH7 - PIN7 (input pullup).
+ * PH8 - PIN8 (input pullup).
+ * PH9 - PIN9 (input pullup).
+ * PH10 - PIN10 (input pullup).
+ * PH11 - PIN11 (input pullup).
+ * PH12 - PIN12 (input pullup).
+ * PH13 - PIN13 (input pullup).
+ * PH14 - PIN14 (input pullup).
+ * PH15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \
+ PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input pullup).
+ * PI1 - PIN1 (input pullup).
+ * PI2 - PIN2 (input pullup).
+ * PI3 - PIN3 (input pullup).
+ * PI4 - PIN4 (input pullup).
+ * PI5 - PIN5 (input pullup).
+ * PI6 - PIN6 (input pullup).
+ * PI7 - PIN7 (input pullup).
+ * PI8 - PIN8 (input pullup).
+ * PI9 - PIN9 (input pullup).
+ * PI10 - PIN10 (input pullup).
+ * PI11 - PIN11 (input pullup).
+ * PI12 - PIN12 (input pullup).
+ * PI13 - PIN13 (input pullup).
+ * PI14 - PIN14 (input pullup).
+ * PI15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
+
+/*
+ * GPIOJ setup:
+ *
+ * PJ0 - PIN0 (input pullup).
+ * PJ1 - PIN1 (input pullup).
+ * PJ2 - PIN2 (input pullup).
+ * PJ3 - PIN3 (input pullup).
+ * PJ4 - PIN4 (input pullup).
+ * PJ5 - PIN5 (input pullup).
+ * PJ6 - PIN6 (input pullup).
+ * PJ7 - PIN7 (input pullup).
+ * PJ8 - PIN8 (input pullup).
+ * PJ9 - PIN9 (input pullup).
+ * PJ10 - PIN10 (input pullup).
+ * PJ11 - PIN11 (input pullup).
+ * PJ12 - PIN12 (input pullup).
+ * PJ13 - PIN13 (input pullup).
+ * PJ14 - PIN14 (input pullup).
+ * PJ15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \
+ PIN_MODE_INPUT(GPIOJ_PIN1) | \
+ PIN_MODE_INPUT(GPIOJ_PIN2) | \
+ PIN_MODE_INPUT(GPIOJ_PIN3) | \
+ PIN_MODE_INPUT(GPIOJ_PIN4) | \
+ PIN_MODE_INPUT(GPIOJ_PIN5) | \
+ PIN_MODE_INPUT(GPIOJ_PIN6) | \
+ PIN_MODE_INPUT(GPIOJ_PIN7) | \
+ PIN_MODE_INPUT(GPIOJ_PIN8) | \
+ PIN_MODE_INPUT(GPIOJ_PIN9) | \
+ PIN_MODE_INPUT(GPIOJ_PIN10) | \
+ PIN_MODE_INPUT(GPIOJ_PIN11) | \
+ PIN_MODE_INPUT(GPIOJ_PIN12) | \
+ PIN_MODE_INPUT(GPIOJ_PIN13) | \
+ PIN_MODE_INPUT(GPIOJ_PIN14) | \
+ PIN_MODE_INPUT(GPIOJ_PIN15))
+#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOJ_PIN15))
+#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOJ_PIN15))
+#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOJ_PIN15))
+#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \
+ PIN_ODR_HIGH(GPIOJ_PIN1) | \
+ PIN_ODR_HIGH(GPIOJ_PIN2) | \
+ PIN_ODR_HIGH(GPIOJ_PIN3) | \
+ PIN_ODR_HIGH(GPIOJ_PIN4) | \
+ PIN_ODR_HIGH(GPIOJ_PIN5) | \
+ PIN_ODR_HIGH(GPIOJ_PIN6) | \
+ PIN_ODR_HIGH(GPIOJ_PIN7) | \
+ PIN_ODR_HIGH(GPIOJ_PIN8) | \
+ PIN_ODR_HIGH(GPIOJ_PIN9) | \
+ PIN_ODR_HIGH(GPIOJ_PIN10) | \
+ PIN_ODR_HIGH(GPIOJ_PIN11) | \
+ PIN_ODR_HIGH(GPIOJ_PIN12) | \
+ PIN_ODR_HIGH(GPIOJ_PIN13) | \
+ PIN_ODR_HIGH(GPIOJ_PIN14) | \
+ PIN_ODR_HIGH(GPIOJ_PIN15))
+#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN7, 0U))
+#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOJ_PIN15, 0U))
+
+/*
+ * GPIOK setup:
+ *
+ * PK0 - PIN0 (input pullup).
+ * PK1 - PIN1 (input pullup).
+ * PK2 - PIN2 (input pullup).
+ * PK3 - PIN3 (input pullup).
+ * PK4 - PIN4 (input pullup).
+ * PK5 - PIN5 (input pullup).
+ * PK6 - PIN6 (input pullup).
+ * PK7 - PIN7 (input pullup).
+ * PK8 - PIN8 (input pullup).
+ * PK9 - PIN9 (input pullup).
+ * PK10 - PIN10 (input pullup).
+ * PK11 - PIN11 (input pullup).
+ * PK12 - PIN12 (input pullup).
+ * PK13 - PIN13 (input pullup).
+ * PK14 - PIN14 (input pullup).
+ * PK15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \
+ PIN_MODE_INPUT(GPIOK_PIN1) | \
+ PIN_MODE_INPUT(GPIOK_PIN2) | \
+ PIN_MODE_INPUT(GPIOK_PIN3) | \
+ PIN_MODE_INPUT(GPIOK_PIN4) | \
+ PIN_MODE_INPUT(GPIOK_PIN5) | \
+ PIN_MODE_INPUT(GPIOK_PIN6) | \
+ PIN_MODE_INPUT(GPIOK_PIN7) | \
+ PIN_MODE_INPUT(GPIOK_PIN8) | \
+ PIN_MODE_INPUT(GPIOK_PIN9) | \
+ PIN_MODE_INPUT(GPIOK_PIN10) | \
+ PIN_MODE_INPUT(GPIOK_PIN11) | \
+ PIN_MODE_INPUT(GPIOK_PIN12) | \
+ PIN_MODE_INPUT(GPIOK_PIN13) | \
+ PIN_MODE_INPUT(GPIOK_PIN14) | \
+ PIN_MODE_INPUT(GPIOK_PIN15))
+#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOK_PIN15))
+#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \
+ PIN_OSPEED_VERYLOW(GPIOK_PIN15))
+#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOK_PIN15))
+#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \
+ PIN_ODR_HIGH(GPIOK_PIN1) | \
+ PIN_ODR_HIGH(GPIOK_PIN2) | \
+ PIN_ODR_HIGH(GPIOK_PIN3) | \
+ PIN_ODR_HIGH(GPIOK_PIN4) | \
+ PIN_ODR_HIGH(GPIOK_PIN5) | \
+ PIN_ODR_HIGH(GPIOK_PIN6) | \
+ PIN_ODR_HIGH(GPIOK_PIN7) | \
+ PIN_ODR_HIGH(GPIOK_PIN8) | \
+ PIN_ODR_HIGH(GPIOK_PIN9) | \
+ PIN_ODR_HIGH(GPIOK_PIN10) | \
+ PIN_ODR_HIGH(GPIOK_PIN11) | \
+ PIN_ODR_HIGH(GPIOK_PIN12) | \
+ PIN_ODR_HIGH(GPIOK_PIN13) | \
+ PIN_ODR_HIGH(GPIOK_PIN14) | \
+ PIN_ODR_HIGH(GPIOK_PIN15))
+#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN1, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN2, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN3, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN4, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN5, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN6, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN7, 0U))
+#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN9, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN10, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN11, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN12, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN13, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN14, 0U) | \
+ PIN_AFIO_AF(GPIOK_PIN15, 0U))
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* BOARD_H */
diff --git a/os/hal/boards/ST_NUCLEO144_F413ZH/board.mk b/os/hal/boards/ST_NUCLEO144_F413ZH/board.mk new file mode 100644 index 000000000..6403f41de --- /dev/null +++ b/os/hal/boards/ST_NUCLEO144_F413ZH/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F413ZH/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F413ZH
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.chcfg new file mode 100644 index 000000000..5b07d87bc --- /dev/null +++ b/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.chcfg @@ -0,0 +1,1453 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+ <configuration_settings>
+ <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+ <output_path>..</output_path>
+ <hal_version>5.0.x</hal_version>
+ </configuration_settings>
+ <board_name>STMicroelectronics STM32 Nucleo144-F413ZH</board_name>
+ <board_id>ST_NUCLEO144_F413ZH</board_id>
+ <board_functions></board_functions>
+ <subtype>STM32F413xx</subtype>
+ <clocks
+ HSEFrequency="8000000"
+ HSEBypass="true"
+ LSEFrequency="0"
+ LSEBypass="false"
+ VDD="300" />
+ <ports>
+ <GPIOA>
+ <pin0
+ ID="ZIO_D32 TIM2_CH1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_A8 ADC1_IN2"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ARD_A0 ADC1_IN3"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="ZIO_D24 SPI3_NSS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="ARD_D13 SPI1_SCK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="ARD_D12 SPI1_MISO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="ARD_D11 SPI1_MOSI ZIO_D71"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="USB_SOF"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin9
+ ID="USB_VBUS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Analog"
+ Alternate="0" />
+ <pin10
+ ID="USB_ID"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin11
+ ID="USB_DM"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin12
+ ID="USB_DP"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="10" />
+ <pin13
+ ID="SWDIO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin14
+ ID="SWCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="0" />
+ <pin15
+ ID="ZIO_D20 I2S3_WS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="6" />
+ </GPIOA>
+ <GPIOB>
+ <pin0
+ ID="ZIO_D33 TIM3_CH3 LED1"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin1
+ ID="ZIO_A6 ADC1_IN9"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_D27 QUADSPI_CLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ZIO_D23 I2S3_CK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="ZIO_D25 SPI3_MISO"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="ZIO_D22 I2S3_SD"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="ZIO_D26 QUADSPI_BK1_NCS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="LED2"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin8
+ ID="ARD_D15 I2C1_SCL"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="ARD_D14 I2C1_SDA"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="ZIO_D36 TIM2_CH3"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="ZIO_D35 TIM2_CH4"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="ZIO_D19 I2S2_WS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="ZIO_D18 I2S2_CK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="LED3"
+ Type="PushPull"
+ Level="Low"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Output"
+ Alternate="0" />
+ <pin15
+ ID="ZIO_D17 I2S2_SD"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOB>
+ <GPIOC>
+ <pin0
+ ID="ARD_A1 ADC1_IN10"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="ARD_A3 ADC1_IN11"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_A7 ADC1_IN12"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ARD_A2 ADC1_IN13"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="ARD_A4 ADC1_IN14"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="ARD_A5 ADC1_IN15"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="ZIO_D16 I2S2_MCK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="ZIO_D21 I2S3_MCK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="ZIO_D43 SDMMC_D0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="ZIO_D44 SDMMC_D1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="ZIO_D45 SDMMC_D2"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="ZIO_D46 SDMMC_D3"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="ZIO_D47 SDMMC_CK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="BUTTON"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="OSC32_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="OSC32_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOC>
+ <GPIOD>
+ <pin0
+ ID="ZIO_D67 CAN1_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="ZIO_D66 CAN1_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_D48 SDMMC_CMD"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ZIO_D55 USART2_CTS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="ZIO_D54 USART2_RTS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="ZIO_D53 USART2_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="ZIO_D52 USART2_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="ZIO_D51 USART2_SCLK"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="USART3_RX STLK_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin9
+ ID="USART3_TX STLK_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Alternate"
+ Alternate="7" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="ZIO_D30 QUADSPI_BK1_IO0"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="ZIO_D29 QUADSPI_BK1_IO1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="ZIO_D28 QUADSPI_BK1_IO3"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="ARD_D10 SPI1_NSS"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="ARD_D9 TIM4_CH4"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOD>
+ <GPIOE>
+ <pin0
+ ID="ZIO_D34 TIM4_ETR"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_D31 ZIO_D56 QUADSPI_BK1_IO2"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ZIO_D60 SAI1_SD_B"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID="ZIO_D57 SAI1_FS_A"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID="ZIO_D58 SAI1_SCK_A"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="ZIO_D59 SAI1_SD_A"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="ZIO_D41 TIM1_ETR"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="ZIO_D42 TIM1_CH1N"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="ARD_D6 TIM1_CH1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID="ZIO_D40 TIM1_CH2N"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID="ARD_D5 TIM1_CH2"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="ZIO_D39 TIM1_CH3N"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="ARD_D3 TIM1_CH3"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="ZIO_D38"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="ZIO_D37 TIM1_BKIN1"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOE>
+ <GPIOF>
+ <pin0
+ ID="ZIO_D68 I2C2_SDA"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="ZIO_D69 I2C2_SCL"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_D70 I2C2_SMBA"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID="ZIO_D62 SAI1_MCLK_B"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID="ZIO_D61 SAI1_SCK_B"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="ZIO_D63 SAI1_FS_B"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID="ARD_D8"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID="ARD_D7"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="ARD_D4"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID="ARD_D2"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOF>
+ <GPIOG>
+ <pin0
+ ID="ZIO_D65"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="ZIO_D64"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID="ZIO_D49"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID="ZIO_D50"
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID="USB_GPIO_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Output"
+ Alternate="0" />
+ <pin7
+ ID="USB_GPIO_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID="ARD_D0 USART6_RX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID="ARD_D1 USART6_TX"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOG>
+ <GPIOH>
+ <pin0
+ ID="OSC_IN"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID="OSC_OUT"
+ Type="PushPull"
+ Level="High"
+ Speed="Maximum"
+ Resistor="Floating"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOH>
+ <GPIOI>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOI>
+ <GPIOJ>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOJ>
+ <GPIOK>
+ <pin0
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin1
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin2
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin3
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin4
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin5
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin6
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin7
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin8
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin9
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin10
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin11
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin12
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin13
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin14
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ <pin15
+ ID=""
+ Type="PushPull"
+ Level="High"
+ Speed="Minimum"
+ Resistor="PullUp"
+ Mode="Input"
+ Alternate="0" />
+ </GPIOK>
+ </ports>
+</board>
diff --git a/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.fmpp b/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.fmpp new file mode 100644 index 000000000..41754c141 --- /dev/null +++ b/os/hal/boards/ST_NUCLEO144_F413ZH/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +} diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c index 542e08879..1cfa9c49c 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c @@ -256,9 +256,15 @@ void stm32_clock_init(void) { #endif /* STM32_ACTIVATE_PLLSAI */
/* Other clock-related settings (dividers, MCO etc).*/
+#if !defined(STM32F413xx)
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
+#else
+ RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
+ STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
+#endif
#if STM32_HAS_RCC_DCKCFGR
/* DCKCFGR register initialization, note, must take care of the _OFF
@@ -271,7 +277,8 @@ void stm32_clock_init(void) { #if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
-#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+#if (STM32_ACTIVATE_PLLSAI == TRUE) && \
+ (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF)
dckcfgr |= STM32_PLLSAIDIVR;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
@@ -279,9 +286,15 @@ void stm32_clock_init(void) { DCKCFGR register.*/
dckcfgr |= STM32_CK48MSEL;
#endif
+#if !defined(STM32F413xx)
RCC->DCKCFGR = dckcfgr |
STM32_TIMPRE | STM32_PLLSAIDIVR |
STM32_PLLSAIDIVQ | STM32_PLLI2SDIVQ;
+#else
+ RCC->DCKCFGR = dckcfgr |
+ STM32_TIMPRE |
+ STM32_PLLDIVR | STM32_PLLI2SDIVR;
+#endif
}
#endif
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h index e075816c8..531984060 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h @@ -43,8 +43,6 @@ #ifndef HAL_LLD_TYPE1_H
#define HAL_LLD_TYPE1_H
-#include "stm32_registry.h"
-
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
@@ -1026,8 +1024,8 @@ #endif /* !defined(STM32F4XX) */
/**
- * @brief Maximum frequency thresholds and wait states for flash access.
- * @note The values are valid for 2.7V to 3.6V supply range.
+ * @name Maximum frequency thresholds and wait states for flash access.
+ * @{
*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
defined(STM32F40_41xxx) || defined(STM32F446xx) || \
@@ -1253,6 +1251,7 @@ #error "invalid VDD voltage specified"
#endif
#endif /* STM32F2XX */
+/** @} */
/*
* HSI related checks.
@@ -1283,6 +1282,11 @@ #error "HSI not enabled, required by STM32_I2SSRC"
#endif
+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLI2S) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_I2SSRC"
+#endif
+
#if ((STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S)) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI)
@@ -1341,6 +1345,11 @@ #error "HSE not enabled, required by STM32_I2SSRC"
#endif
+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
+ (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_PLLI2SSRC"
+#endif
+
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#error "HSE not enabled, required by STM32_RTCSEL"
#endif
@@ -1741,7 +1750,7 @@ #if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
-#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN
+#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN
#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
#else
#error "invalid STM32_PLLI2SSRC value specified"
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h index 5bf326b92..607d3e7ab 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h @@ -15,7 +15,7 @@ */
/**
- * @file STM32F4xx/hal_lld.h
+ * @file STM32F4xx/hal_lld_type2.h
* @brief STM32F4xx/STM32F2xx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
@@ -26,24 +26,15 @@ * - STM32_VDD (as hundredths of Volt).
* .
* One of the following macros must also be defined:
- * - STM32F2XX for High-performance STM32F2 devices.
- * - STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx,
- * STM32F446xx for High-performance STM32F4 devices of
- * Foundation line.
- * - STM32F401xx, STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx
- * for High-performance STM32F4 devices of Access line.
- * - STM32F427xx, STM32F437xx, STM32F429xx, STM32F439xx, STM32F469xx,
- * STM32F479xx for High-performance STM32F4 devices of Advanced line.
+ * - STM32F413xx for High-performance STM32F4 devices of Access line.
* .
*
* @addtogroup HAL
* @{
*/
-#ifndef HAL_LLD_H
-#define HAL_LLD_H
-
-#include "stm32_registry.h"
+#ifndef HAL_LLD_TYPE2_H
+#define HAL_LLD_TYPE2_H
/*===========================================================================*/
/* Driver constants. */
@@ -58,66 +49,9 @@ * @name Platform identification macros
* @{
*/
-#if defined(STM32F205xx) || defined(__DOXYGEN__)
-#define PLATFORM_NAME "STM32F205 High Performance"
-
-#elif defined(STM32F207xx)
-#define PLATFORM_NAME "STM32F207 High Performance"
-
-#elif defined(STM32F215xx)
-#define PLATFORM_NAME "STM32F215 High Performance"
-
-#elif defined(STM32F217xx)
-#define PLATFORM_NAME "STM32F217 High Performance"
-
-#elif defined(STM32F401xx)
-#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
-
-#elif defined(STM32F405xx)
-#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
-
-#elif defined(STM32F407xx)
-#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
-
-#elif defined(STM32F410xx)
-#define PLATFORM_NAME "STM32F410 High Performance with DSP and FPU"
-
-#elif defined(STM32F411xx)
-#define PLATFORM_NAME "STM32F411 High Performance with DSP and FPU"
-
-#elif defined(STM32F412xx)
-#define PLATFORM_NAME "STM32F412 High Performance with DSP and FPU"
-
-#elif defined(STM32F413xx)
+#if defined(STM32F413xx)
#define PLATFORM_NAME "STM32F413 High Performance with DSP and FPU"
-#elif defined(STM32F415xx)
-#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
-
-#elif defined(STM32F417xx)
-#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
-
-#elif defined(STM32F427xx)
-#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
-
-#elif defined(STM32F429xx)
-#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
-
-#elif defined(STM32F437xx)
-#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
-
-#elif defined(STM32F439xx)
-#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
-
-#elif defined(STM32F446xx)
-#define PLATFORM_NAME "STM32F446 High Performance with DSP and FPU"
-
-#elif defined(STM32F469xx)
-#define PLATFORM_NAME "STM32F469 High Performance with DSP and FPU"
-
-#elif defined(STM32F479xx)
-#define PLATFORM_NAME "STM32F479 High Performance with DSP and FPU"
-
#else
#error "STM32F2xx/F4xx device not specified"
#endif
@@ -127,13 +61,12 @@ * @name Absolute Maximum Ratings
* @{
*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || \
- defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(__DOXYGEN__)
+
+#if defined(STM32F413xx) || defined(__DOXYGEN__)
/**
* @brief Absolute maximum system clock.
*/
-#define STM32_SYSCLK_MAX 180000000
+#define STM32_SYSCLK_MAX 100000000
/**
* @brief Maximum HSE clock frequency.
@@ -151,7 +84,7 @@ #define STM32_HSECLK_MIN 4000000
/**
- * @brief Minimum HSE clock frequency.
+ * @brief Minimum HSE clock frequency using an external source.
*/
#define STM32_HSECLK_BYP_MIN 1000000
@@ -161,7 +94,7 @@ #define STM32_LSECLK_MAX 32768
/**
- * @brief Maximum LSE clock frequency.
+ * @brief Maximum LSE clock frequency using an external source.
*/
#define STM32_LSECLK_BYP_MAX 1000000
@@ -188,12 +121,12 @@ /**
* @brief Minimum PLLs VCO clock frequency.
*/
-#define STM32_PLLVCO_MIN 192000000
+#define STM32_PLLVCO_MIN 100000000
/**
* @brief Maximum PLL output clock frequency.
*/
-#define STM32_PLLOUT_MAX 180000000
+#define STM32_PLLOUT_MAX 100000000
/**
* @brief Minimum PLL output clock frequency.
@@ -201,133 +134,20 @@ #define STM32_PLLOUT_MIN 24000000
/**
- * @brief Maximum PLLI2S output clock frequency.
- */
-#define STM32_PLLI2SOUT_MAX 216000000
-
-/**
- * @brief Maximum PLLSAI output clock frequency.
- */
-#define STM32_PLLSAIOUT_MAX 216000000
-
-/**
* @brief Maximum APB1 clock frequency.
*/
-#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
+#define STM32_PCLK1_MAX 50000000
/**
* @brief Maximum APB2 clock frequency.
*/
-#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
+#define STM32_PCLK2_MAX 100000000
/**
* @brief Maximum SPI/I2S clock frequency.
*/
-#define STM32_SPII2S_MAX 45000000
-#endif
-
-#if defined(STM32F40_41xxx)
-#define STM32_SYSCLK_MAX 168000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 168000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 42000000
-#define STM32_PCLK2_MAX 84000000
-#define STM32_SPII2S_MAX 42000000
-#endif
-
-#if defined(STM32F401xx)
-#define STM32_SYSCLK_MAX 84000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 84000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 42000000
-#define STM32_PCLK2_MAX 84000000
-#define STM32_SPII2S_MAX 42000000
-#endif
-
-#if defined(STM32F410xx) || defined(STM32F411xx) || \
- defined(STM32F412xx) || defined(STM32F413xx)
-#define STM32_SYSCLK_MAX 100000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 100000000
-#define STM32_PLLOUT_MAX 100000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 50000000
-#define STM32_PCLK2_MAX 100000000
#define STM32_SPII2S_MAX 50000000
#endif
-
-#if defined(STM32F446xx)
-#define STM32_SYSCLK_MAX 180000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 50000000
-#define STM32_HSECLK_MIN 4000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2100000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 100000000
-#define STM32_PLLOUT_MAX 180000000
-#define STM32_PLLOUT_MIN 12500000
-#define STM32_PLLI2SOUT_MAX 216000000
-#define STM32_PLLSAIOUT_MAX 216000000
-#define STM32_PCLK1_MAX (STM32_PLLOUT_MAX / 4)
-#define STM32_PCLK2_MAX (STM32_PLLOUT_MAX / 2)
-#define STM32_SPII2S_MAX 45000000
-#endif
-
-#if defined(STM32F2XX)
-#define STM32_SYSCLK_MAX 120000000
-#define STM32_HSECLK_MAX 26000000
-#define STM32_HSECLK_BYP_MAX 26000000
-#define STM32_HSECLK_MIN 1000000
-#define STM32_HSECLK_BYP_MIN 1000000
-#define STM32_LSECLK_MAX 32768
-#define STM32_LSECLK_BYP_MAX 1000000
-#define STM32_LSECLK_MIN 32768
-#define STM32_PLLIN_MAX 2000000
-#define STM32_PLLIN_MIN 950000
-#define STM32_PLLVCO_MAX 432000000
-#define STM32_PLLVCO_MIN 192000000
-#define STM32_PLLOUT_MAX 120000000
-#define STM32_PLLOUT_MIN 24000000
-#define STM32_PCLK1_MAX 30000000
-#define STM32_PCLK2_MAX 60000000
-#define STM32_SPII2S_MAX 30000000
-#endif
/** @} */
/**
@@ -412,10 +232,6 @@ #define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */
#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */
-#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */
-#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
-#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
-
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
@@ -442,11 +258,6 @@ */
#define STM32_PLLI2SM_MASK (31 << 0) /**< PLLI2SM mask. */
#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */
-#define STM32_PLLI2SP_MASK (3 << 16) /**< PLLI2SP mask. */
-#define STM32_PLLI2SP_DIV2 (0 << 16) /**< PLLI2S clock divided by 2. */
-#define STM32_PLLI2SP_DIV4 (1 << 16) /**< PLLI2S clock divided by 4. */
-#define STM32_PLLI2SP_DIV6 (2 << 16) /**< PLLI2S clock divided by 6. */
-#define STM32_PLLI2SP_DIV8 (3 << 16) /**< PLLI2S clock divided by 8. */
#define STM32_PLLI2SSRC_MASK (1 << 22) /**< PLLI2SSRC mask. */
#define STM32_PLLI2SSRC_PLLSRC (0 << 22) /**< PLLI2SSRC is selected PLL
source. */
@@ -456,21 +267,6 @@ /** @} */
/**
- * @name RCC_PLLSAICFGR register bits definitions
- * @{
- */
-#define STM32_PLLSAIM_MASK (31 << 0) /**< PLLSAIM mask. */
-#define STM32_PLLSAIN_MASK (511 << 6) /**< PLLSAIN mask. */
-#define STM32_PLLSAIP_MASK (3 << 16) /**< PLLSAIP mask. */
-#define STM32_PLLSAIP_DIV2 (0 << 16) /**< PLLSAI clock divided by 2. */
-#define STM32_PLLSAIP_DIV4 (1 << 16) /**< PLLSAI clock divided by 4. */
-#define STM32_PLLSAIP_DIV6 (2 << 16) /**< PLLSAI clock divided by 6. */
-#define STM32_PLLSAIP_DIV8 (3 << 16) /**< PLLSAI clock divided by 8. */
-#define STM32_PLLSAIQ_MASK (15 << 24) /**< PLLSAIQ mask. */
-#define STM32_PLLSAIR_MASK (7 << 28) /**< PLLSAIR mask. */
-/** @} */
-
-/**
* @name RCC_BDCR register bits definitions
* @{
*/
@@ -485,20 +281,8 @@ * @name RCC_DCKCFGR register bits definitions
* @{
*/
-#if !defined(STM32F413xx) || defined(_DOXYGEN__)
-#define STM32_PLLI2SDIVQ_MASK (31 << 0) /**< PLLI2SDIVQ mask. */
-#define STM32_PLLSAIDIVQ_MASK (31 << 8) /**< PLLSAIDIVQ mask. */
-#else
-#define STM32_PLLI2SDIVR_MASK (31 << 0)
-#define STM32_PLLSAIDIVR_MASK (31 << 8)
-#endif
-
-#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */
-#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */
-#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
-#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
-#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
-#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
+#define STM32_PLLI2SDIVR_MASK (31 << 0) /**< PLLI2SDIVR mask. */
+#define STM32_PLLDIVR_MASK (31 << 8) /**< PLLDIVR mask. */
#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
#define STM32_SAI1SEL_PLLSAI (0 << 20) /**< SAI1 source is PLLSAI. */
@@ -527,38 +311,24 @@ #define STM32_I2S2SEL_AFIN (1 << 27) /**< I2S2 source is AF Input. */
#define STM32_I2S2SEL_MCO1 (2 << 27) /**< I2S2 source is MCO1. */
#define STM32_I2S2SEL_OFF 0xFFFFFFFFU /**< I2S2 clock is not required.*/
-
-#define STM32_DSISEL_MASK (1 << 28) /**< DSISEL mask. */
-#define STM32_DSISEL_PHY (0 << 28) /**< DSI source is DSI-PSY. */
-#define STM32_DSISEL_PLLR (1 << 28) /**< DSI source is PLLR. */
/** @} */
/**
* @name RCC_DCKCFGR2 register bits definitions
* @{
*/
-#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
-#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
-#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
-#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
-
-#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
-#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
-#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
+#define STM32_I2CFMP1SEL_MASK (3 << 22) /**< I2CFMP1SEL mask. */
+#define STM32_I2CFMP1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
+#define STM32_I2CFMP1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
+#define STM32_I2CFMP1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
-#define STM32_CK48MSEL_PLLALT (1 << 27) /**< PLL48CLK source is PLLSAI
- or PLLI2S depending on
- device. */
+#define STM32_CK48MSEL_PLLI2S (1 << 27) /**< PLL48CLK source is PLLI2S. */
-#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
-#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
-#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
-
-#define STM32_SPDIFSEL_MASK (1 << 29) /**< SPDIFSEL mask. */
-#define STM32_SPDIFSEL_PLLI2S (0 << 29) /**< SPDIF source is PLLI2S. */
-#define STM32_SPDIFSEL_PLL (1 << 29) /**< SPDIF source is PLL. */
+#define STM32_SDIOSEL_MASK (1 << 28) /**< SDIOSEL mask. */
+#define STM32_SDIOSEL_PLL48CLK (0 << 28) /**< SDIO source is PLL48CLK. */
+#define STM32_SDIOSEL_SYSCLK (1 << 28) /**< SDIO source is SYSCLK. */
#define STM32_LPTIM1SEL_MASK (3 << 30) /**< LPTIM1 mask. */
#define STM32_LPTIM1SEL_APB (0 << 30) /**< LPTIM1 source is APB. */
@@ -649,7 +419,6 @@ #define STM32_SW STM32_SW_PLL
#endif
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
/**
* @brief Clock source for the PLLs.
* @note This setting has only effect if the PLL is selected as the
@@ -674,141 +443,87 @@ /**
* @brief PLLN multiplier value.
* @note The allowed values are 192..432.
- * @note The default value is calculated for a 168MHz system clock from
+ * @note The default value is calculated for a 96MHz system clock from
* an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE 336
+#define STM32_PLLN_VALUE 384
#endif
/**
* @brief PLLP divider value.
* @note The allowed values are 2, 4, 6, 8.
- * @note The default value is calculated for a 168MHz system clock from
+ * @note The default value is calculated for a 96MHz system clock from
* an external 8MHz HSE clock.
*/
#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLP_VALUE 2
+#define STM32_PLLP_VALUE 4
#endif
/**
* @brief PLLQ multiplier value.
* @note The allowed values are 2..15.
- * @note The default value is calculated for a 168MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE 7
-#endif
-
-/**
- * @brief PLLR divider value.
- * @note The allowed values are 2..7.
* @note The default value is calculated for a 96MHz system clock from
* an external 8MHz HSE clock.
*/
-#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLR_VALUE 4
-#endif
-
-#else /* !defined(STM32F4XX) */
-/**
- * @brief Clock source for the PLLs.
- * @note This setting has only effect if the PLL is selected as the
- * system clock source.
- * @note The default value is calculated for a 120MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief PLLM divider value.
- * @note The allowed values are 2..63.
- * @note The default value is calculated for a 120MHz system clock from
- * an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLM_VALUE 8
+#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLQ_VALUE 8
#endif
/**
- * @brief PLLN multiplier value.
- * @note The allowed values are 192..432.
- * @note The default value is calculated for a 120MHz system clock from
- * an external 8MHz HSE clock.
+ * @brief AHB prescaler value.
*/
-#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLN_VALUE 240
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE STM32_HPRE_DIV1
#endif
/**
- * @brief PLLP divider value.
- * @note The allowed values are 2, 4, 6, 8.
- * @note The default value is calculated for a 120MHz system clock from
- * an external 8MHz HSE clock.
+ * @brief APB1 prescaler value.
*/
-#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLP_VALUE 2
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1 STM32_PPRE1_DIV4
#endif
/**
- * @brief PLLQ multiplier value.
- * @note The allowed values are 2..15.
- * @note The default value is calculated for a 120MHz system clock from
- * an external 8MHz HSE clock.
+ * @brief APB2 prescaler value.
*/
-#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE 5
-#endif
-#endif /* !defined(STM32F4XX) */
-
-/**
- * @brief I2S clock source (post-PLL).
- * @note Not all devices have this setting, it is alternative to
- * @p STM32_PLLI2SSRC.
- */
-#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
-#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2 STM32_PPRE2_DIV2
#endif
/**
* @brief I2S clock source (pre-PLL).
- * @note Not all devices have this setting, it is alternative to
- * @p STM32_I2SSRC.
*/
#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)
-#define STM32_PLLI2SSRC STM32_PLLI2SSRC_CKIN
+#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
#endif
/**
* @brief I2S external clock value, zero if not present.
- * @note Not all devices have this setting.
*/
#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)
#define STM32_I2SCKIN_VALUE 0
#endif
/**
- * @brief PLLI2SN multiplier value.
- * @note The allowed values are 192..432, except for
- * STM32F446 where values are 50...432.
+ * @brief PLLI2SM divider value.
+ * @note The allowed values are 2..63.
* @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
-#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SN_VALUE 192
+#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SM_VALUE 8
#endif
/**
- * @brief PLLI2SM divider value.
- * @note The allowed values are 2..63.
+ * @brief PLLI2SN multiplier value.
+ * @note The allowed values are 192..432, except for
+ * STM32F446 where values are 50...432.
* @note The default value is calculated for a 96MHz I2S clock
* output from an external 8MHz HSE clock.
*/
-#if !defined(STM32_PLLI2SM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SM_VALUE 4
+#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SN_VALUE 192
#endif
/**
@@ -822,14 +537,6 @@ #endif
/**
- * @brief PLLI2SP divider value.
- * @note The allowed values are 2, 4, 6 and 8.
- */
-#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SP_VALUE 4
-#endif
-
-/**
* @brief PLLI2SQ divider value.
* @note The allowed values are 2..15.
*/
@@ -838,80 +545,19 @@ #endif
/**
- * @brief PLLI2SDIVQ divider value (SAI clock divider).
+ * @brief PLLI2SDIVR divider value (SAI clock divider).
* @note The allowed values are 1..32.
*/
-#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLI2SDIVQ_VALUE 1
-#endif
-
-/**
- * @brief PLLSAIM value.
- * @note The allowed values are 2..63.
- * @note The default value is calculated for a 96MHz SAI clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIM_VALUE 4
+#if !defined(STM32_PLLI2SDIVR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLI2SDIVR_VALUE 1
#endif
/**
- * @brief PLLSAIN value.
- * @note The allowed values are 50..432.
- * @note The default value is calculated for a 96MHz SAI clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIN_VALUE 192
-#endif
-
-/**
- * @brief PLLSAIM value.
- * @note The allowed values are 2..63.
- * @note The default value is calculated for a 96MHz SAI clock
- * output from an external 8MHz HSE clock.
- */
-#if !defined(STM32_PLLSAIM_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIM_VALUE 4
-#endif
-
-/**
- * @brief PLLSAIR value.
- * @note The allowed values are 2..7.
- */
-#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIR_VALUE 4
-#endif
-
-/**
- * @brief PLLSAIP divider value.
- * @note The allowed values are 2, 4, 6 and 8.
- */
-#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIP_VALUE 8
-#endif
-
-/**
- * @brief PLLSAIQ value.
- * @note The allowed values are 2..15.
- */
-#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIQ_VALUE 4
-#endif
-
-/**
- * @brief PLLSAIDIVR divider value (SAI clock divider).
- */
-#if !defined(STM32_PLLSAIDIVR) || defined(__DOXYGEN__)
-#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
-#endif
-
-/**
- * @brief PLLSAIDIVQ divider value (LCD clock divider).
+ * @brief PLLDIVR divider value (SAI clock divider).
* @note The allowed values are 1..32.
*/
-#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAIDIVQ_VALUE 1
+#if !defined(STM32_PLLDIVR_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLDIVR_VALUE 1
#endif
/**
@@ -945,27 +591,6 @@ #endif
/**
- * @brief AHB prescaler value.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1 STM32_PPRE1_DIV4
-#endif
-
-/**
- * @brief APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2 STM32_PPRE2_DIV2
-#endif
-
-/**
* @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
@@ -1016,7 +641,6 @@ /* Derived constants and error checks. */
/*===========================================================================*/
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
/*
* Configuration-related checks.
*/
@@ -1024,67 +648,15 @@ #error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
#endif
-#else /* !defined(STM32F4XX) */
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F2xx_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F2xx_MCUCONF not defined"
+#if defined(STM32F413xx) && !defined(STM32F413_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F413_MCUCONF not defined"
#endif
-#endif /* !defined(STM32F4XX) */
/**
- * @brief Maximum frequency thresholds and wait states for flash access.
- * @note The values are valid for 2.7V to 3.6V supply range.
+ * @name Maximum frequency thresholds and wait states for flash access.
+ * @{
*/
-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
- defined(STM32F40_41xxx) || defined(STM32F446xx) || \
- defined(STM32F469_479xx) || defined(__DOXYGEN__)
-#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
-#define STM32_0WS_THRESHOLD 30000000
-#define STM32_1WS_THRESHOLD 60000000
-#define STM32_2WS_THRESHOLD 90000000
-#define STM32_3WS_THRESHOLD 120000000
-#define STM32_4WS_THRESHOLD 150000000
-#define STM32_5WS_THRESHOLD 180000000
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 24000000
-#define STM32_1WS_THRESHOLD 48000000
-#define STM32_2WS_THRESHOLD 72000000
-#define STM32_3WS_THRESHOLD 96000000
-#define STM32_4WS_THRESHOLD 120000000
-#define STM32_5WS_THRESHOLD 144000000
-#define STM32_6WS_THRESHOLD 168000000
-#define STM32_7WS_THRESHOLD 180000000
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 22000000
-#define STM32_1WS_THRESHOLD 44000000
-#define STM32_2WS_THRESHOLD 66000000
-#define STM32_3WS_THRESHOLD 88000000
-#define STM32_4WS_THRESHOLD 110000000
-#define STM32_5WS_THRESHOLD 132000000
-#define STM32_6WS_THRESHOLD 154000000
-#define STM32_7WS_THRESHOLD 176000000
-#define STM32_8WS_THRESHOLD 180000000
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 20000000
-#define STM32_1WS_THRESHOLD 40000000
-#define STM32_2WS_THRESHOLD 60000000
-#define STM32_3WS_THRESHOLD 80000000
-#define STM32_4WS_THRESHOLD 100000000
-#define STM32_5WS_THRESHOLD 120000000
-#define STM32_6WS_THRESHOLD 140000000
-#define STM32_7WS_THRESHOLD 168000000
-#define STM32_8WS_THRESHOLD 0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-#elif defined(STM32F413xx)
+#if defined(STM32F413xx)
#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
#define STM32_0WS_THRESHOLD 25000000
#define STM32_1WS_THRESHOLD 50000000
@@ -1128,184 +700,8 @@ #else
#error "invalid VDD voltage specified"
#endif
-
-#elif defined(STM32F412xx)
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD 30000000
-#define STM32_1WS_THRESHOLD 64000000
-#define STM32_2WS_THRESHOLD 90000000
-#define STM32_3WS_THRESHOLD 100000000
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 24000000
-#define STM32_1WS_THRESHOLD 48000000
-#define STM32_2WS_THRESHOLD 72000000
-#define STM32_3WS_THRESHOLD 96000000
-#define STM32_4WS_THRESHOLD 100000000
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 18000000
-#define STM32_1WS_THRESHOLD 36000000
-#define STM32_2WS_THRESHOLD 54000000
-#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 90000000
-#define STM32_5WS_THRESHOLD 100000000
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 170) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 16000000
-#define STM32_1WS_THRESHOLD 32000000
-#define STM32_2WS_THRESHOLD 48000000
-#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 80000000
-#define STM32_5WS_THRESHOLD 96000000
-#define STM32_6WS_THRESHOLD 100000000
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-#elif defined(STM32F410xx) || defined(STM32F411xx)
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD 30000000
-#define STM32_1WS_THRESHOLD 64000000
-#define STM32_2WS_THRESHOLD 90000000
-#define STM32_3WS_THRESHOLD 100000000
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 24000000
-#define STM32_1WS_THRESHOLD 48000000
-#define STM32_2WS_THRESHOLD 72000000
-#define STM32_3WS_THRESHOLD 96000000
-#define STM32_4WS_THRESHOLD 100000000
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 18000000
-#define STM32_1WS_THRESHOLD 36000000
-#define STM32_2WS_THRESHOLD 54000000
-#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 90000000
-#define STM32_5WS_THRESHOLD 100000000
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 171) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 16000000
-#define STM32_1WS_THRESHOLD 32000000
-#define STM32_2WS_THRESHOLD 48000000
-#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 80000000
-#define STM32_5WS_THRESHOLD 96000000
-#define STM32_6WS_THRESHOLD 100000000
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-
-#elif defined(STM32F401xx)
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD 30000000
-#define STM32_1WS_THRESHOLD 60000000
-#define STM32_2WS_THRESHOLD 84000000
-#define STM32_3WS_THRESHOLD 0
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 24000000
-#define STM32_1WS_THRESHOLD 48000000
-#define STM32_2WS_THRESHOLD 72000000
-#define STM32_3WS_THRESHOLD 84000000
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 18000000
-#define STM32_1WS_THRESHOLD 36000000
-#define STM32_2WS_THRESHOLD 54000000
-#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 84000000
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 16000000
-#define STM32_1WS_THRESHOLD 32000000
-#define STM32_2WS_THRESHOLD 48000000
-#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 80000000
-#define STM32_5WS_THRESHOLD 84000000
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#define STM32_8WS_THRESHOLD 0
-#else
-#error "invalid VDD voltage specified"
-#endif
-
-#else /* STM32F2XX */
-#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
-#define STM32_0WS_THRESHOLD 30000000
-#define STM32_1WS_THRESHOLD 60000000
-#define STM32_2WS_THRESHOLD 90000000
-#define STM32_3WS_THRESHOLD 120000000
-#define STM32_4WS_THRESHOLD 0
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
-#define STM32_0WS_THRESHOLD 24000000
-#define STM32_1WS_THRESHOLD 48000000
-#define STM32_2WS_THRESHOLD 72000000
-#define STM32_3WS_THRESHOLD 96000000
-#define STM32_4WS_THRESHOLD 120000000
-#define STM32_5WS_THRESHOLD 0
-#define STM32_6WS_THRESHOLD 0
-#define STM32_7WS_THRESHOLD 0
-#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
-#define STM32_0WS_THRESHOLD 18000000
-#define STM32_1WS_THRESHOLD 36000000
-#define STM32_2WS_THRESHOLD 54000000
-#define STM32_3WS_THRESHOLD 72000000
-#define STM32_4WS_THRESHOLD 90000000
-#define STM32_5WS_THRESHOLD 108000000
-#define STM32_6WS_THRESHOLD 120000000
-#define STM32_7WS_THRESHOLD 0
-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
-#define STM32_0WS_THRESHOLD 16000000
-#define STM32_1WS_THRESHOLD 32000000
-#define STM32_2WS_THRESHOLD 48000000
-#define STM32_3WS_THRESHOLD 64000000
-#define STM32_4WS_THRESHOLD 80000000
-#define STM32_5WS_THRESHOLD 96000000
-#define STM32_6WS_THRESHOLD 112000000
-#define STM32_7WS_THRESHOLD 120000000
-#else
-#error "invalid VDD voltage specified"
-#endif
-#endif /* STM32F2XX */
+#endif /* defined(STM32F413xx) */
+/** @} */
/*
* HSI related checks.
@@ -1331,7 +727,7 @@ #error "HSI not enabled, required by STM32_MCO2SEL"
#endif
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLI2S) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_I2SSRC"
#endif
@@ -1389,9 +785,9 @@ #error "HSE not enabled, required by STM32_MCO2SEL"
#endif
-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \
+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_I2SSRC"
+#error "HSE not enabled, required by STM32_PLLI2SSRC"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
@@ -1520,13 +916,13 @@ #endif
/**
- * @brief STM32_PLLR field.
+ * @brief STM32_PLLDIVR_VALUE field.
*/
-#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 7)) || \
+#if ((STM32_PLLDIVR_VALUE >= 1) && (STM32_PLLDIVR_VALUE <= 32)) || \
defined(__DOXYGEN__)
-#define STM32_PLLR (STM32_PLLR_VALUE << 28)
+#define STM32_PLLDIVR ((STM32_PLLDIVR_VALUE - 1) << 8)
#else
-#error "invalid STM32_PLLR_VALUE value specified"
+#error "invalid STM32_PLLDIVR_VALUE value specified"
#endif
/**
@@ -1574,41 +970,7 @@ #endif
/* Calculating VOS settings, it is different for each sub-platform.*/
-#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
- defined(STM32F446xx) || defined(STM32F469_479xx) || \
- defined(__DOXYGEN__)
-#if STM32_SYSCLK <= 120000000
-#define STM32_VOS STM32_VOS_SCALE3
-#define STM32_OVERDRIVE_REQUIRED FALSE
-#elif STM32_SYSCLK <= 144000000
-#define STM32_VOS STM32_VOS_SCALE2
-#define STM32_OVERDRIVE_REQUIRED FALSE
-#elif STM32_SYSCLK <= 168000000
-#define STM32_VOS STM32_VOS_SCALE1
-#define STM32_OVERDRIVE_REQUIRED FALSE
-#else
-#define STM32_VOS STM32_VOS_SCALE1
-#define STM32_OVERDRIVE_REQUIRED TRUE
-#endif
-
-#elif defined(STM32F40_41xxx)
-#if STM32_SYSCLK <= 144000000
-#define STM32_VOS STM32_VOS_SCALE2
-#else
-#define STM32_VOS STM32_VOS_SCALE1
-#endif
-#define STM32_OVERDRIVE_REQUIRED FALSE
-
-#elif defined(STM32F401xx)
-#if STM32_SYSCLK <= 60000000
-#define STM32_VOS STM32_VOS_SCALE3
-#else
-#define STM32_VOS STM32_VOS_SCALE2
-#endif
-#define STM32_OVERDRIVE_REQUIRED FALSE
-
-#elif defined(STM32F410xx) || defined(STM32F411xx) || \
- defined(STM32F412xx) || defined(STM32F413xx)
+#if defined(STM32F413xx)
#if STM32_SYSCLK <= 64000000
#define STM32_VOS STM32_VOS_SCALE3
#elif STM32_SYSCLK <= 84000000
@@ -1617,9 +979,6 @@ #define STM32_VOS STM32_VOS_SCALE1
#endif
#define STM32_OVERDRIVE_REQUIRED FALSE
-
-#else /* STM32F2XX */
-#define STM32_OVERDRIVE_REQUIRED FALSE
#endif
/**
@@ -1709,8 +1068,7 @@ (STM32_CLOCK48_REQUIRED && \
(STM32_HAS_RCC_CK48MSEL && \
STM32_RCC_CK48MSEL_USES_I2S && \
- (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
- (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
+ (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S)) || \
(STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) || \
(STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) || \
defined(__DOXYGEN__)
@@ -1744,21 +1102,6 @@ #endif
/**
- * @brief STM32_PLLI2SP field.
- */
-#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLI2SP STM32_PLLI2SP_DIV2
-#elif STM32_PLLI2SP_VALUE == 4
-#define STM32_PLLI2SP STM32_PLLI2SP_DIV4
-#elif STM32_PLLI2SP_VALUE == 6
-#define STM32_PLLI2SP STM32_PLLI2SP_DIV6
-#elif STM32_PLLI2SP_VALUE == 8
-#define STM32_PLLI2SP STM32_PLLI2SP_DIV8
-#else
-#error "invalid STM32_PLLI2SP_VALUE value specified"
-#endif
-
-/**
* @brief STM32_PLLI2SQ field.
*/
#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \
@@ -1769,23 +1112,23 @@ #endif
/**
- * @brief STM32_PLLI2SDIVQ field.
+ * @brief STM32_PLLI2SR field.
*/
-#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) || \
+#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
defined(__DOXYGEN__)
-#define STM32_PLLI2SDIVQ ((STM32_PLLI2SQ_VALUE - 1) << 0)
+#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
#else
-#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
+#error "invalid STM32_PLLI2SR_VALUE value specified"
#endif
/**
- * @brief STM32_PLLI2SR field.
+ * @brief STM32_PLLI2SDIVR field.
*/
-#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
+#if ((STM32_PLLI2SDIVR_VALUE >= 1) && (STM32_PLLI2SDIVR_VALUE <= 32)) || \
defined(__DOXYGEN__)
-#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
+#define STM32_PLLI2SDIVR ((STM32_PLLI2SR_VALUE - 1) << 0)
#else
-#error "invalid STM32_PLLI2SR_VALUE value specified"
+#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"
#endif
/**
@@ -1794,7 +1137,7 @@ #if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)
#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLI2SCLKIN (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)
-#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN
+#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_CKIN
#define STM32_PLLI2SCLKIN (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)
#else
#error "invalid STM32_PLLI2SSRC value specified"
@@ -1817,11 +1160,6 @@ #endif
/**
- * @brief PLLI2S P output clock frequency.
- */
-#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE)
-
-/**
* @brief PLLI2S Q output clock frequency.
*/
#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE)
@@ -1831,145 +1169,11 @@ */
#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE)
-/*
- * PLLSAI enable check.
- */
-#if (STM32_HAS_RCC_PLLSAI && \
- (STM32_CLOCK48_REQUIRED && \
- (STM32_HAS_RCC_CK48MSEL && \
- !STM32_RCC_CK48MSEL_USES_I2S && \
- (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) || \
- (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \
- (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) || \
- (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) || \
- (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) || \
- defined(__DOXYGEN__)
/**
* @brief PLLSAI activation flag.
+ * @note Always FALSE, there is no PLLSAI.
*/
-#define STM32_ACTIVATE_PLLSAI TRUE
-#else
#define STM32_ACTIVATE_PLLSAI FALSE
-#endif
-
-/**
- * @brief STM32_PLLSAIM field.
- */
-#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLSAIM (STM32_PLLSAIM_VALUE << 0)
-#else
-#error "invalid STM32_PLLSAIM_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLSAIN field.
- */
-#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6)
-#else
-#error "invalid STM32_PLLSAIN_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLSAIQ field.
- */
-#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24)
-#else
-#error "invalid STM32_PLLSAIQ_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLSAIDIVQ_VALUE field.
- */
-#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)
-#else
-#error "invalid STM32_PLLSAIDIVQ_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLSAIR field.
- */
-#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \
- defined(__DOXYGEN__)
-#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28)
-#else
-#error "invalid STM32_PLLSAIR_VALUE value specified"
-#endif
-
-/**
- * @brief STM32_PLLSAIP field.
- */
-
-#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__)
-#define STM32_PLLSAIP STM32_PLLSAIP_DIV2
-
-#elif STM32_PLLSAIP_VALUE == 4
-#define STM32_PLLSAIP STM32_PLLSAIP_DIV4
-
-#elif STM32_PLLSAIP_VALUE == 6
-#define STM32_PLLSAIP STM32_PLLSAIP_DIV6
-
-#elif STM32_PLLSAIP_VALUE == 8
-#define STM32_PLLSAIP STM32_PLLSAIP_DIV8
-
-#else
-#error "invalid STM32_PLLSAIP_VALUE value specified"
-#endif
-
-/**
- * @brief PLLSAI input clock frequency.
- */
-#if defined(STM32F446xx)
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLSAIM_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLSAIM_VALUE)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-#else /* !defined(STM32F446xx) */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLSAICLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLSAICLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-#endif /* defined(STM32F446xx) */
-
-/**
- * @brief PLLSAI VCO frequency.
- */
-#define STM32_PLLSAIVCO (STM32_PLLSAICLKIN * STM32_PLLSAIN_VALUE)
-
-/*
- * PLLSAI VCO frequency range check.
- */
-#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \
- (STM32_PLLSAIVCO > STM32_PLLVCO_MAX)
-#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
-#endif
-
-/**
- * @brief PLLSAI P output clock frequency.
- */
-#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)
-
-/**
- * @brief PLLSAI Q output clock frequency.
- */
-#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE)
-
-/**
- * @brief PLLSAI R output clock frequency.
- */
-#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
/**
* @brief MCO1 divider clock.
@@ -2099,7 +1303,7 @@ #if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
+#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S
#if STM32_RCC_CK48MSEL_USES_I2S
#define STM32_PLL48CLK STM32_PLLI2S_Q_CLKOUT
#else
@@ -2244,6 +1448,6 @@ extern "C" { }
#endif
-#endif /* HAL_LLD_H */
+#endif /* HAL_LLD_TYPE2_H */
/** @} */
|