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author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-02 14:52:05 +0000 |
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committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-02 14:52:05 +0000 |
commit | 814f557d2f39ff5655556d036a36076f36bc121d (patch) | |
tree | 38a860ad26445f8db97eefd47c3896670e66bba1 /os/hal/ports/STM32/STM32F4xx | |
parent | 4d7be5bf04f6784d92e3f9a9e389cd4dde3e237f (diff) | |
download | ChibiOS-814f557d2f39ff5655556d036a36076f36bc121d.tar.gz ChibiOS-814f557d2f39ff5655556d036a36076f36bc121d.tar.bz2 ChibiOS-814f557d2f39ff5655556d036a36076f36bc121d.zip |
Registry updated for STM32F7xx.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8145 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx')
-rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 9e34b7ce3..54471483d 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -122,6 +122,8 @@ #define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | \
@@ -154,6 +156,8 @@ #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C3_TX_DMA_CHN 0x00030000
+#define STM32_HAS_I2C4 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -321,6 +325,9 @@ STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART6_TX_DMA_CHN 0x55000000
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
@@ -420,6 +427,8 @@ #define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOI TRUE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | \
@@ -452,6 +461,8 @@ #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C3_TX_DMA_CHN 0x00030000
+#define STM32_HAS_I2C4 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#if !defined(STM32F2XX)
@@ -605,6 +616,9 @@ STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART6_TX_DMA_CHN 0x55000000
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
@@ -693,6 +707,8 @@ #define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | \
@@ -721,6 +737,8 @@ #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C3_TX_DMA_CHN 0x00030000
+#define STM32_HAS_I2C4 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -844,6 +862,9 @@ STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART6_TX_DMA_CHN 0x55000000
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
@@ -914,6 +935,8 @@ #define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | \
@@ -943,6 +966,8 @@ #define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C3_TX_DMA_CHN 0x00030000
+#define STM32_HAS_I2C4 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -1073,6 +1098,9 @@ STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART6_TX_DMA_CHN 0x55000000
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 TRUE
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