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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-07 08:34:43 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-07 08:34:43 +0000 |
| commit | b058a251b800ac85c10019c6123a629bc942eaaf (patch) | |
| tree | d57ee358f687268980b4bba4f51f48234001cc22 /os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | |
| parent | 0c9f553e4fed400108f90f1504e88d1882c097e6 (diff) | |
| download | ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.tar.gz ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.tar.bz2 ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.zip | |
Added support for STM32F413, added ability to handle the TIMPRE bit in the RCC_CFGR register.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12011 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index e22cf27ab..e55caf2f6 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -605,6 +605,30 @@ /** @} */
/**
+ * @brief Enables the I2C4 peripheral clock.
+ *
+ * @api
+ */
+#define rccEnableI2C4() rccEnableAPB1(RCC_APB1ENR_FMPI2C1EN, lp)
+
+/**
+ * @brief Disables the I2C4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_FMPI2C1EN, lp)
+
+/**
+ * @brief Resets the I2C4 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_FMPI2C1RST)
+/** @} */
+
+/**
* @name OTG peripherals specific RCC operations
* @{
*/
@@ -1198,6 +1222,31 @@ /** @} */
/**
+ * @brief Enables the LPTIM1 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPTIM1(lp) rccEnableAPB1(RCC_APB1ENR_LPTIM1EN, lp)
+
+/**
+ * @brief Disables the LPTIM1 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableLPTIM1() rccDisableAPB1(RCC_APB1ENR_LPTIM1EN, lp)
+
+/**
+ * @brief Resets the LPTIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPTIM1() rccResetAPB1(RCC_APB1RSTR_LPTIM1RST)
+/** @} */
+
+/**
* @name USART/UART peripherals specific RCC operations
* @{
*/
@@ -1387,6 +1436,56 @@ /** @} */
/**
+ * @brief Enables the UART9 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART9(lp) rccEnableAPB2(RCC_APB2ENR_UART9EN, lp)
+
+/**
+ * @brief Disables the UART9 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART9() rccDisableAPB2(RCC_APB2ENR_UART9EN, lp)
+
+/**
+ * @brief Resets the UART9 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART9() rccResetAPB2(RCC_APB2RSTR_UART9RST)
+/** @} */
+
+/**
+ * @brief Enables the UART10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART10(lp) rccEnableAPB2(RCC_APB2ENR_UART10EN, lp)
+
+/**
+ * @brief Disables the UART10 peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableUART10(lp) rccDisableAPB2(RCC_APB2ENR_UART10EN, lp)
+
+/**
+ * @brief Resets the UART10 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART10() rccResetAPB2(RCC_APB2RSTR_UART10RST)
+/** @} */
+
+/**
* @name LTDC peripheral specific RCC operations
* @{
*/
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