Added support for STM32F413, added ability to handle the TIMPRE bit in the RCC_CFGR register.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12011 110e8d01-0319-4d1e-a829-52ad28d1bb01

6 files changed, 735 insertions, 29 deletions

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index d74ddbf0e..2948c78ae 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -234,9 +234,15 @@ void stm32_clock_init(void) {
 #endif /* STM32_ACTIVATE_PLL */

 

 #if STM32_ACTIVATE_PLLI2S

+#if defined(STM32F413xx)

+  /* PLLI2S activation.*/

+  RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |

+                    STM32_I2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;

+#else

   /* PLLI2S activation.*/

   RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |

                     STM32_PLLI2SQ | STM32_PLLI2SM;

+#endif

   RCC->CR |= RCC_CR_PLLI2SON;

 

   /* Waiting for PLL lock.*/

@@ -255,10 +261,17 @@ void stm32_clock_init(void) {
     ;

 #endif /* STM32_ACTIVATE_PLLSAI */

 

+#if defined(STM32F413xx)

+  /* Other clock-related settings (dividers, MCO etc).*/

+  RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

+              STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |

+              STM32_HPRE;

+#else

   /* Other clock-related settings (dividers, MCO etc).*/

   RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

               STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |

               STM32_HPRE;

+#endif

 

 #if defined(STM32F446xx)

   /* DCKCFGR register initialization, note, must take care of the _OFF

@@ -274,6 +287,9 @@ void stm32_clock_init(void) {
 #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF

     dckcfgr |= STM32_PLLSAIDIVR;

 #endif

+#if STM32_TIMPRE == STM32_TIMPRE_HCLK

+    dckcfgr |= STM32_TIMPRE_HCLK;

+#endif

     RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;

   }

   RCC->DCKCFGR2 = STM32_CK48MSEL;

@@ -282,18 +298,37 @@ void stm32_clock_init(void) {
    pseudo settings.*/

   {

     uint32_t dckcfgr = 0;

-  #if STM32_SAI2SEL != STM32_SAI2SEL_OFF

+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF

     dckcfgr |= STM32_SAI2SEL;

-  #endif

-  #if STM32_SAI1SEL != STM32_SAI1SEL_OFF

+#endif

+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF

     dckcfgr |= STM32_SAI1SEL;

-  #endif

-  #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF

+#endif

+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF

     dckcfgr |= STM32_PLLSAIDIVR;

-  #endif

+#endif

     RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | 

                    STM32_CK48MSEL;

   }

+#elif defined(STM32F413xx)

+  /* DCKCFGR register initialization. */

+  {

+    uint32_t dckcfgr = 0;

+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF

+    dckcfgr |= STM32_SAI2SEL;

+#endif

+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF

+    dckcfgr |= STM32_SAI1SEL;

+#endif

+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF

+    dckcfgr |= STM32_PLLSAIDIVR;

+#endif

+#if STM32_TIMPRE == STM32_TIMPRE_HCLK

+    dckcfgr |= STM32_TIMPRE_HCLK;

+#endif

+    RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;

+  }

+  RCC->DCKCFGR2 = STM32_CK48MSEL;

 #endif

 

   /* Flash setup.*/

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 6125c9a31..de5aaa5cb 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -88,6 +88,9 @@
 #elif defined(STM32F412xx)

 #define PLATFORM_NAME           "STM32F412 High Performance with DSP and FPU"

 

+#elif defined(STM32F413xx)

+#define PLATFORM_NAME           "STM32F413 High Performance with DSP and FPU"

+

 #elif defined(STM32F415xx)

 #define PLATFORM_NAME           "STM32F415 High Performance with DSP and FPU"

 

@@ -264,7 +267,7 @@
 #endif

 

 #if defined(STM32F410xx) || defined(STM32F411xx) ||                         \

-    defined(STM32F412xx)

+    defined(STM32F412xx) || defined(STM32F413xx)

 #define STM32_SYSCLK_MAX        100000000

 #define STM32_HSECLK_MAX        26000000

 #define STM32_HSECLK_BYP_MAX    50000000

@@ -446,6 +449,11 @@
 #define STM32_PLLI2SP_DIV8      (3 << 16)   /**< PLLI2S clock divided by 8. */

 #define STM32_PLLI2SQ_MASK      (15 << 24)  /**< PLLI2SQ mask.              */

 #define STM32_PLLI2SR_MASK      (7 << 28)   /**< PLLI2SR mask.              */

+#if defined(STM32F413xx)

+#define STM32_PLLI2SSRC_MASK    (1 << 22)   /**< PLLI2SSRC mask.            */

+#define STM32_PLLI2SSRC_CKIN    (0 << 22)   /**< PLLI2SSRC is CK_IN.        */

+#define STM32_PLLI2SSRC_I2SCKIN (1 << 22)   /**< PLLI2SSRC is I2S_CKIN.     */

+#endif

 /** @} */

 

 /**

@@ -531,6 +539,20 @@
 #define STM32_I2C1SEL_SYSCLK    (1 << 22)   /**< I2C1 source is SYSCLK.     */

 #define STM32_I2C1SEL_HSI       (2 << 22)   /**< I2C1 source is HSI.        */

 

+#if defined(STM32F413xx)

+/* TODO: Chibios definition could be set from CMSIS stm32f413xx.h.          */

+#define STM32_I2CFMP1SEL_MASK   (3 << 22)   /**< I2C1SEL mask.              */

+#define STM32_I2CFMP1SEL_APB    (0 << 22)   /**< I2C1 source is APB.        */

+#define STM32_I2CFMP1SEL_SYSCLK (1 << 22)   /**< I2C1 source is SYSCLK.     */

+#define STM32_I2CFMP1SEL_HSI    (2 << 22)   /**< I2C1 source is HSI.        */

+

+#define STM32_LPTIM1SEL_MASK    (3 << 30)   /**< LPTIM1 mask.               */

+#define STM32_LPTIM1SEL_APB     (0 << 30)   /**< LPTIM1 source is APB.      */

+#define STM32_LPTIM1SEL_HSI     (1 << 30)   /**< LPTIM1 source is HSI.      */

+#define STM32_LPTIM1SEL_LSI     (2 << 30)   /**< LPTIM1 source is LSI.      */

+#define STM32_LPTIM1SEL_LSE     (3 << 30)   /**< LPTIM1 source is LSE.      */

+#endif

+

 #define STM32_CECSEL_MASK       (1 << 26)   /**< CECSEL mask.               */

 #define STM32_CECSEL_LSE        (0 << 26)   /**< CEC source is LSE.         */

 #define STM32_CECSEL_HSIDIV488  (1 << 26)   /**< CEC source is HSI/488.     */

@@ -538,6 +560,9 @@
 #define STM32_CK48MSEL_MASK     (1 << 27)   /**< CK48MSEL mask.             */

 #define STM32_CK48MSEL_PLL      (0 << 27)   /**< PLL48CLK source is PLL.    */

 #define STM32_CK48MSEL_PLLSAI   (1 << 27)   /**< PLL48CLK source is PLLSAI. */

+#if defined(STM32F413xx)

+#define STM32_CK48MSEL_PLLI2S   (1 << 27)   /**< PLL48CLK source is PLLI2S. */

+#endif

 

 #define STM32_SDMMCSEL_MASK     (1 << 28)   /**< SDMMCSEL mask.             */

 #define STM32_SDMMCSEL_PLL48CLK (0 << 28)   /**< SDMMC source is PLL48CLK.  */

@@ -682,6 +707,16 @@
 #define STM32_PLLQ_VALUE            7

 #endif

 

+/**

+ * @brief   PLLR divider value.

+ * @note    The allowed values are 2..7.

+ * @note    The default value is calculated for a 96MHz system clock from

+ *          an external 8MHz HSE clock.

+ */

+#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLR_VALUE             4

+#endif

+

 #else /* !defined(STM32F4XX) */

 /**

  * @brief   Clock source for the PLLs.

@@ -1025,12 +1060,57 @@
 #error "invalid VDD voltage specified"

 #endif

 

-#elif defined(STM32F401xx)

+#elif defined(STM32F413xx)

+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

+#define STM32_0WS_THRESHOLD         25000000

+#define STM32_1WS_THRESHOLD         50000000

+#define STM32_2WS_THRESHOLD         75000000

+#define STM32_3WS_THRESHOLD         100000000

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

+#define STM32_0WS_THRESHOLD         20000000

+#define STM32_1WS_THRESHOLD         40000000

+#define STM32_2WS_THRESHOLD         60000000

+#define STM32_3WS_THRESHOLD         80000000

+#define STM32_4WS_THRESHOLD         100000000

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

+#define STM32_0WS_THRESHOLD         18000000

+#define STM32_1WS_THRESHOLD         36000000

+#define STM32_2WS_THRESHOLD         54000000

+#define STM32_3WS_THRESHOLD         72000000

+#define STM32_4WS_THRESHOLD         90000000

+#define STM32_5WS_THRESHOLD         100000000

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 170) && (STM32_VDD < 210)

+#define STM32_0WS_THRESHOLD         16000000

+#define STM32_1WS_THRESHOLD         32000000

+#define STM32_2WS_THRESHOLD         48000000

+#define STM32_3WS_THRESHOLD         64000000

+#define STM32_4WS_THRESHOLD         80000000

+#define STM32_5WS_THRESHOLD         96000000

+#define STM32_6WS_THRESHOLD         100000000

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#else

+#error "invalid VDD voltage specified"

+#endif

+

+#elif defined(STM32F412xx)

 #if (STM32_VDD >= 270) && (STM32_VDD <= 360)

 #define STM32_0WS_THRESHOLD         30000000

-#define STM32_1WS_THRESHOLD         60000000

-#define STM32_2WS_THRESHOLD         84000000

-#define STM32_3WS_THRESHOLD         0

+#define STM32_1WS_THRESHOLD         64000000

+#define STM32_2WS_THRESHOLD         90000000

+#define STM32_3WS_THRESHOLD         100000000

 #define STM32_4WS_THRESHOLD         0

 #define STM32_5WS_THRESHOLD         0

 #define STM32_6WS_THRESHOLD         0

@@ -1040,8 +1120,8 @@
 #define STM32_0WS_THRESHOLD         24000000

 #define STM32_1WS_THRESHOLD         48000000

 #define STM32_2WS_THRESHOLD         72000000

-#define STM32_3WS_THRESHOLD         84000000

-#define STM32_4WS_THRESHOLD         0

+#define STM32_3WS_THRESHOLD         96000000

+#define STM32_4WS_THRESHOLD         100000000

 #define STM32_5WS_THRESHOLD         0

 #define STM32_6WS_THRESHOLD         0

 #define STM32_7WS_THRESHOLD         0

@@ -1051,19 +1131,19 @@
 #define STM32_1WS_THRESHOLD         36000000

 #define STM32_2WS_THRESHOLD         54000000

 #define STM32_3WS_THRESHOLD         72000000

-#define STM32_4WS_THRESHOLD         84000000

-#define STM32_5WS_THRESHOLD         0

+#define STM32_4WS_THRESHOLD         90000000

+#define STM32_5WS_THRESHOLD         100000000

 #define STM32_6WS_THRESHOLD         0

 #define STM32_7WS_THRESHOLD         0

 #define STM32_8WS_THRESHOLD         0

-#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

+#elif (STM32_VDD >= 170) && (STM32_VDD < 210)

 #define STM32_0WS_THRESHOLD         16000000

 #define STM32_1WS_THRESHOLD         32000000

 #define STM32_2WS_THRESHOLD         48000000

 #define STM32_3WS_THRESHOLD         64000000

 #define STM32_4WS_THRESHOLD         80000000

-#define STM32_5WS_THRESHOLD         84000000

-#define STM32_6WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         96000000

+#define STM32_6WS_THRESHOLD         100000000

 #define STM32_7WS_THRESHOLD         0

 #define STM32_8WS_THRESHOLD         0

 #else

@@ -1115,6 +1195,52 @@
 #error "invalid VDD voltage specified"

 #endif

 

+

+#elif defined(STM32F401xx)

+#if (STM32_VDD >= 270) && (STM32_VDD <= 360)

+#define STM32_0WS_THRESHOLD         30000000

+#define STM32_1WS_THRESHOLD         60000000

+#define STM32_2WS_THRESHOLD         84000000

+#define STM32_3WS_THRESHOLD         0

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 240) && (STM32_VDD < 270)

+#define STM32_0WS_THRESHOLD         24000000

+#define STM32_1WS_THRESHOLD         48000000

+#define STM32_2WS_THRESHOLD         72000000

+#define STM32_3WS_THRESHOLD         84000000

+#define STM32_4WS_THRESHOLD         0

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 210) && (STM32_VDD < 240)

+#define STM32_0WS_THRESHOLD         18000000

+#define STM32_1WS_THRESHOLD         36000000

+#define STM32_2WS_THRESHOLD         54000000

+#define STM32_3WS_THRESHOLD         72000000

+#define STM32_4WS_THRESHOLD         84000000

+#define STM32_5WS_THRESHOLD         0

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#elif (STM32_VDD >= 180) && (STM32_VDD < 210)

+#define STM32_0WS_THRESHOLD         16000000

+#define STM32_1WS_THRESHOLD         32000000

+#define STM32_2WS_THRESHOLD         48000000

+#define STM32_3WS_THRESHOLD         64000000

+#define STM32_4WS_THRESHOLD         80000000

+#define STM32_5WS_THRESHOLD         84000000

+#define STM32_6WS_THRESHOLD         0

+#define STM32_7WS_THRESHOLD         0

+#define STM32_8WS_THRESHOLD         0

+#else

+#error "invalid VDD voltage specified"

+#endif

+

 #else /* STM32F2XX */

 #if (STM32_VDD >= 270) && (STM32_VDD <= 360)

 #define STM32_0WS_THRESHOLD         30000000

@@ -1363,6 +1489,16 @@
 #endif

 

 /**

+ * @brief   STM32_PLLR field.

+ */

+#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 7)) ||                 \

+    defined(__DOXYGEN__)

+#define STM32_PLLR                  (STM32_PLLR_VALUE << 28)

+#else

+#error "invalid STM32_PLLR_VALUE value specified"

+#endif

+

+/**

  * @brief   PLL VCO frequency.

  */

 #define STM32_PLLVCO                (STM32_PLLCLKIN * STM32_PLLN_VALUE)

@@ -1440,7 +1576,8 @@
 #endif

 #define STM32_OVERDRIVE_REQUIRED    FALSE

 

-#elif defined(STM32F410xx) || defined(STM32F411xx) || defined(STM32F412xx)

+#elif defined(STM32F410xx) || defined(STM32F411xx) ||                      \

+      defined(STM32F412xx) || defined(STM32F413xx)

 #if STM32_SYSCLK <= 64000000

 #define STM32_VOS                   STM32_VOS_SCALE3

 #elif STM32_SYSCLK <= 84000000

@@ -1537,10 +1674,13 @@
 /*

  * PLLI2S enable check.

  */

-#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                                \

+#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S)    \

+    && defined(STM32F413xx)) ||                                             \

+    (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                                \

     (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) ||                              \

     (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S) ||                              \

     defined(__DOXYGEN__)

+

 /**

  * @brief   PLLI2S activation flag.

  */

@@ -1562,21 +1702,21 @@
 /**

  * @brief   STM32_PLLI2SN field.

  */

-#if defined (STM32F446xx) || defined(__DOXYGEN__)

+#if defined(STM32F446xx) || defined(STM32F413xx) || defined(__DOXYGEN__)

 #if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) ||       \

     defined(__DOXYGEN__)

 #define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)

 #else

 #error "invalid STM32_PLLI2SN_VALUE value specified"

 #endif

-#else  /* !defined(STM32F446xx) */

+#else  /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 #if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) ||       \

     defined(__DOXYGEN__)

 #define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)

 #else

 #error "invalid STM32_PLLI2SN_VALUE value specified"

 #endif

-#endif  /* defined(STM32F446xx) */

+#endif  /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 

 /**

  * @brief   STM32_PLLI2SP field.

@@ -1616,7 +1756,7 @@
 /**

  * @brief   PLLI2S input clock frequency.

  */

-#if defined(STM32F446xx)

+#if defined(STM32F446xx) || defined(STM32F413xx)

 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

 #define STM32_PLLI2SCLKIN           (STM32_HSECLK / STM32_PLLI2SM_VALUE)

 #elif STM32_PLLSRC == STM32_PLLSRC_HSI

@@ -1624,7 +1764,7 @@
 #else

 #error "invalid STM32_PLLSRC value specified"

 #endif

-#else /* !defined(STM32F446xx) */

+#else /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

 #define STM32_PLLI2SCLKIN           (STM32_HSECLK / STM32_PLLM_VALUE)

 #elif STM32_PLLSRC == STM32_PLLSRC_HSI

@@ -1632,7 +1772,7 @@
 #else

 #error "invalid STM32_PLLSRC value specified"

 #endif

-#endif /* defined(STM32F446xx) */

+#endif /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 

 /**

  * @brief   PLLI2S VCO frequency.

@@ -1665,7 +1805,8 @@
 /*

  * PLLSAI enable check.

  */

-#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \

+#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)    \

+    && defined(STM32F446xx)) ||                                             \

     (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) ||                           \

     (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) ||                              \

     (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI) ||                              \

@@ -1914,14 +2055,60 @@
 #if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)

 #if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)

 #define STM32_PLL48CLK              (STM32_PLLVCO / STM32_PLLQ_VALUE)

-#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI

+#elif (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI) && defined(STM32F446xx)

 #define STM32_PLL48CLK              (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE)

+#elif (STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S) && defined(STM32F413xx)

+#define STM32_PLL48CLK              STM32_PLLI2S_Q_CLKOUT

 #else

 #error "invalid source selected for PLL48CLK clock"

 #endif

 #else /* !STM32_CLOCK48_REQUIRED */

 #define STM32_PLL48CLK              0

-#endif /* !STM32_CLOCK48_REQUIRED */

+#endif /* STM32_CLOCK48_REQUIRED */

+

+#if defined(STM32F413xx) || defined(STM32F446xx)

+#if STM32_TIMPRE == STM32_TIMPRE_HCLK

+/**

+ * @brief   Clock of timers connected to APB1

+ *          (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).

+ */

+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \

+    (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \

+    (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) ||            \

+    defined(__DOXYGEN__)

+#define STM32_TIMCLK1               STM32_HCLK

+#else

+#define STM32_TIMCLK1               (STM32_PCLK1 * 4)

+#endif

+#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */

+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)

+#define STM32_TIMCLK1               STM32_HCLK

+#else /* !(STM32_TIMPRE_HCLK == STM32_TIMPRE_HCLK) */

+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)

+#endif

+#endif /* STM32_TIMPRE == STM32_TIMPRE_HCLK */

+

+#if (STM32_TIMPRE == STM32_TIMPRE_HCLK) || defined(STM32F446xx)

+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) ||                                    \

+    (STM32_PPRE1 == STM32_PPRE1_DIV2) ||                                    \

+    (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) ||            \

+    defined(__DOXYGEN__)

+/**

+ * @brief   Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).

+ */

+#define STM32_TIMCLK2               STM32_HCLK

+#else

+#define STM32_TIMCLK2               (STM32_PCLK2 * 4)

+#endif

+#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */

+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)

+#define STM32_TIMCLK2               STM32_HCLK

+#else

+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)

+#endif

+#endif /* STM32_TIMPRE != STM32_TIMPRE_HCLK */

+

+#else /* !(defined(STM32F413xx) || defined(STM32F446xx)) */

 

 /**

  * @brief   Clock of timers connected to APB1

@@ -1941,6 +2128,7 @@
 #else

 #define STM32_TIMCLK2               (STM32_PCLK2 * 2)

 #endif

+#endif /*  defined(STM32F413) */

 

 /**

  * @brief   Flash settings.

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
index bb53b4418..483c3fedc 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
@@ -130,6 +130,12 @@
 #define STM32_TIM14_NUMBER          45

 

 /*

+ * LPTIM units.

+ */

+#define STM32_LPTIM1_HANDLER        Vector1C4

+

+#define STM32_LPTIM1_NUMBER         97

+/*

  * USART units.

  */

 #define STM32_USART1_HANDLER        VectorD4

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index e22cf27ab..e55caf2f6 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -605,6 +605,30 @@
 /** @} */

 

 /**

+ * @brief   Enables the I2C4 peripheral clock.

+ *

+ * @api

+ */

+#define rccEnableI2C4() rccEnableAPB1(RCC_APB1ENR_FMPI2C1EN, lp)

+

+/**

+ * @brief   Disables the I2C4 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_FMPI2C1EN, lp)

+

+/**

+ * @brief   Resets the I2C4 peripheral.

+ *

+ * @api

+ */

+#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_FMPI2C1RST)

+/** @} */

+

+/**

  * @name    OTG peripherals specific RCC operations

  * @{

  */

@@ -1198,6 +1222,31 @@
 /** @} */

 

 /**

+ * @brief   Enables the LPTIM1 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableLPTIM1(lp) rccEnableAPB1(RCC_APB1ENR_LPTIM1EN, lp)

+

+/**

+ * @brief   Disables the LPTIM1 peripheral clock.

+ *

+ * @api

+ */

+#define rccDisableLPTIM1() rccDisableAPB1(RCC_APB1ENR_LPTIM1EN, lp)

+

+/**

+ * @brief   Resets the LPTIM1 peripheral.

+ *

+ * @api

+ */

+#define rccResetLPTIM1() rccResetAPB1(RCC_APB1RSTR_LPTIM1RST)

+/** @} */

+

+/**

  * @name    USART/UART peripherals specific RCC operations

  * @{

  */

@@ -1387,6 +1436,56 @@
 /** @} */

 

 /**

+ * @brief   Enables the UART9 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART9(lp) rccEnableAPB2(RCC_APB2ENR_UART9EN, lp)

+

+/**

+ * @brief   Disables the UART9 peripheral clock.

+ *

+ * @api

+ */

+#define rccDisableUART9() rccDisableAPB2(RCC_APB2ENR_UART9EN, lp)

+

+/**

+ * @brief   Resets the UART9 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART9() rccResetAPB2(RCC_APB2RSTR_UART9RST)

+/** @} */

+

+/**

+ * @brief   Enables the UART10 peripheral clock.

+ * @note    The @p lp parameter is ignored in this family.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableUART10(lp) rccEnableAPB2(RCC_APB2ENR_UART10EN, lp)

+

+/**

+ * @brief   Disables the UART10 peripheral clock.

+ *

+ * @api

+ */

+#define rccDisableUART10(lp) rccDisableAPB2(RCC_APB2ENR_UART10EN, lp)

+

+/**

+ * @brief   Resets the UART10 peripheral.

+ *

+ * @api

+ */

+#define rccResetUART10() rccResetAPB2(RCC_APB2RSTR_UART10RST)

+/** @} */

+

+/**

  * @name    LTDC peripheral specific RCC operations

  * @{

  */

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index 20812b8c4..b8048770d 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -40,6 +40,9 @@
 #define STM32F427_437xx

 #define STM32F4XX

 

+#elif defined(STM32F413xx)

+#define STM32F4XX

+

 #elif defined(STM32F412Cx) || defined(STM32F412Rx) ||                       \

       defined(STM32F412Vx) || defined(STM32F412Zx)

 #define STM32F412xx

@@ -1165,6 +1168,379 @@
 #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */

 

 /*===========================================================================*/

+/* STM32F413xx, STM32F413Mx, STM32F413Rx, STM32F413Vx, STM32F413Zx           */

+/*===========================================================================*/

+

+#if defined(STM32F413xx)

+

+/* ADC attributes.*/

+#define STM32_ADC_HANDLER                   Vector88

+#define STM32_ADC_NUMBER                    18

+

+#define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

+#define STM32_HAS_ADC2                      FALSE

+#define STM32_HAS_ADC3                      FALSE

+#define STM32_HAS_ADC4                      FALSE

+

+#define STM32_HAS_SDADC1                    FALSE

+#define STM32_HAS_SDADC2                    FALSE

+#define STM32_HAS_SDADC3                    FALSE

+

+/* CAN attributes.*/

+#define STM32_HAS_CAN1                      TRUE

+#define STM32_HAS_CAN2                      TRUE

+#define STM32_HAS_CAN3                      FALSE

+#define STM32_CAN_MAX_FILTERS               28

+

+/* DAC attributes.*/

+#define STM32_HAS_DAC1_CH1                  FALSE

+#define STM32_HAS_DAC1_CH2                  FALSE

+#define STM32_HAS_DAC2_CH1                  FALSE

+#define STM32_HAS_DAC2_CH2                  FALSE

+

+/* DMA attributes.*/

+#define STM32_ADVANCED_DMA                  TRUE

+#define STM32_DMA_CACHE_HANDLING            FALSE

+

+#define STM32_HAS_DMA1                      TRUE

+#define STM32_DMA1_CH0_HANDLER              Vector6C

+#define STM32_DMA1_CH1_HANDLER              Vector70

+#define STM32_DMA1_CH2_HANDLER              Vector74

+#define STM32_DMA1_CH3_HANDLER              Vector78

+#define STM32_DMA1_CH4_HANDLER              Vector7C

+#define STM32_DMA1_CH5_HANDLER              Vector80

+#define STM32_DMA1_CH6_HANDLER              Vector84

+#define STM32_DMA1_CH7_HANDLER              VectorFC

+#define STM32_DMA1_CH0_NUMBER               11

+#define STM32_DMA1_CH1_NUMBER               12

+#define STM32_DMA1_CH2_NUMBER               13

+#define STM32_DMA1_CH3_NUMBER               14

+#define STM32_DMA1_CH4_NUMBER               15

+#define STM32_DMA1_CH5_NUMBER               16

+#define STM32_DMA1_CH6_NUMBER               17

+#define STM32_DMA1_CH7_NUMBER               47

+

+#define STM32_HAS_DMA2                      TRUE

+#define STM32_DMA2_CH0_HANDLER              Vector120

+#define STM32_DMA2_CH1_HANDLER              Vector124

+#define STM32_DMA2_CH2_HANDLER              Vector128

+#define STM32_DMA2_CH3_HANDLER              Vector12C

+#define STM32_DMA2_CH4_HANDLER              Vector130

+#define STM32_DMA2_CH5_HANDLER              Vector150

+#define STM32_DMA2_CH6_HANDLER              Vector154

+#define STM32_DMA2_CH7_HANDLER              Vector158

+#define STM32_DMA2_CH0_NUMBER               56

+#define STM32_DMA2_CH1_NUMBER               57

+#define STM32_DMA2_CH2_NUMBER               58

+#define STM32_DMA2_CH3_NUMBER               59

+#define STM32_DMA2_CH4_NUMBER               60

+#define STM32_DMA2_CH5_NUMBER               68

+#define STM32_DMA2_CH6_NUMBER               69

+#define STM32_DMA2_CH7_NUMBER               70

+

+/* ETH attributes.*/

+#define STM32_HAS_ETH                       FALSE

+

+/* EXTI attributes.*/

+#define STM32_EXTI_NUM_LINES                23

+#define STM32_EXTI_IMR_MASK                 0x00000000U

+

+/* GPIO attributes.*/

+#define STM32_HAS_GPIOA                     TRUE

+#define STM32_HAS_GPIOB                     TRUE

+#define STM32_HAS_GPIOC                     TRUE

+#define STM32_HAS_GPIOD                     TRUE

+#define STM32_HAS_GPIOE                     TRUE

+#define STM32_HAS_GPIOH                     TRUE

+#define STM32_HAS_GPIOF                     TRUE

+#define STM32_HAS_GPIOG                     TRUE

+#define STM32_HAS_GPIOI                     FALSE

+#define STM32_HAS_GPIOJ                     FALSE

+#define STM32_HAS_GPIOK                     FALSE

+#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

+                                             RCC_AHB1ENR_GPIOBEN |          \

+                                             RCC_AHB1ENR_GPIOCEN |          \

+                                             RCC_AHB1ENR_GPIODEN |          \

+                                             RCC_AHB1ENR_GPIOEEN |          \

+                                             RCC_AHB1ENR_GPIOFEN |          \

+                                             RCC_AHB1ENR_GPIOGEN |          \

+                                             RCC_AHB1ENR_GPIOHEN)

+

+/* I2C attributes.*/

+#define STM32_HAS_I2C1                      TRUE

+#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C1_RX_DMA_CHN               0x00100001

+#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN               0x11000000

+

+#define STM32_HAS_I2C2                      TRUE

+#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_I2C2_RX_DMA_CHN               0x00007700

+#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

+#define STM32_I2C2_TX_DMA_CHN               0x70000000

+

+#define STM32_HAS_I2C3                      TRUE

+#define STM32_I2C3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_I2C3_RX_DMA_CHN               0x00000310

+#define STM32_I2C3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 4) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C3_TX_DMA_CHN               0x00630000

+

+#define STM32_HAS_I2C4                      TRUE

+#define STM32_I2C4_SUPPORTS_FMP             TRUE

+#define STM32_HAS_I2C4                      TRUE

+#define STM32_I2C4_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_I2C4_RX_DMA_CHN               0x00001000

+#define STM32_I2C4_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 1)

+#define STM32_I2C4_TX_DMA_CHN               0x00000020

+

+/* QUADSPI attributes.*/

+#define STM32_HAS_QUADSPI1                  TRUE

+#define STM32_QUADSPI1_HANDLER              Vector1B0

+#define STM32_QUADSPI1_NUMBER               92

+#define STM32_QUADSPI1_DMA_MSK              STM32_DMA_STREAM_ID_MSK(2, 7)

+#define STM32_QUADSPI1_DMA_CHN              0x30000000

+

+/* RTC attributes.*/

+#define STM32_HAS_RTC                       TRUE

+#define STM32_RTC_HAS_SUBSECONDS            TRUE

+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

+#define STM32_RTC_NUM_ALARMS                2

+#define STM32_RTC_HAS_INTERRUPTS            FALSE

+

+/* SDIO attributes.*/

+#define STM32_HAS_SDIO                      TRUE

+#define STM32_SDC_SDIO_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 6))

+#define STM32_SDC_SDIO_DMA_CHN              0x04004000

+

+/* SPI attributes.*/

+#define STM32_HAS_SPI1                      TRUE

+#define STM32_SPI1_SUPPORTS_I2S             TRUE

+#define STM32_SPI1_I2S_FULLDUPLEX           FALSE

+#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_SPI1_RX_DMA_CHN               0x00000303

+#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_SPI1_TX_DMA_CHN               0x00303200

+

+#define STM32_HAS_SPI2                      TRUE

+#define STM32_SPI2_SUPPORTS_I2S             TRUE

+#define STM32_SPI2_I2S_FULLDUPLEX           TRUE

+#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_SPI2_RX_DMA_CHN               0x00000000

+#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_SPI2_TX_DMA_CHN               0x00000000

+

+#define STM32_HAS_SPI3                      TRUE

+#define STM32_SPI3_SUPPORTS_I2S             TRUE

+#define STM32_SPI3_I2S_FULLDUPLEX           TRUE

+#define STM32_SPI3_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_SPI3_RX_DMA_CHN               0x00000000

+#define STM32_SPI3_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 5) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_SPI3_TX_DMA_CHN               0x00000000

+

+#define STM32_HAS_SPI4                      TRUE

+#define STM32_SPI4_SUPPORTS_I2S             TRUE

+#define STM32_SPI4_I2S_FULLDUPLEX           FALSE

+#define STM32_SPI4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_SPI4_RX_DMA_CHN               0x00045004

+#define STM32_SPI4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_SPI4_TX_DMA_CHN               0x00050040

+

+#define STM32_HAS_SPI5                      TRUE

+#define STM32_SPI5_SUPPORTS_I2S             TRUE

+#define STM32_SPI5_I2S_FULLDUPLEX           FALSE

+#define STM32_SPI5_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_SPI5_RX_DMA_CHN               0x00702000

+#define STM32_SPI5_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 4) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 6))

+#define STM32_SPI5_TX_DMA_CHN               0x07520000

+

+#define STM32_HAS_SPI6                      FALSE

+

+/* TIM attributes.*/

+#define STM32_TIM_MAX_CHANNELS              4

+

+#define STM32_HAS_TIM1                      TRUE

+#define STM32_TIM1_IS_32BITS                FALSE

+#define STM32_TIM1_CHANNELS                 4

+

+#define STM32_HAS_TIM2                      TRUE

+#define STM32_TIM2_IS_32BITS                TRUE

+#define STM32_TIM2_CHANNELS                 4

+

+#define STM32_HAS_TIM3                      TRUE

+#define STM32_TIM3_IS_32BITS                FALSE

+#define STM32_TIM3_CHANNELS                 4

+

+#define STM32_HAS_TIM4                      TRUE

+#define STM32_TIM4_IS_32BITS                FALSE

+#define STM32_TIM4_CHANNELS                 4

+

+#define STM32_HAS_TIM5                      TRUE

+#define STM32_TIM5_IS_32BITS                TRUE

+#define STM32_TIM5_CHANNELS                 4

+

+#define STM32_HAS_TIM6                      TRUE

+#define STM32_TIM6_IS_32BITS                FALSE

+#define STM32_TIM6_CHANNELS                 0

+

+#define STM32_HAS_TIM7                      TRUE

+#define STM32_TIM7_IS_32BITS                FALSE

+#define STM32_TIM7_CHANNELS                 0

+

+#define STM32_HAS_TIM8                      TRUE

+#define STM32_TIM8_IS_32BITS                FALSE

+#define STM32_TIM8_CHANNELS                 4

+

+#define STM32_HAS_TIM9                      TRUE

+#define STM32_TIM9_IS_32BITS                FALSE

+#define STM32_TIM9_CHANNELS                 2

+

+#define STM32_HAS_TIM10                     TRUE

+#define STM32_TIM10_IS_32BITS               FALSE

+#define STM32_TIM10_CHANNELS                1

+

+#define STM32_HAS_TIM11                     TRUE

+#define STM32_TIM11_IS_32BITS               FALSE

+#define STM32_TIM11_CHANNELS                1

+

+#define STM32_HAS_TIM12                     TRUE

+#define STM32_TIM12_IS_32BITS               FALSE

+#define STM32_TIM12_CHANNELS                2

+

+#define STM32_HAS_TIM13                     TRUE

+#define STM32_TIM13_IS_32BITS               FALSE

+#define STM32_TIM13_CHANNELS                1

+

+#define STM32_HAS_TIM14                     TRUE

+#define STM32_TIM14_IS_32BITS               FALSE

+#define STM32_TIM14_CHANNELS                1

+

+#define STM32_HAS_TIM15                     FALSE

+#define STM32_HAS_TIM16                     FALSE

+#define STM32_HAS_TIM17                     FALSE

+#define STM32_HAS_TIM18                     FALSE

+#define STM32_HAS_TIM19                     FALSE

+#define STM32_HAS_TIM20                     FALSE

+#define STM32_HAS_TIM21                     FALSE

+#define STM32_HAS_TIM22                     FALSE

+

+#define STM32_HAS_LPTIM1                    TRUE

+

+/* USART attributes.*/

+#define STM32_HAS_USART1                    TRUE

+#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_USART1_RX_DMA_CHN             0x00400400

+#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

+#define STM32_USART1_TX_DMA_CHN             0x40000000

+

+#define STM32_HAS_USART2                    TRUE

+#define STM32_USART2_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 5)

+#define STM32_USART2_RX_DMA_CHN             0x00400000

+#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

+#define STM32_USART2_TX_DMA_CHN             0x04000000

+

+#define STM32_HAS_USART3                    TRUE

+#define STM32_USART3_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 1)

+#define STM32_USART3_RX_DMA_CHN             0x00000040

+#define STM32_USART3_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART3_TX_DMA_CHN             0x00074000

+

+#define STM32_HAS_UART4                     TRUE

+#define STM32_UART4_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 2)

+#define STM32_UART4_RX_DMA_CHN              0x00000400

+#define STM32_UART4_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_UART4_TX_DMA_CHN              0x00040000

+

+#define STM32_HAS_UART5                     TRUE

+#define STM32_UART5_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)

+#define STM32_UART5_RX_DMA_CHN              0x00000004

+#define STM32_UART5_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 7)

+#define STM32_UART5_TX_DMA_CHN              0x40000000

+

+#define STM32_HAS_USART6                    TRUE

+#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_USART6_RX_DMA_CHN             0x00000550

+#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_USART6_TX_DMA_CHN             0x55000000

+

+#define STM32_HAS_UART7                     TRUE

+#define STM32_UART7_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_UART7_RX_DMA_CHN              0x00005000

+#define STM32_UART7_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 1)

+#define STM32_UART7_TX_DMA_CHN              0x00000050

+

+#define STM32_HAS_UART8                     TRUE

+#define STM32_UART8_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 6)

+#define STM32_UART8_RX_DMA_CHN              0x05000000

+#define STM32_UART8_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(1, 0)

+#define STM32_UART8_TX_DMA_CHN              0x00000005

+

+#define STM32_HAS_UART9                     TRUE

+#define STM32_UART9_RX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(2, 7)

+#define STM32_UART9_RX_DMA_CHN              0x00000000

+#define STM32_UART9_TX_DMA_MSK              STM32_DMA_STREAM_ID_MSK(2, 0)

+#define STM32_UART9_TX_DMA_CHN              0x00000001

+

+#define STM32_HAS_UART10                    TRUE

+#define STM32_UART10_RX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 3)

+#define STM32_UART10_RX_DMA_CHN             0x00009000

+#define STM32_UART10_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 5)

+#define STM32_UART10_TX_DMA_CHN             0x00900000

+

+#define STM32_HAS_LPUART1                   FALSE

+

+/* USB attributes.*/

+#define STM32_OTG_STEPPING                  2

+#define STM32_HAS_OTG1                      TRUE

+#define STM32_OTG1_ENDPOINTS                3

+

+#define STM32_HAS_OTG2                      FALSE

+#define STM32_HAS_USB                       FALSE

+

+/* IWDG attributes.*/

+#define STM32_HAS_IWDG                      TRUE

+#define STM32_IWDG_IS_WINDOWED              FALSE

+

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      FALSE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     FALSE

+

+/* FSMC attributes.*/

+#define STM32_HAS_FSMC                      FALSE

+

+/* CRC attributes.*/

+#define STM32_HAS_CRC                       TRUE

+#define STM32_CRC_PROGRAMMABLE              FALSE

+

+#endif /* defined(STM32F413xx) */

+

+/*===========================================================================*/

 /* STM32F412Cx, STM32F412Rx, STM32F412Vx, STM32F412Zx                        */

 /*===========================================================================*/

 

diff --git a/readme.txt b/readme.txt
index 56f1419a1..04c73486c 100644
--- a/readme.txt
+++ b/readme.txt
@@ -91,6 +91,8 @@
 *****************************************************************************

 

 *** Next ***

+- NEW: Added support for STM32F413, added ability to handle the TIMPRE bit

+       in the RCC_CFGR register.

 - NEW: Added optional support for character match callback in the UART

        high level driver.

 - NEW: Change, chMtxGetNextMutexS() renamed to chMtxGetNextMutexX().