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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-07 08:34:43 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-07 08:34:43 +0000 |
| commit | b058a251b800ac85c10019c6123a629bc942eaaf (patch) | |
| tree | d57ee358f687268980b4bba4f51f48234001cc22 /os/hal/ports/STM32/STM32F4xx/hal_lld.c | |
| parent | 0c9f553e4fed400108f90f1504e88d1882c097e6 (diff) | |
| download | ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.tar.gz ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.tar.bz2 ChibiOS-b058a251b800ac85c10019c6123a629bc942eaaf.zip | |
Added support for STM32F413, added ability to handle the TIMPRE bit in the RCC_CFGR register.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12011 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/hal_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld.c | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c index d74ddbf0e..2948c78ae 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c @@ -234,9 +234,15 @@ void stm32_clock_init(void) { #endif /* STM32_ACTIVATE_PLL */
#if STM32_ACTIVATE_PLLI2S
+#if defined(STM32F413xx)
+ /* PLLI2S activation.*/
+ RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
+ STM32_I2SSRC | STM32_PLLI2SQ | STM32_PLLI2SM;
+#else
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
STM32_PLLI2SQ | STM32_PLLI2SM;
+#endif
RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
@@ -255,10 +261,17 @@ void stm32_clock_init(void) { ;
#endif /* STM32_ACTIVATE_PLLSAI */
+#if defined(STM32F413xx)
+ /* Other clock-related settings (dividers, MCO etc).*/
+ RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
+ STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
+#else
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
+#endif
#if defined(STM32F446xx)
/* DCKCFGR register initialization, note, must take care of the _OFF
@@ -274,6 +287,9 @@ void stm32_clock_init(void) { #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
+#if STM32_TIMPRE == STM32_TIMPRE_HCLK
+ dckcfgr |= STM32_TIMPRE_HCLK;
+#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
}
RCC->DCKCFGR2 = STM32_CK48MSEL;
@@ -282,18 +298,37 @@ void stm32_clock_init(void) { pseudo settings.*/
{
uint32_t dckcfgr = 0;
- #if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
- #endif
- #if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
- #endif
- #if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+#endif
+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
- #endif
+#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ |
STM32_CK48MSEL;
}
+#elif defined(STM32F413xx)
+ /* DCKCFGR register initialization. */
+ {
+ uint32_t dckcfgr = 0;
+#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
+ dckcfgr |= STM32_SAI2SEL;
+#endif
+#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
+ dckcfgr |= STM32_SAI1SEL;
+#endif
+#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
+ dckcfgr |= STM32_PLLSAIDIVR;
+#endif
+#if STM32_TIMPRE == STM32_TIMPRE_HCLK
+ dckcfgr |= STM32_TIMPRE_HCLK;
+#endif
+ RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
+ }
+ RCC->DCKCFGR2 = STM32_CK48MSEL;
#endif
/* Flash setup.*/
|