diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-12 16:26:56 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-12 16:26:56 +0000 |
| commit | c246d898d2d2c16972182dab3e7201c359c8b7da (patch) | |
| tree | 5b7bffe17908f133f213b36ae5ab9d50ac899aae /os/hal/ports/STM32/STM32F3xx/stm32_registry.h | |
| parent | d7b170b525754e5fc502c32d796dfa594775fd0e (diff) | |
| download | ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.tar.gz ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.tar.bz2 ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.zip | |
New STM32F3xx CMSIS headers.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8587 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F3xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 777 |
1 files changed, 757 insertions, 20 deletions
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 36ceae28e..25de802d8 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -208,11 +208,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM9 FALSE
@@ -278,6 +278,256 @@ #endif /* defined(STM32F303xC) */
/*===========================================================================*/
+/* STM32F303xE. */
+/*===========================================================================*/
+#if defined(STM32F303xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 TRUE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F303xE) */
+
+/*===========================================================================*/
/* STM32F303x8. */
/*===========================================================================*/
#if defined(STM32F303x8)
@@ -420,11 +670,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM8 FALSE
@@ -622,11 +872,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -827,11 +1077,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -1055,11 +1305,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM7 FALSE
@@ -1127,6 +1377,245 @@ #endif /* defined(STM32F302xC) */
/*===========================================================================*/
+/* STM32F302xE. */
+/*===========================================================================*/
+#if defined(STM32F302xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F302xE) */
+
+/*===========================================================================*/
/* STM32F318x8. */
/*===========================================================================*/
#if defined(STM32F318x8)
@@ -1264,11 +1753,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -1469,11 +1958,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
@@ -1536,7 +2025,7 @@ /*===========================================================================*/
/* STM32F358xC. */
/*===========================================================================*/
-#if defined(STM32F358xC) || defined(__DOXYGEN__)
+#if defined(STM32F358xC)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
@@ -1694,11 +2183,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM7 FALSE
@@ -1768,7 +2257,7 @@ /*===========================================================================*/
/* STM32F334x8. */
/*===========================================================================*/
-#if defined(STM32F334x8) || defined(__DOXYGEN__)
+#if defined(STM32F334x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
@@ -1904,11 +2393,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
@@ -1968,6 +2457,254 @@ #define STM32_CRC_PROGRAMMABLE TRUE
#endif /* defined(STM32F334x8) */
+/*===========================================================================*/
+/* STM32F398xx. */
+/*===========================================================================*/
+#if defined(STM32F398xx)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 TRUE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F398xx) */
+
/** @} */
#endif /* _STM32_REGISTRY_H_ */
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