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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-11-25 13:56:44 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-11-25 13:56:44 +0000 |
| commit | 6268914b7c6eac2a8ee04b2f9d4c270fc5363dee (patch) | |
| tree | 49eb94045477dd3d2794afee365adfb21dcee5f0 /os/hal/ports/STM32/STM32F0xx/stm32_registry.h | |
| parent | b8a4c26a9cab50e5a845d0033665a4d74b17444b (diff) | |
| download | ChibiOS-6268914b7c6eac2a8ee04b2f9d4c270fc5363dee.tar.gz ChibiOS-6268914b7c6eac2a8ee04b2f9d4c270fc5363dee.tar.bz2 ChibiOS-6268914b7c6eac2a8ee04b2f9d4c270fc5363dee.zip | |
RTC adjustments for F0 devices.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12439 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 98 |
1 files changed, 81 insertions, 17 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index f7749ed74..966e8f4d4 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -37,8 +37,16 @@ * @name STM32F0xx capabilities
* @{
*/
+
+/*===========================================================================*/
+/* Common. */
+/*===========================================================================*/
+
+/* RNG attributes.*/
+#define STM32_HAS_RNG1 FALSE
+
/*===========================================================================*/
-/* STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC. */
+/* STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC. */
/*===========================================================================*/
#if defined(STM32F030x4) || defined(STM32F030x6) || \
defined(STM32F030x8) || defined(STM32F030xC) || defined(__DOXYGEN__)
@@ -117,7 +125,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 20
-#define STM32_EXTI_IMR_MASK 0xFFF50000U
+#define STM32_EXTI_IMR1_MASK 0xFFF50000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -174,7 +182,14 @@ #define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#endif
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -428,7 +443,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x0FF40000U
+#define STM32_EXTI_IMR1_MASK 0x0FF40000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -466,7 +481,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -639,7 +661,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x7FF40000U
+#define STM32_EXTI_IMR1_MASK 0x7FF40000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -677,7 +699,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -858,7 +887,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x7FF40000U
+#define STM32_EXTI_IMR1_MASK 0x7FF40000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -896,7 +925,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -1086,7 +1122,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x0F940000U
+#define STM32_EXTI_IMR1_MASK 0x0F940000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -1130,7 +1166,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -1322,7 +1365,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x7F840000U
+#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -1374,7 +1417,14 @@ #define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
#endif
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -1588,7 +1638,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x7F840000U
+#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -1635,7 +1685,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -1870,7 +1927,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 32
-#define STM32_EXTI_IMR_MASK 0x7F840000U
+#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
@@ -1918,7 +1975,14 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
#define STM32_RTC_NUM_ALARMS 1
-#define STM32_RTC_HAS_INTERRUPTS FALSE
+#define STM32_RTC_STORAGE_SIZE 0
+#define STM32_RTC_COMMON_HANDLER Vector48
+#define STM32_RTC_COMMON_NUMBER 2
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 19
+#define STM32_RTC_WKUP_EXTI 20
+#define STM32_RTC_IRQ_ENABLE() \
+ nvicEnableVector(STM32_RTC_COMMON_NUMBER, STM32_IRQ_EXTI17_20_IRQ_PRIORITY)
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
|