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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-12-20 10:33:27 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2014-12-20 10:33:27 +0000
commit2e7aee242c1df1223b46abaaef063b0bbccd77e9 (patch)
treee5b307d89948e1826213acc8dd9d023b1201229f /os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
parent372b97790c3992966043fcbf3f8e1955c6ab97ce (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7588 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx/stm32_rcc.h')
-rw-r--r--os/hal/ports/STM32/STM32F0xx/stm32_rcc.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
index 1c3835357..73e026f31 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
@@ -524,8 +524,43 @@
* @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+/** @} */
+
+/**
+ * @name USB peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/**
+ * @name CRC peripherals specific RCC operations
+ * @{
+ */
+/**
* @brief Enables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
@@ -551,8 +586,13 @@
* @api
*/
#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
+/** @} */
/**
+ * @name WWDG peripherals specific RCC operations
+ * @{
+ */
+/**
* @brief Enables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*