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-rw-r--r--os/hal/ports/STM32/LLD/USBv1/stm32_usb.h16
-rw-r--r--os/hal/ports/STM32/LLD/USBv1/usb_lld.c10
-rw-r--r--os/hal/ports/STM32/LLD/USBv1/usb_lld.h16
-rw-r--r--os/hal/ports/STM32/STM32F0xx/hal_lld.h72
-rw-r--r--os/hal/ports/STM32/STM32F0xx/stm32_isr.h8
-rw-r--r--os/hal/ports/STM32/STM32F0xx/stm32_rcc.h40
-rw-r--r--testhal/STM32/STM32F0xx/USB_CDC/.project2
-rw-r--r--testhal/STM32/STM32F0xx/USB_CDC/main.c4
-rw-r--r--testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h2
9 files changed, 135 insertions, 35 deletions
diff --git a/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
index d16b6266c..69f7beb62 100644
--- a/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
+++ b/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h
@@ -95,6 +95,14 @@ typedef struct {
* @brief RX counter register 1.
*/
volatile uint16_t RXCOUNT1;
+ /*
+ * @brief LPM Control and Status Register.
+ */
+ volatile uint32_t LPMCSR;
+ /*
+ * @brief Battery Charging Detector
+ */
+ volatile uint32_t BCDR;
} stm32_usb_descriptor_t;
/**
@@ -108,12 +116,20 @@ typedef struct {
/**
* @brief USB registers block numeric address.
*/
+#if defined(USB_BASE) || defined(__DOXYGEN__)
+#define STM32_USB_BASE USB_BASE
+#else
#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00)
+#endif
/**
* @brief USB RAM numeric address.
*/
+#if defined(USB_PMAADDR) || defined(__DOXYGEN__)
+#define STM32_USBRAM_BASE USB_PMAADDR
+#else
#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
+#endif
/**
* @brief Pointer to the USB registers block.
diff --git a/os/hal/ports/STM32/LLD/USBv1/usb_lld.c b/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
index 3a7ff272d..e606dc390 100644
--- a/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+++ b/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
@@ -261,9 +261,7 @@ static void usb_packet_write_from_queue(stm32_usb_descriptor_t *udp,
/*===========================================================================*/
#if STM32_USB_USE_USB1 || defined(__DOXYGEN__)
-#if !defined(STM32_USB1_HP_HANDLER)
-#error "STM32_USB1_HP_HANDLER not defined"
-#endif
+#if STM32_USB1_HP_NUMBER != STM32_USB1_LP_NUMBER
/**
* @brief USB high priority interrupt handler.
*
@@ -275,10 +273,8 @@ CH_IRQ_HANDLER(STM32_USB1_HP_HANDLER) {
CH_IRQ_EPILOGUE();
}
+#endif /* STM32_USB1_LP_NUMBER != STM32_USB1_HP_NUMBER */
-#if !defined(STM32_USB1_LP_HANDLER)
-#error "STM32_USB1_LP_HANDLER not defined"
-#endif
/**
* @brief USB low priority interrupt handler.
*
@@ -416,7 +412,7 @@ CH_IRQ_HANDLER(STM32_USB1_LP_HANDLER) {
CH_IRQ_EPILOGUE();
}
-#endif
+#endif /* STM32_USB_USE_USB1 */
/*===========================================================================*/
/* Driver exported functions. */
diff --git a/os/hal/ports/STM32/LLD/USBv1/usb_lld.h b/os/hal/ports/STM32/LLD/USBv1/usb_lld.h
index ece8bf66a..090200641 100644
--- a/os/hal/ports/STM32/LLD/USBv1/usb_lld.h
+++ b/os/hal/ports/STM32/LLD/USBv1/usb_lld.h
@@ -108,6 +108,22 @@
#error "the USB driver requires a 48MHz clock"
#endif
+#if !defined(STM32_USB1_HP_HANDLER)
+#error "STM32_USB1_HP_HANDLER not defined"
+#endif
+
+#if !defined(STM32_USB1_HP_NUMBER)
+#error "STM32_USB1_HP_NUMBER not defined"
+#endif
+
+#if !defined(STM32_USB1_LP_HANDLER)
+#error "STM32_USB1_LP_HANDLER not defined"
+#endif
+
+#if !defined(STM32_USB1_LP_NUMBER)
+#error "STM32_USB1_LP_NUMBER not defined"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h
index e92ed269e..c685821e0 100644
--- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h
@@ -247,6 +247,9 @@
#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
+#define STM32_USBSW_MASK (1 << 7) /**< USB clock source mask. */
+#define STM32_USBSW_HSI48 (0 << 7) /**< USB clock is HSI48. */
+#define STM32_USBSW_PCLK (1 << 7) /**< USB clock is PCLK. */
#define STM32_ADCSW_MASK (1 << 8) /**< ADC clock source mask. */
#define STM32_ADCSW_HSI14 (0 << 8) /**< ADC clock is HSI14. */
#define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */
@@ -264,63 +267,63 @@
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT FALSE
+#define STM32_NO_INIT FALSE
#endif
/**
* @brief Enables or disables the programmable voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE FALSE
+#define STM32_PVD_ENABLE FALSE
#endif
/**
* @brief Sets voltage level for programmable voltage detector.
*/
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS STM32_PLS_LEV0
+#define STM32_PLS STM32_PLS_LEV0
#endif
/**
* @brief Enables or disables the HSI clock source.
*/
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED TRUE
+#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the HSI14 clock source.
*/
#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI14_ENABLED TRUE
+#define STM32_HSI14_ENABLED TRUE
#endif
/**
* @brief Enables or disables the HSI48 clock source.
*/
#if !defined(STM32_HSI48_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI48_ENABLED FALSE
+#define STM32_HSI48_ENABLED FALSE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED FALSE
+#define STM32_LSI_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
#endif
/**
@@ -331,7 +334,7 @@
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW STM32_SW_PLL
+#define STM32_SW STM32_SW_PLL
#endif
/**
@@ -342,7 +345,7 @@
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLSRC STM32_PLLSRC_HSE
#endif
/**
@@ -363,7 +366,7 @@
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE 6
+#define STM32_PLLMUL_VALUE 6
#endif
/**
@@ -372,63 +375,70 @@
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_HPRE STM32_HPRE_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
-#define STM32_PPRE STM32_PPRE_DIV1
+#define STM32_PPRE STM32_PPRE_DIV1
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADCPRE STM32_ADCPRE_DIV4
+#define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
/**
* @brief ADC clock source.
*/
#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
-#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_ADCSW STM32_ADCSW_HSI14
+#endif
+
+/**
+ * @brief USB Clock source.
+ */
+#if !defined(STM32_USBSW) || defined(__DOXYGEN__)
+#define STM32_USBSW STM32_USBSW_HSI48
#endif
/**
* @brief CEC clock source.
*/
#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
-#define STM32_CECSW STM32_CECSW_HSI
+#define STM32_CECSW STM32_CECSW_HSI
#endif
/**
* @brief I2C1 clock source.
*/
#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
-#define STM32_I2C1SW STM32_I2C1SW_HSI
+#define STM32_I2C1SW STM32_I2C1SW_HSI
#endif
/**
* @brief USART1 clock source.
*/
#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
-#define STM32_USART1SW STM32_USART1SW_PCLK
+#define STM32_USART1SW STM32_USART1SW_PCLK
#endif
/**
* @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCSEL STM32_RTCSEL_LSI
#endif
/** @} */
@@ -603,6 +613,7 @@
/* PLL activation conditions.*/
#if (STM32_SW == STM32_SW_PLL) || \
+ (STM32_USBSW == STM32_USBSW_PCLK) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
@@ -750,7 +761,7 @@
/**
* @brief ADC frequency.
*/
-#if STM32_ADCSW == STM32_ADCSW_HSI14
+#if (STM32_ADCSW == STM32_ADCSW_HSI14) || defined(__DOXYGEN__)
#define STM32_ADCCLK STM32_HSI14CLK
#elif STM32_ADCSW == STM32_ADCSW_PCLK
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
@@ -770,9 +781,20 @@
#endif
/**
+ * @brief USB frequency.
+ */
+#if (STM32_USBSW == STM32_USBSW_HSI48) || defined(__DOXYGEN__)
+#define STM32_USBCLK STM32_HSI48CLK
+#elif STM32_USBSW == STM32_USBSW_PCLK
+#define STM32_USBCLK STM32_PLLCLKOUT
+#else
+#error "invalid source selected for USB clock"
+#endif
+
+/**
* @brief CEC frequency.
*/
-#if STM32_CECSW == STM32_CECSW_HSI
+#if (STM32_CECSW == STM32_CECSW_HSI) || defined(__DOXYGEN__)
#define STM32_CECCLK STM32_HSICLK
#elif STM32_CECSW == STM32_CECSW_LSE
#define STM32_CECCLK STM32_LSECLK
@@ -783,7 +805,7 @@
/**
* @brief I2C1 frequency.
*/
-#if STM32_I2CSW == STM32_I2C1SW_HSI
+#if (STM32_I2CSW == STM32_I2C1SW_HSI) || defined(__DOXYGEN__)
#define STM32_I2C1CLK STM32_HSICLK
#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
#define STM32_I2C1CLK STM32_SYSCLK
@@ -794,7 +816,7 @@
/**
* @brief USART1 frequency.
*/
-#if STM32_USART1SW == STM32_USART1SW_PCLK
+#if (STM32_USART1SW == STM32_USART1SW_PCLK) || defined(__DOXYGEN__)
#define STM32_USART1CLK STM32_PCLK
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
index e81cc0e00..225b685b0 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_isr.h
@@ -64,6 +64,14 @@
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_LP_HANDLER VectorBC
+#define STM32_USB1_LP_NUMBER 31
+#define STM32_USB1_HP_HANDLER VectorBC
+#define STM32_USB1_HP_NUMBER 31
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
index 1c3835357..73e026f31 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_rcc.h
@@ -524,8 +524,43 @@
* @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+/** @} */
+
+/**
+ * @name USB peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
/**
+ * @brief Disables the USB peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/**
+ * @name CRC peripherals specific RCC operations
+ * @{
+ */
+/**
* @brief Enables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
@@ -551,8 +586,13 @@
* @api
*/
#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
+/** @} */
/**
+ * @name WWDG peripherals specific RCC operations
+ * @{
+ */
+/**
* @brief Enables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
diff --git a/testhal/STM32/STM32F0xx/USB_CDC/.project b/testhal/STM32/STM32F0xx/USB_CDC/.project
index 393b7838d..f097b827b 100644
--- a/testhal/STM32/STM32F0xx/USB_CDC/.project
+++ b/testhal/STM32/STM32F0xx/USB_CDC/.project
@@ -27,7 +27,7 @@
<link>
<name>board</name>
<type>2</type>
- <locationURI>CHIBIOS/os/hal/boards/ST_STM32F3_DISCOVERY</locationURI>
+ <locationURI>CHIBIOS/os/hal/boards/ST_STM32F072B_DISCOVERY</locationURI>
</link>
<link>
<name>os</name>
diff --git a/testhal/STM32/STM32F0xx/USB_CDC/main.c b/testhal/STM32/STM32F0xx/USB_CDC/main.c
index dc29d6855..f6f304cdc 100644
--- a/testhal/STM32/STM32F0xx/USB_CDC/main.c
+++ b/testhal/STM32/STM32F0xx/USB_CDC/main.c
@@ -451,9 +451,9 @@ static msg_t Thread1(void *arg) {
chRegSetThreadName("blinker");
while (TRUE) {
systime_t time = serusbcfg.usbp->state == USB_ACTIVE ? 250 : 500;
- palClearPad(GPIOE, GPIOE_LED3_RED);
+ palClearPad(GPIOC, GPIOC_LED_RED);
chThdSleepMilliseconds(time);
- palSetPad(GPIOE, GPIOE_LED3_RED);
+ palSetPad(GPIOC, GPIOC_LED_RED);
chThdSleepMilliseconds(time);
}
}
diff --git a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h
index 482b6ba11..fc28e745e 100644
--- a/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h
+++ b/testhal/STM32/STM32F0xx/USB_CDC/mcuconf.h
@@ -38,6 +38,7 @@
#define STM32_PLS STM32_PLS_LEV0
#define STM32_HSI_ENABLED TRUE
#define STM32_HSI14_ENABLED TRUE
+#define STM32_HSI48_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
@@ -52,6 +53,7 @@
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCSW STM32_ADCSW_HSI14
+#define STM32_USBSW STM32_USBSW_HSI48
#define STM32_CECSW STM32_CECSW_HSI
#define STM32_I2C1SW STM32_I2C1SW_HSI
#define STM32_USART1SW STM32_USART1SW_PCLK
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 13:32:25 +0000