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author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-05 10:30:58 +0000 |
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committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-05 10:30:58 +0000 |
commit | a6224d1964ef80a53500bde178d639c12dda98ee (patch) | |
tree | dd164c214dec2c418774f7fc668788e5e11a18db /os/hal/ports/STM32/LLD | |
parent | 590c1329a400a67c937b30dd55c58210549348b5 (diff) | |
download | ChibiOS-a6224d1964ef80a53500bde178d639c12dda98ee.tar.gz ChibiOS-a6224d1964ef80a53500bde178d639c12dda98ee.tar.bz2 ChibiOS-a6224d1964ef80a53500bde178d639c12dda98ee.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6754 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD')
-rw-r--r-- | os/hal/ports/STM32/LLD/DACv1/dac_lld.c | 2717 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/DACv1/dac_lld.h | 2811 |
2 files changed, 745 insertions, 4783 deletions
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c index bd65728db..4eee1725a 100644 --- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c +++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c @@ -1,2370 +1,351 @@ - - - - - -<!DOCTYPE html> -<html> - <head prefix="og: http://ogp.me/ns# fb: http://ogp.me/ns/fb# object: http://ogp.me/ns/object# article: http://ogp.me/ns/article# profile: http://ogp.me/ns/profile#"> - <meta charset='utf-8'> - <meta http-equiv="X-UA-Compatible" content="IE=edge"> - <title>ChibiOS/os/hal/ports/STM32/DACv1/dac_lld.c at dac-3.0 · mobyfab/ChibiOS · GitHub</title> - <link rel="search" type="application/opensearchdescription+xml" href="/opensearch.xml" title="GitHub" /> - <link rel="fluid-icon" href="https://github.com/fluidicon.png" title="GitHub" /> - <link rel="apple-touch-icon" sizes="57x57" href="/apple-touch-icon-114.png" /> - <link rel="apple-touch-icon" sizes="114x114" href="/apple-touch-icon-114.png" /> - <link rel="apple-touch-icon" sizes="72x72" href="/apple-touch-icon-144.png" /> - <link rel="apple-touch-icon" sizes="144x144" href="/apple-touch-icon-144.png" /> - <meta property="fb:app_id" content="1401488693436528"/> - - <meta content="@github" name="twitter:site" /><meta content="summary" name="twitter:card" /><meta content="mobyfab/ChibiOS" name="twitter:title" /><meta content="Mirror of the ChibiOS SVN repository (updated every 10 minutes)" name="twitter:description" /><meta content="https://1.gravatar.com/avatar/f152cebdb9ab085fd2369e2e9eb7342b?d=https%3A%2F%2Fidenticons.github.com%2Fdecfe48600b86598c97bc3499607b4a9.png&r=x&s=400" name="twitter:image:src" /> -<meta content="GitHub" property="og:site_name" /><meta content="object" property="og:type" /><meta content="https://1.gravatar.com/avatar/f152cebdb9ab085fd2369e2e9eb7342b?d=https%3A%2F%2Fidenticons.github.com%2Fdecfe48600b86598c97bc3499607b4a9.png&r=x&s=400" property="og:image" /><meta content="mobyfab/ChibiOS" property="og:title" /><meta content="https://github.com/mobyfab/ChibiOS" property="og:url" /><meta content="Mirror of the ChibiOS SVN repository (updated every 10 minutes)" property="og:description" /> - - <meta name="hostname" content="github-fe132-cp1-prd.iad.github.net"> - <meta name="ruby" content="ruby 2.1.0p0-github-tcmalloc (87c9373a41) [x86_64-linux]"> - <link rel="assets" href="https://github.global.ssl.fastly.net/"> - <link rel="conduit-xhr" href="https://ghconduit.com:25035/"> - <link rel="xhr-socket" href="/_sockets" /> - - - <meta name="msapplication-TileImage" content="/windows-tile.png" /> - <meta name="msapplication-TileColor" content="#ffffff" /> - <meta name="selected-link" value="repo_source" data-pjax-transient /> - <meta content="collector.githubapp.com" name="octolytics-host" /><meta content="collector-cdn.github.com" name="octolytics-script-host" /><meta content="github" name="octolytics-app-id" /><meta content="A4810129:1E8A:132FF1B:5316FA02" name="octolytics-dimension-request_id" /> - - - - - <link rel="icon" type="image/x-icon" href="/favicon.ico" /> - - <meta content="authenticity_token" name="csrf-param" /> -<meta content="+I75OT9V9FDjod/MtXvKnsFPyB9rwHLiS1IyZTd0pHk=" name="csrf-token" /> - - <link href="https://github.global.ssl.fastly.net/assets/github-144f6fbd93cc11df8cc03bc000351f75fa1e5875.css" media="all" rel="stylesheet" type="text/css" /> - <link href="https://github.global.ssl.fastly.net/assets/github2-ff993fcf465373a314708ecedfbbffc29250b930.css" media="all" rel="stylesheet" type="text/css" /> - - - - - <script crossorigin="anonymous" src="https://github.global.ssl.fastly.net/assets/frameworks-490867a148cf94468c141093ccd4e56ed2144eb9.js" type="text/javascript"></script> - <script async="async" crossorigin="anonymous" src="https://github.global.ssl.fastly.net/assets/github-a74d8739a439667125da3a5c5435962d57986a54.js" type="text/javascript"></script> +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/** + * @file STM32/DACv1/dac_lld.c + * @brief STM32 DAC subsystem low level driver source. + * + * @addtogroup DAC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_DAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if !defined(DAC1) +#define DAC1 DAC +#define rccEnableDAC1 rccEnableDAC +#define rccDisableDAC1 rccDisableDAC +#endif + +#define DAC_CHN1_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM, \ + STM32_DAC_CHN1_DMA_CHN) + +#define DAC_CHN2_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM, \ + STM32_DAC_CHN2_DMA_CHN) + +#define DAC_CHN3_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM, \ + STM32_DAC_CHN3_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief CHN1 driver identifier.*/ +#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__) +DACDriver DACD1; +#endif + +/** @brief CHN2 driver identifier.*/ +#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__) +DACDriver DACD2; +#endif + +/** @brief CHN3 driver identifier.*/ +#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__) +DACDriver DACD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + + +/** + * @brief Shared end/half-of-tx service routine. + * + * @param[in] dacp pointer to the @p DACDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) { +#if defined(STM32_DAC_DMA_ERROR_HOOK) + (void)dacp; + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + /* DMA errors handling.*/ + //~ _dac_isr_error_code(dacp, flags); + } + else { + if ((flags & STM32_DMA_ISR_HTIF) != 0) { + /* Half transfer processing.*/ + //~ _dac_isr_half_code(dacp); + } + if ((flags & STM32_DMA_ISR_TCIF) != 0) { + /* Transfer complete processing.*/ + //~ _dac_isr_full_code(dacp); + } + } +#else + (void)dacp; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level DAC driver initialization. + * + * @notapi + */ +void dac_lld_init(void) { + +#if STM32_DAC_USE_CHN1 + dacObjectInit(&DACD1); + DACD1.dac = DAC1; + DACD1.tim = STM32_TIM6; + DACD1.irqprio = STM32_DAC_CHN1_IRQ_PRIORITY; + DACD1.dma = STM32_DMA_STREAM(STM32_DAC_CHN1_DMA_STREAM); + DACD1.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN1_DMA_CHANNEL) | \ + STM32_DMA_CR_PL(STM32_DAC_CHN1_DMA_PRIORITY) | \ + STM32_DMA_CR_DIR_M2P | \ + STM32_DMA_CR_DMEIE | \ + STM32_DMA_CR_TEIE | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; +#endif + +#if STM32_DAC_USE_CHN2 + dacObjectInit(&DACD2); + DACD2.dac = DAC1; + DACD2.tim = STM32_TIM7; + DACD2.irqprio = STM32_DAC_CHN2_IRQ_PRIORITY; + DACD2.dma = STM32_DMA_STREAM(STM32_DAC_CHN2_DMA_STREAM); + DACD2.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN2_DMA_CHANNEL) | \ + STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \ + STM32_DMA_CR_DIR_M2P | \ + STM32_DMA_CR_DMEIE | \ + STM32_DMA_CR_TEIE | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; +#endif + +#if STM32_DAC_USE_CHN3 + dacObjectInit(&DACD3); + DACD3.dac = DAC2; + DACD3.tim = STM32_TIM18; + DACD3.irqprio = STM32_DAC_CHN3_IRQ_PRIORITY; + DACD3.dma = STM32_DMA_STREAM(STM32_DAC_CHN3_DMA_STREAM); + DACD3.dmamode = STM32_DMA_CR_CHSEL(DAC_CHN3_DMA_CHANNEL) | \ + STM32_DMA_CR_PL(STM32_DAC_CHN2_DMA_PRIORITY) | \ + STM32_DMA_CR_DIR_M2P | \ + STM32_DMA_CR_DMEIE | \ + STM32_DMA_CR_TEIE | \ + STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE; +#endif +} + +/** + * @brief Configures and activates the DAC peripheral. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @notapi + */ +void dac_lld_start(DACDriver *dacp) { + uint32_t arr, regshift, trgo, dataoffset; + bool b; + /* If in stopped state then enables the DAC and DMA clocks.*/ + if (dacp->state == DAC_STOP) { +#if STM32_DAC_USE_CHN1 + if (&DACD1 == dacp) { + rccEnableDAC1(FALSE); + /* DAC1 CR data is at bits 0:15 */ + regshift = 0; + dataoffset = 0; + /* Timer setup */ + rccEnableTIM6(FALSE); + rccResetTIM6(); + trgo = STM32_DAC_CR_TSEL_TIM6; + } +#endif +#if STM32_DAC_USE_CHN2 + if (&DACD2 == dacp) { + rccEnableDAC1(FALSE); + /* DAC2 CR data is at bits 16:31 */ + regshift = 16; + dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1; + /* Timer setup */ + rccEnableTIM7(FALSE); + rccResetTIM7(); + trgo = STM32_DAC_CR_TSEL_TIM7; + } +#endif +#if STM32_DAC_USE_CHN3 + if (&DACD3 == dacp) { + rccEnableDAC2(FALSE); + /* DAC3 CR data is at bits 0:15 */ + regshift = 0; + dataoffset = 0; + /* Timer setup */ + rccEnableTIM18(FALSE); + rccResetTIM18(); + trgo = STM32_DAC_CR_TSEL_TIM18; + } +#endif +#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3 + dacp->clock = STM32_TIMCLK1; + arr = (dacp->clock / dacp->config->frequency); + osalDbgAssert((arr <= 0xFFFF), + "invalid frequency"); + + /* Timer configuration.*/ + dacp->tim->CR1 = 0; /* Initially stopped. */ + dacp->tim->PSC = 0; /* Prescaler value. */ + dacp->tim->DIER = 0; + dacp->tim->ARR = arr; + dacp->tim->EGR = TIM_EGR_UG; /* Update event. */ + dacp->tim->CR2 &= (uint16_t)~TIM_CR2_MMS; + dacp->tim->CR2 |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */ + dacp->tim->CNT = 0; /* Reset counter. */ + dacp->tim->SR = 0; /* Clear pending IRQs. */ + /* Update Event IRQ enabled. */ + /* Timer start.*/ + dacp->tim->CR1 = TIM_CR1_CEN; + + /* DAC configuration */ + dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \ + (STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift; - <meta http-equiv="x-pjax-version" content="348cbaf0429fd819da9310a1f5148dfb"> - - <link data-pjax-transient rel='permalink' href='/mobyfab/ChibiOS/blob/42c482fbf2b4feae8dd524e664d084bb6de4f9ba/os/hal/ports/STM32/DACv1/dac_lld.c'> - - <meta name="description" content="Mirror of the ChibiOS SVN repository (updated every 10 minutes)" /> - - <meta content="1305966" name="octolytics-dimension-user_id" /><meta content="mobyfab" name="octolytics-dimension-user_login" /><meta content="10358524" name="octolytics-dimension-repository_id" /><meta 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data-clipboard-text="https://github.com/mobyfab/ChibiOS.git" data-copied-hint="copied!"><span class="octicon octicon-clippy"></span></span> - </div> -</div> - + /* DMA setup. */ + b = dmaStreamAllocate(dacp->dma, + dacp->irqprio, + (stm32_dmaisr_t)dac_lld_serve_tx_interrupt, + (void *)dacp); + osalDbgAssert(!b, "stream already allocated"); + switch (dacp->config->dhrm) { + /* Sets the DAC data register */ + case DAC_DHRM_12BIT_RIGHT: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + break; + case DAC_DHRM_12BIT_LEFT: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + break; + case DAC_DHRM_8BIT_RIGHT: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + break; +#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2 + case DAC_DHRM_12BIT_RIGHT_DUAL: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + break; + case DAC_DHRM_12BIT_LEFT_DUAL: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + break; + case DAC_DHRM_8BIT_RIGHT_DUAL: + dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD); + dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; + break; +#endif + } - -<div class="clone-url " - data-protocol-type="subversion" - data-url="/users/set_protocol?protocol_selector=subversion&protocol_type=clone"> - <h3><strong>Subversion</strong> checkout URL</h3> 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-<span id="L342" rel="#L342">342</span> -<span id="L343" rel="#L343">343</span> -<span id="L344" rel="#L344">344</span> -<span id="L345" rel="#L345">345</span> -<span id="L346" rel="#L346">346</span> -<span id="L347" rel="#L347">347</span> -<span id="L348" rel="#L348">348</span> -<span id="L349" rel="#L349">349</span> -<span id="L350" rel="#L350">350</span> -<span id="L351" rel="#L351">351</span> - - </td> - <td class="blob-line-code"><div class="code-body highlight"><pre><div class='line' id='LC1'><span class="cm">/*</span></div><div class='line' id='LC2'><span class="cm"> ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,</span></div><div class='line' id='LC3'><span class="cm"> 2011,2012 Giovanni Di Sirio.</span></div><div class='line' id='LC4'><br/></div><div class='line' id='LC5'><span class="cm"> This file is part of ChibiOS/RT.</span></div><div class='line' id='LC6'><br/></div><div class='line' id='LC7'><span class="cm"> ChibiOS/RT is free software; you can redistribute it and/or modify</span></div><div class='line' id='LC8'><span class="cm"> it under the terms of the GNU General Public License as published by</span></div><div class='line' id='LC9'><span class="cm"> the Free Software Foundation; either version 3 of the License, or</span></div><div class='line' id='LC10'><span class="cm"> (at your option) any later version.</span></div><div class='line' id='LC11'><br/></div><div class='line' id='LC12'><span class="cm"> ChibiOS/RT is distributed in the hope that it will be useful,</span></div><div class='line' id='LC13'><span class="cm"> but WITHOUT ANY WARRANTY; without even the implied warranty of</span></div><div class='line' id='LC14'><span class="cm"> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span></div><div class='line' id='LC15'><span class="cm"> GNU General Public License for more details.</span></div><div class='line' id='LC16'><br/></div><div class='line' id='LC17'><span class="cm"> You should have received a copy of the GNU General Public License</span></div><div class='line' id='LC18'><span class="cm"> along with this program. If not, see <http://www.gnu.org/licenses/>.</span></div><div class='line' id='LC19'><span class="cm">*/</span></div><div class='line' id='LC20'><br/></div><div class='line' id='LC21'><span class="cm">/**</span></div><div class='line' id='LC22'><span class="cm"> * @file STM32/DACv1/dac_lld.c</span></div><div class='line' id='LC23'><span class="cm"> * @brief STM32 DAC subsystem low level driver source.</span></div><div class='line' id='LC24'><span class="cm"> *</span></div><div class='line' id='LC25'><span class="cm"> * @addtogroup DAC</span></div><div class='line' id='LC26'><span class="cm"> * @{</span></div><div class='line' id='LC27'><span class="cm"> */</span></div><div class='line' id='LC28'><br/></div><div class='line' id='LC29'><span class="cp">#include "hal.h"</span></div><div class='line' id='LC30'><br/></div><div class='line' id='LC31'><span class="cp">#if HAL_USE_DAC || defined(__DOXYGEN__)</span></div><div class='line' id='LC32'><br/></div><div class='line' id='LC33'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC34'><span class="cm">/* Driver local definitions. */</span></div><div class='line' id='LC35'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC36'><br/></div><div class='line' id='LC37'><span class="cp">#if !defined(DAC1)</span></div><div class='line' id='LC38'><span class="cp">#define DAC1 DAC</span></div><div class='line' id='LC39'><span class="cp">#define rccEnableDAC1 rccEnableDAC</span></div><div class='line' id='LC40'><span class="cp">#define rccDisableDAC1 rccDisableDAC</span></div><div class='line' id='LC41'><span class="cp">#endif</span></div><div class='line' id='LC42'><br/></div><div class='line' id='LC43'><span class="cp">#define DAC_CHN1_DMA_CHANNEL \</span></div><div class='line' id='LC44'><span class="cp"> STM32_DMA_GETCHANNEL(STM32_DAC_CHN1_DMA_STREAM, \</span></div><div class='line' id='LC45'><span class="cp"> STM32_DAC_CHN1_DMA_CHN)</span></div><div class='line' id='LC46'><br/></div><div class='line' id='LC47'><span class="cp">#define DAC_CHN2_DMA_CHANNEL \</span></div><div class='line' id='LC48'><span class="cp"> STM32_DMA_GETCHANNEL(STM32_DAC_CHN2_DMA_STREAM, \</span></div><div class='line' id='LC49'><span class="cp"> STM32_DAC_CHN2_DMA_CHN)</span></div><div class='line' id='LC50'><span class="cp"> </span></div><div class='line' id='LC51'><span class="cp">#define DAC_CHN3_DMA_CHANNEL \</span></div><div class='line' id='LC52'><span class="cp"> STM32_DMA_GETCHANNEL(STM32_DAC_CHN3_DMA_STREAM, \</span></div><div class='line' id='LC53'><span class="cp"> STM32_DAC_CHN3_DMA_CHN)</span></div><div class='line' id='LC54'><br/></div><div class='line' id='LC55'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC56'><span class="cm">/* Driver exported variables. */</span></div><div class='line' id='LC57'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC58'><br/></div><div class='line' id='LC59'><span class="cm">/** @brief CHN1 driver identifier.*/</span></div><div class='line' id='LC60'><span class="cp">#if STM32_DAC_USE_CHN1 || defined(__DOXYGEN__)</span></div><div class='line' id='LC61'><span class="n">DACDriver</span> <span class="n">DACD1</span><span class="p">;</span></div><div class='line' id='LC62'><span class="cp">#endif</span></div><div class='line' id='LC63'><br/></div><div class='line' id='LC64'><span class="cm">/** @brief CHN2 driver identifier.*/</span></div><div class='line' id='LC65'><span class="cp">#if STM32_DAC_USE_CHN2 || defined(__DOXYGEN__)</span></div><div class='line' id='LC66'><span class="n">DACDriver</span> <span class="n">DACD2</span><span class="p">;</span></div><div class='line' id='LC67'><span class="cp">#endif</span></div><div class='line' id='LC68'><br/></div><div class='line' id='LC69'><span class="cm">/** @brief CHN3 driver identifier.*/</span></div><div class='line' id='LC70'><span class="cp">#if STM32_DAC_USE_CHN3 || defined(__DOXYGEN__)</span></div><div class='line' id='LC71'><span class="n">DACDriver</span> <span class="n">DACD3</span><span class="p">;</span></div><div class='line' id='LC72'><span class="cp">#endif</span></div><div class='line' id='LC73'><br/></div><div class='line' id='LC74'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC75'><span class="cm">/* Driver local variables. */</span></div><div class='line' id='LC76'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC77'><br/></div><div class='line' id='LC78'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC79'><span class="cm">/* Driver local functions. */</span></div><div class='line' id='LC80'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC81'><br/></div><div class='line' id='LC82'><br/></div><div class='line' id='LC83'><span class="cm">/**</span></div><div class='line' id='LC84'><span class="cm"> * @brief Shared end/half-of-tx service routine.</span></div><div class='line' id='LC85'><span class="cm"> *</span></div><div class='line' id='LC86'><span class="cm"> * @param[in] dacp pointer to the @p DACDriver object</span></div><div class='line' id='LC87'><span class="cm"> * @param[in] flags pre-shifted content of the ISR register</span></div><div class='line' id='LC88'><span class="cm"> */</span></div><div class='line' id='LC89'><span class="k">static</span> <span class="kt">void</span> <span class="nf">dac_lld_serve_tx_interrupt</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">,</span> <span class="kt">uint32_t</span> <span class="n">flags</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC90'><span class="cp">#if defined(STM32_DAC_DMA_ERROR_HOOK)</span></div><div class='line' id='LC91'> <span class="p">(</span><span class="kt">void</span><span class="p">)</span><span class="n">dacp</span><span class="p">;</span></div><div class='line' id='LC92'> <span class="k">if</span> <span class="p">((</span><span class="n">flags</span> <span class="o">&</span> <span class="p">(</span><span class="n">STM32_DMA_ISR_TEIF</span> <span class="o">|</span> <span class="n">STM32_DMA_ISR_DMEIF</span><span class="p">))</span> <span class="o">!=</span> <span class="mi">0</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC93'> <span class="cm">/* DMA errors handling.*/</span></div><div class='line' id='LC94'> <span class="c1">//~ _dac_isr_error_code(dacp, flags);</span></div><div class='line' id='LC95'> <span class="p">}</span></div><div class='line' id='LC96'> <span class="k">else</span> <span class="p">{</span></div><div class='line' id='LC97'> <span class="k">if</span> <span class="p">((</span><span class="n">flags</span> <span class="o">&</span> <span class="n">STM32_DMA_ISR_HTIF</span><span class="p">)</span> <span class="o">!=</span> <span class="mi">0</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC98'> <span class="cm">/* Half transfer processing.*/</span></div><div class='line' id='LC99'> <span class="c1">//~ _dac_isr_half_code(dacp);</span></div><div class='line' id='LC100'> <span class="p">}</span></div><div class='line' id='LC101'> <span class="k">if</span> <span class="p">((</span><span class="n">flags</span> <span class="o">&</span> <span class="n">STM32_DMA_ISR_TCIF</span><span class="p">)</span> <span class="o">!=</span> <span class="mi">0</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC102'> <span class="cm">/* Transfer complete processing.*/</span></div><div class='line' id='LC103'> <span class="c1">//~ _dac_isr_full_code(dacp);</span></div><div class='line' id='LC104'> <span class="p">}</span></div><div class='line' id='LC105'> <span class="p">}</span></div><div class='line' id='LC106'><span class="cp">#else</span></div><div class='line' id='LC107'> <span class="p">(</span><span class="kt">void</span><span class="p">)</span><span class="n">dacp</span><span class="p">;</span></div><div class='line' id='LC108'> <span class="p">(</span><span class="kt">void</span><span class="p">)</span><span class="n">flags</span><span class="p">;</span></div><div class='line' id='LC109'><span class="cp">#endif</span></div><div class='line' id='LC110'><span class="p">}</span></div><div class='line' id='LC111'><br/></div><div class='line' id='LC112'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC113'><span class="cm">/* Driver interrupt handlers. */</span></div><div class='line' id='LC114'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC115'><br/></div><div class='line' id='LC116'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC117'><span class="cm">/* Driver exported functions. */</span></div><div class='line' id='LC118'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC119'><br/></div><div class='line' id='LC120'><span class="cm">/**</span></div><div class='line' id='LC121'><span class="cm"> * @brief Low level DAC driver initialization.</span></div><div class='line' id='LC122'><span class="cm"> *</span></div><div class='line' id='LC123'><span class="cm"> * @notapi</span></div><div class='line' id='LC124'><span class="cm"> */</span></div><div class='line' id='LC125'><span class="kt">void</span> <span class="nf">dac_lld_init</span><span class="p">(</span><span class="kt">void</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC126'><br/></div><div class='line' id='LC127'><span class="cp">#if STM32_DAC_USE_CHN1</span></div><div class='line' id='LC128'> <span class="n">dacObjectInit</span><span class="p">(</span><span class="o">&</span><span class="n">DACD1</span><span class="p">);</span></div><div class='line' id='LC129'> <span class="n">DACD1</span><span class="p">.</span><span class="n">dac</span> <span class="o">=</span> <span class="n">DAC1</span><span class="p">;</span></div><div class='line' id='LC130'> <span class="n">DACD1</span><span class="p">.</span><span class="n">tim</span> <span class="o">=</span> <span class="n">STM32_TIM6</span><span class="p">;</span></div><div class='line' id='LC131'> <span class="n">DACD1</span><span class="p">.</span><span class="n">irqprio</span> <span class="o">=</span> <span class="n">STM32_DAC_CHN1_IRQ_PRIORITY</span><span class="p">;</span></div><div class='line' id='LC132'> <span class="n">DACD1</span><span class="p">.</span><span class="n">dma</span> <span class="o">=</span> <span class="n">STM32_DMA_STREAM</span><span class="p">(</span><span class="n">STM32_DAC_CHN1_DMA_STREAM</span><span class="p">);</span></div><div class='line' id='LC133'> <span class="n">DACD1</span><span class="p">.</span><span class="n">dmamode</span> <span class="o">=</span> <span class="n">STM32_DMA_CR_CHSEL</span><span class="p">(</span><span class="n">DAC_CHN1_DMA_CHANNEL</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC134'> <span class="n">STM32_DMA_CR_PL</span><span class="p">(</span><span class="n">STM32_DAC_CHN1_DMA_PRIORITY</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC135'> <span class="n">STM32_DMA_CR_DIR_M2P</span> <span class="o">|</span> \</div><div class='line' id='LC136'> <span class="n">STM32_DMA_CR_DMEIE</span> <span class="o">|</span> \</div><div class='line' id='LC137'> <span class="n">STM32_DMA_CR_TEIE</span> <span class="o">|</span> \</div><div class='line' id='LC138'> <span class="n">STM32_DMA_CR_MINC</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_TCIE</span><span class="p">;</span></div><div class='line' id='LC139'><span class="cp">#endif</span></div><div class='line' id='LC140'><br/></div><div class='line' id='LC141'><span class="cp">#if STM32_DAC_USE_CHN2</span></div><div class='line' id='LC142'> <span class="n">dacObjectInit</span><span class="p">(</span><span class="o">&</span><span class="n">DACD2</span><span class="p">);</span></div><div class='line' id='LC143'> <span class="n">DACD2</span><span class="p">.</span><span class="n">dac</span> <span class="o">=</span> <span class="n">DAC1</span><span class="p">;</span></div><div class='line' id='LC144'> <span class="n">DACD2</span><span class="p">.</span><span class="n">tim</span> <span class="o">=</span> <span class="n">STM32_TIM7</span><span class="p">;</span></div><div class='line' id='LC145'> <span class="n">DACD2</span><span class="p">.</span><span class="n">irqprio</span> <span class="o">=</span> <span class="n">STM32_DAC_CHN2_IRQ_PRIORITY</span><span class="p">;</span></div><div class='line' id='LC146'> <span class="n">DACD2</span><span class="p">.</span><span class="n">dma</span> <span class="o">=</span> <span class="n">STM32_DMA_STREAM</span><span class="p">(</span><span class="n">STM32_DAC_CHN2_DMA_STREAM</span><span class="p">);</span></div><div class='line' id='LC147'> <span class="n">DACD2</span><span class="p">.</span><span class="n">dmamode</span> <span class="o">=</span> <span class="n">STM32_DMA_CR_CHSEL</span><span class="p">(</span><span class="n">DAC_CHN2_DMA_CHANNEL</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC148'> <span class="n">STM32_DMA_CR_PL</span><span class="p">(</span><span class="n">STM32_DAC_CHN2_DMA_PRIORITY</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC149'> <span class="n">STM32_DMA_CR_DIR_M2P</span> <span class="o">|</span> \</div><div class='line' id='LC150'> <span class="n">STM32_DMA_CR_DMEIE</span> <span class="o">|</span> \</div><div class='line' id='LC151'> <span class="n">STM32_DMA_CR_TEIE</span> <span class="o">|</span> \</div><div class='line' id='LC152'> <span class="n">STM32_DMA_CR_MINC</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_TCIE</span><span class="p">;</span></div><div class='line' id='LC153'><span class="cp">#endif</span></div><div class='line' id='LC154'><br/></div><div class='line' id='LC155'><span class="cp">#if STM32_DAC_USE_CHN3</span></div><div class='line' id='LC156'> <span class="n">dacObjectInit</span><span class="p">(</span><span class="o">&</span><span class="n">DACD3</span><span class="p">);</span></div><div class='line' id='LC157'> <span class="n">DACD3</span><span class="p">.</span><span class="n">dac</span> <span class="o">=</span> <span class="n">DAC2</span><span class="p">;</span></div><div class='line' id='LC158'> <span class="n">DACD3</span><span class="p">.</span><span class="n">tim</span> <span class="o">=</span> <span class="n">STM32_TIM18</span><span class="p">;</span></div><div class='line' id='LC159'> <span class="n">DACD3</span><span class="p">.</span><span class="n">irqprio</span> <span class="o">=</span> <span class="n">STM32_DAC_CHN3_IRQ_PRIORITY</span><span class="p">;</span></div><div class='line' id='LC160'> <span class="n">DACD3</span><span class="p">.</span><span class="n">dma</span> <span class="o">=</span> <span class="n">STM32_DMA_STREAM</span><span class="p">(</span><span class="n">STM32_DAC_CHN3_DMA_STREAM</span><span class="p">);</span></div><div class='line' id='LC161'> <span class="n">DACD3</span><span class="p">.</span><span class="n">dmamode</span> <span class="o">=</span> <span class="n">STM32_DMA_CR_CHSEL</span><span class="p">(</span><span class="n">DAC_CHN3_DMA_CHANNEL</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC162'> <span class="n">STM32_DMA_CR_PL</span><span class="p">(</span><span class="n">STM32_DAC_CHN2_DMA_PRIORITY</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC163'> <span class="n">STM32_DMA_CR_DIR_M2P</span> <span class="o">|</span> \</div><div class='line' id='LC164'> <span class="n">STM32_DMA_CR_DMEIE</span> <span class="o">|</span> \</div><div class='line' id='LC165'> <span class="n">STM32_DMA_CR_TEIE</span> <span class="o">|</span> \</div><div class='line' id='LC166'> <span class="n">STM32_DMA_CR_MINC</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_TCIE</span><span class="p">;</span></div><div class='line' id='LC167'><span class="cp">#endif</span></div><div class='line' id='LC168'><span class="p">}</span></div><div class='line' id='LC169'><br/></div><div class='line' id='LC170'><span class="cm">/**</span></div><div class='line' id='LC171'><span class="cm"> * @brief Configures and activates the DAC peripheral.</span></div><div class='line' id='LC172'><span class="cm"> *</span></div><div class='line' id='LC173'><span class="cm"> * @param[in] dacp pointer to the @p DACDriver object</span></div><div class='line' id='LC174'><span class="cm"> *</span></div><div class='line' id='LC175'><span class="cm"> * @notapi</span></div><div class='line' id='LC176'><span class="cm"> */</span></div><div class='line' id='LC177'><span class="kt">void</span> <span class="nf">dac_lld_start</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC178'> <span class="kt">uint32_t</span> <span class="n">arr</span><span class="p">,</span> <span class="n">regshift</span><span class="p">,</span> <span class="n">trgo</span><span class="p">,</span> <span class="n">dataoffset</span><span class="p">;</span></div><div class='line' id='LC179'> <span class="kt">bool</span> <span class="n">b</span><span class="p">;</span></div><div class='line' id='LC180'> <span class="cm">/* If in stopped state then enables the DAC and DMA clocks.*/</span></div><div class='line' id='LC181'> <span class="k">if</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">state</span> <span class="o">==</span> <span class="n">DAC_STOP</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC182'><span class="cp">#if STM32_DAC_USE_CHN1</span></div><div class='line' id='LC183'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD1</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC184'> <span class="n">rccEnableDAC1</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC185'> <span class="cm">/* DAC1 CR data is at bits 0:15 */</span></div><div class='line' id='LC186'> <span class="n">regshift</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span></div><div class='line' id='LC187'> <span class="n">dataoffset</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span></div><div class='line' id='LC188'> <span class="cm">/* Timer setup */</span></div><div class='line' id='LC189'> <span class="n">rccEnableTIM6</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC190'> <span class="n">rccResetTIM6</span><span class="p">();</span></div><div class='line' id='LC191'> <span class="n">trgo</span> <span class="o">=</span> <span class="n">STM32_DAC_CR_TSEL_TIM6</span><span class="p">;</span></div><div class='line' id='LC192'> <span class="p">}</span></div><div class='line' id='LC193'><span class="cp">#endif</span></div><div class='line' id='LC194'><span class="cp">#if STM32_DAC_USE_CHN2</span></div><div class='line' id='LC195'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD2</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC196'> <span class="n">rccEnableDAC1</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC197'> <span class="cm">/* DAC2 CR data is at bits 16:31 */</span></div><div class='line' id='LC198'> <span class="n">regshift</span> <span class="o">=</span> <span class="mi">16</span><span class="p">;</span></div><div class='line' id='LC199'> <span class="n">dataoffset</span> <span class="o">=</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12R2</span> <span class="o">-</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12R1</span><span class="p">;</span></div><div class='line' id='LC200'> <span class="cm">/* Timer setup */</span></div><div class='line' id='LC201'> <span class="n">rccEnableTIM7</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC202'> <span class="n">rccResetTIM7</span><span class="p">();</span></div><div class='line' id='LC203'> <span class="n">trgo</span> <span class="o">=</span> <span class="n">STM32_DAC_CR_TSEL_TIM7</span><span class="p">;</span></div><div class='line' id='LC204'> <span class="p">}</span></div><div class='line' id='LC205'><span class="cp">#endif</span></div><div class='line' id='LC206'><span class="cp">#if STM32_DAC_USE_CHN3</span></div><div class='line' id='LC207'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD3</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC208'> <span class="n">rccEnableDAC2</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC209'> <span class="cm">/* DAC3 CR data is at bits 0:15 */</span></div><div class='line' id='LC210'> <span class="n">regshift</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span></div><div class='line' id='LC211'> <span class="n">dataoffset</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span></div><div class='line' id='LC212'> <span class="cm">/* Timer setup */</span></div><div class='line' id='LC213'> <span class="n">rccEnableTIM18</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC214'> <span class="n">rccResetTIM18</span><span class="p">();</span></div><div class='line' id='LC215'> <span class="n">trgo</span> <span class="o">=</span> <span class="n">STM32_DAC_CR_TSEL_TIM18</span><span class="p">;</span></div><div class='line' id='LC216'> <span class="p">}</span></div><div class='line' id='LC217'><span class="cp">#endif</span></div><div class='line' id='LC218'><span class="cp">#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3</span></div><div class='line' id='LC219'> <span class="n">dacp</span><span class="o">-></span><span class="n">clock</span> <span class="o">=</span> <span class="n">STM32_TIMCLK1</span><span class="p">;</span></div><div class='line' id='LC220'> <span class="n">arr</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">clock</span> <span class="o">/</span> <span class="n">dacp</span><span class="o">-></span><span class="n">config</span><span class="o">-></span><span class="n">frequency</span><span class="p">);</span></div><div class='line' id='LC221'> <span class="n">osalDbgAssert</span><span class="p">((</span><span class="n">arr</span> <span class="o"><=</span> <span class="mh">0xFFFF</span><span class="p">),</span></div><div class='line' id='LC222'> <span class="s">"invalid frequency"</span><span class="p">);</span></div><div class='line' id='LC223'><br/></div><div class='line' id='LC224'> <span class="cm">/* Timer configuration.*/</span></div><div class='line' id='LC225'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CR1</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="cm">/* Initially stopped. */</span></div><div class='line' id='LC226'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">PSC</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="cm">/* Prescaler value. */</span></div><div class='line' id='LC227'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">DIER</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span></div><div class='line' id='LC228'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">ARR</span> <span class="o">=</span> <span class="n">arr</span><span class="p">;</span></div><div class='line' id='LC229'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">EGR</span> <span class="o">=</span> <span class="n">TIM_EGR_UG</span><span class="p">;</span> <span class="cm">/* Update event. */</span></div><div class='line' id='LC230'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CR2</span> <span class="o">&=</span> <span class="p">(</span><span class="kt">uint16_t</span><span class="p">)</span><span class="o">~</span><span class="n">TIM_CR2_MMS</span><span class="p">;</span></div><div class='line' id='LC231'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CR2</span> <span class="o">|=</span> <span class="p">(</span><span class="kt">uint16_t</span><span class="p">)</span><span class="n">TIM_CR2_MMS_1</span><span class="p">;</span> <span class="cm">/* Enable TRGO updates. */</span></div><div class='line' id='LC232'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CNT</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="cm">/* Reset counter. */</span></div><div class='line' id='LC233'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">SR</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="cm">/* Clear pending IRQs. */</span></div><div class='line' id='LC234'> <span class="cm">/* Update Event IRQ enabled. */</span></div><div class='line' id='LC235'> <span class="cm">/* Timer start.*/</span></div><div class='line' id='LC236'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CR1</span> <span class="o">=</span> <span class="n">TIM_CR1_CEN</span><span class="p">;</span></div><div class='line' id='LC237'><br/></div><div class='line' id='LC238'> <span class="cm">/* DAC configuration */</span></div><div class='line' id='LC239'> <span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">|=</span> <span class="p">(</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DAC_CR_MASK</span><span class="p">)</span> <span class="o">|</span> \</div><div class='line' id='LC240'> <span class="p">(</span><span class="n">STM32_DAC_CR_EN</span> <span class="o">|</span> <span class="n">STM32_DAC_CR_DMAEN</span> <span class="o">|</span> <span class="n">dacp</span><span class="o">-></span><span class="n">config</span><span class="o">-></span><span class="n">cr_flags</span><span class="p">)</span> <span class="p">)</span> <span class="o"><<</span> <span class="n">regshift</span><span class="p">;</span></div><div class='line' id='LC241'> </div><div class='line' id='LC242'> <span class="cm">/* DMA setup. */</span></div><div class='line' id='LC243'> <span class="n">b</span> <span class="o">=</span> <span class="n">dmaStreamAllocate</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span></div><div class='line' id='LC244'> <span class="n">dacp</span><span class="o">-></span><span class="n">irqprio</span><span class="p">,</span></div><div class='line' id='LC245'> <span class="p">(</span><span class="kt">stm32_dmaisr_t</span><span class="p">)</span><span class="n">dac_lld_serve_tx_interrupt</span><span class="p">,</span></div><div class='line' id='LC246'> <span class="p">(</span><span class="kt">void</span> <span class="o">*</span><span class="p">)</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC247'> <span class="n">osalDbgAssert</span><span class="p">(</span><span class="o">!</span><span class="n">b</span><span class="p">,</span> <span class="s">"stream already allocated"</span><span class="p">);</span></div><div class='line' id='LC248'> <span class="k">switch</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">config</span><span class="o">-></span><span class="n">dhrm</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC249'> <span class="cm">/* Sets the DAC data register */</span></div><div class='line' id='LC250'> <span class="k">case</span> <span class="n">DAC_DHRM_12BIT_RIGHT</span>:</div><div class='line' id='LC251'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12R1</span> <span class="o">+</span> <span class="n">dataoffset</span><span class="p">);</span></div><div class='line' id='LC252'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC253'> <span class="n">STM32_DMA_CR_PSIZE_HWORD</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_HWORD</span><span class="p">;</span></div><div class='line' id='LC254'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC255'> <span class="k">case</span> <span class="n">DAC_DHRM_12BIT_LEFT</span>:</div><div class='line' id='LC256'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12L1</span> <span class="o">+</span> <span class="n">dataoffset</span><span class="p">);</span></div><div class='line' id='LC257'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC258'> <span class="n">STM32_DMA_CR_PSIZE_HWORD</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_HWORD</span><span class="p">;</span></div><div class='line' id='LC259'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC260'> <span class="k">case</span> <span class="n">DAC_DHRM_8BIT_RIGHT</span>:</div><div class='line' id='LC261'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR8R1</span> <span class="o">+</span> <span class="n">dataoffset</span><span class="p">);</span></div><div class='line' id='LC262'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC263'> <span class="n">STM32_DMA_CR_PSIZE_BYTE</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_BYTE</span><span class="p">;</span></div><div class='line' id='LC264'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC265'><span class="cp">#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2</span></div><div class='line' id='LC266'> <span class="k">case</span> <span class="n">DAC_DHRM_12BIT_RIGHT_DUAL</span>:</div><div class='line' id='LC267'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12RD</span><span class="p">);</span></div><div class='line' id='LC268'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC269'> <span class="n">STM32_DMA_CR_PSIZE_HWORD</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_HWORD</span><span class="p">;</span></div><div class='line' id='LC270'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC271'> <span class="k">case</span> <span class="n">DAC_DHRM_12BIT_LEFT_DUAL</span>:</div><div class='line' id='LC272'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR12LD</span><span class="p">);</span></div><div class='line' id='LC273'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC274'> <span class="n">STM32_DMA_CR_PSIZE_HWORD</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_HWORD</span><span class="p">;</span></div><div class='line' id='LC275'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC276'> <span class="k">case</span> <span class="n">DAC_DHRM_8BIT_RIGHT_DUAL</span>:</div><div class='line' id='LC277'> <span class="n">dmaStreamSetPeripheral</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="o">&</span><span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">DHR8RD</span><span class="p">);</span></div><div class='line' id='LC278'> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">=</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">&</span> <span class="o">~</span><span class="n">STM32_DMA_CR_SIZE_MASK</span><span class="p">)</span> <span class="o">|</span></div><div class='line' id='LC279'> <span class="n">STM32_DMA_CR_PSIZE_BYTE</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_MSIZE_BYTE</span><span class="p">;</span></div><div class='line' id='LC280'> <span class="k">break</span><span class="p">;</span></div><div class='line' id='LC281'><span class="cp">#endif</span></div><div class='line' id='LC282'> <span class="p">}</span></div><div class='line' id='LC283'> </div><div class='line' id='LC284'> <span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">|=</span> <span class="n">trgo</span> <span class="o"><<</span> <span class="n">regshift</span><span class="p">;</span> <span class="cm">/* Enable timer trigger */</span></div><div class='line' id='LC285'><span class="cp">#endif</span></div><div class='line' id='LC286'> <span class="p">}</span></div><div class='line' id='LC287'><span class="p">}</span></div><div class='line' id='LC288'><br/></div><div class='line' id='LC289'><span class="cm">/**</span></div><div class='line' id='LC290'><span class="cm"> * @brief Deactivates the DAC peripheral.</span></div><div class='line' id='LC291'><span class="cm"> *</span></div><div class='line' id='LC292'><span class="cm"> * @param[in] dacp pointer to the @p DACDriver object</span></div><div class='line' id='LC293'><span class="cm"> *</span></div><div class='line' id='LC294'><span class="cm"> * @notapi</span></div><div class='line' id='LC295'><span class="cm"> */</span></div><div class='line' id='LC296'><span class="kt">void</span> <span class="nf">dac_lld_stop</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC297'><br/></div><div class='line' id='LC298'> <span class="cm">/* If in ready state then disables the DAC clock.*/</span></div><div class='line' id='LC299'> <span class="k">if</span> <span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">state</span> <span class="o">==</span> <span class="n">DAC_READY</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC300'><br/></div><div class='line' id='LC301'> <span class="cm">/* DMA disable.*/</span></div><div class='line' id='LC302'> <span class="n">dmaStreamRelease</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">);</span></div><div class='line' id='LC303'><br/></div><div class='line' id='LC304'><span class="cp">#if STM32_DAC_USE_CHN1</span></div><div class='line' id='LC305'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD1</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC306'> <span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">&=</span> <span class="o">~</span><span class="n">STM32_DAC_CR_EN</span><span class="p">;</span> <span class="cm">/* DAC1 disable.*/</span></div><div class='line' id='LC307'> <span class="p">}</span></div><div class='line' id='LC308'><span class="cp">#endif</span></div><div class='line' id='LC309'><span class="cp">#if STM32_DAC_USE_CHN2</span></div><div class='line' id='LC310'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD2</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC311'> <span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">&=</span> <span class="o">~</span><span class="n">STM32_DAC_CR_EN</span> <span class="o"><<</span> <span class="mi">16</span><span class="p">;</span> <span class="cm">/* DAC1 disable.*/</span></div><div class='line' id='LC312'> <span class="p">}</span></div><div class='line' id='LC313'><span class="cp">#endif</span></div><div class='line' id='LC314'><span class="cp">#if STM32_DAC_USE_CHN3</span></div><div class='line' id='LC315'> <span class="k">if</span> <span class="p">(</span><span class="o">&</span><span class="n">DACD3</span> <span class="o">==</span> <span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC316'> <span class="n">dacp</span><span class="o">-></span><span class="n">dac</span><span class="o">-></span><span class="n">CR</span> <span class="o">&=</span> <span class="o">~</span><span class="n">STM32_DAC_CR_EN</span><span class="p">;</span> <span class="cm">/* DAC2 disable.*/</span></div><div class='line' id='LC317'> <span class="n">rccDisableDAC2</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span> <span class="cm">/* DAC Clock disable.*/</span></div><div class='line' id='LC318'> <span class="p">}</span></div><div class='line' id='LC319'><span class="cp">#endif</span></div><div class='line' id='LC320'> <span class="n">dacp</span><span class="o">-></span><span class="n">tim</span><span class="o">-></span><span class="n">CR1</span> <span class="o">&=</span> <span class="o">~</span><span class="n">TIM_CR1_CEN</span><span class="p">;</span> <span class="cm">/* Disable associated timer */</span></div><div class='line' id='LC321'> <span class="n">dacp</span><span class="o">-></span><span class="n">state</span> <span class="o">=</span> <span class="n">DAC_STOP</span><span class="p">;</span></div><div class='line' id='LC322'><br/></div><div class='line' id='LC323'> <span class="k">if</span> <span class="p">(</span><span class="o">!</span><span class="p">(</span><span class="n">DAC1</span><span class="o">-></span><span class="n">CR</span> <span class="o">&</span> <span class="p">(</span><span class="n">STM32_DAC_CR_EN</span> <span class="o">|</span> <span class="n">STM32_DAC_CR_EN</span> <span class="o"><<</span> <span class="mi">16</span><span class="p">)))</span> <span class="p">{</span></div><div class='line' id='LC324'> <span class="cm">/* DAC Clock disable only if all channels are off.*/</span></div><div class='line' id='LC325'> <span class="n">rccDisableDAC1</span><span class="p">(</span><span class="n">FALSE</span><span class="p">);</span></div><div class='line' id='LC326'> <span class="p">}</span></div><div class='line' id='LC327'> <span class="p">}</span></div><div class='line' id='LC328'><span class="p">}</span></div><div class='line' id='LC329'><br/></div><div class='line' id='LC330'><span class="cm">/**</span></div><div class='line' id='LC331'><span class="cm"> * @brief Sends data over the DAC bus.</span></div><div class='line' id='LC332'><span class="cm"> * @details This asynchronous function starts a transmit operation.</span></div><div class='line' id='LC333'><span class="cm"> * @post At the end of the operation the configured callback is invoked.</span></div><div class='line' id='LC334'><span class="cm"> *</span></div><div class='line' id='LC335'><span class="cm"> * @param[in] dacp pointer to the @p DACDriver object</span></div><div class='line' id='LC336'><span class="cm"> * @param[in] n number of words to send</span></div><div class='line' id='LC337'><span class="cm"> * @param[in] txbuf the pointer to the transmit buffer</span></div><div class='line' id='LC338'><span class="cm"> *</span></div><div class='line' id='LC339'><span class="cm"> * @notapi</span></div><div class='line' id='LC340'><span class="cm"> */</span></div><div class='line' id='LC341'><span class="kt">void</span> <span class="nf">dac_lld_start_conversion</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">)</span> <span class="p">{</span></div><div class='line' id='LC342'> <span class="n">osalDbgAssert</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">samples</span><span class="p">,</span> </div><div class='line' id='LC343'> <span class="s">"dacp->samples is NULL pointer"</span><span class="p">);</span></div><div class='line' id='LC344'> <span class="n">dmaStreamSetMemory0</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="n">dacp</span><span class="o">-></span><span class="n">samples</span><span class="p">);</span></div><div class='line' id='LC345'> <span class="n">dmaStreamSetTransactionSize</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="n">dacp</span><span class="o">-></span><span class="n">depth</span><span class="p">);</span></div><div class='line' id='LC346'> <span class="n">dmaStreamSetMode</span><span class="p">(</span><span class="n">dacp</span><span class="o">-></span><span class="n">dma</span><span class="p">,</span> <span class="n">dacp</span><span class="o">-></span><span class="n">dmamode</span> <span class="o">|</span> <span class="n">STM32_DMA_CR_EN</span> <span class="o">|</span></div><div class='line' id='LC347'> <span class="n">STM32_DMA_CR_CIRC</span><span class="p">);</span></div><div class='line' id='LC348'><span class="p">}</span></div><div class='line' id='LC349'><span class="cp">#endif </span><span class="cm">/* HAL_USE_DAC */</span><span class="cp"></span></div><div class='line' id='LC350'><br/></div><div class='line' id='LC351'><span class="cm">/** @} */</span></div></pre></div></td> - </tr> - </table> - </div> - - </div> -</div> - -<a href="#jump-to-line" rel="facebox[.linejump]" data-hotkey="l" class="js-jump-to-line" style="display:none">Jump to Line</a> -<div id="jump-to-line" style="display:none"> - <form accept-charset="UTF-8" class="js-jump-to-line-form"> - <input class="linejump-input js-jump-to-line-field" type="text" placeholder="Jump to line…" autofocus> - <button type="submit" class="button">Go</button> - </form> -</div> - - </div> - - </div><!-- /.repo-container --> - <div class="modal-backdrop"></div> - </div><!-- /.container --> - </div><!-- /.site --> - - - </div><!-- /.wrapper --> - - <div class="container"> - <div class="site-footer"> - <ul class="site-footer-links right"> - <li><a href="https://status.github.com/">Status</a></li> - <li><a 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Please try again. - </div> - - </body> -</html> - + dacp->dac->CR |= trgo << regshift; /* Enable timer trigger */ +#endif + } +} + +/** + * @brief Deactivates the DAC peripheral. + * + * @param[in] dacp pointer to the @p DACDriver object + * + * @notapi + */ +void dac_lld_stop(DACDriver *dacp) { + + /* If in ready state then disables the DAC clock.*/ + if (dacp->state == DAC_READY) { + + /* DMA disable.*/ + dmaStreamRelease(dacp->dma); + +#if STM32_DAC_USE_CHN1 + if (&DACD1 == dacp) { + dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/ + } +#endif +#if STM32_DAC_USE_CHN2 + if (&DACD2 == dacp) { + dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/ + } +#endif +#if STM32_DAC_USE_CHN3 + if (&DACD3 == dacp) { + dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/ + rccDisableDAC2(FALSE); /* DAC Clock disable.*/ + } +#endif + dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */ + dacp->state = DAC_STOP; + + if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) { + /* DAC Clock disable only if all channels are off.*/ + rccDisableDAC1(FALSE); + } + } +} + +/** + * @brief Sends data over the DAC bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] dacp pointer to the @p DACDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void dac_lld_start_conversion(DACDriver *dacp) { + osalDbgAssert(dacp->samples, + "dacp->samples is NULL pointer"); + dmaStreamSetMemory0(dacp->dma, dacp->samples); + dmaStreamSetTransactionSize(dacp->dma, dacp->depth); + dmaStreamSetMode(dacp->dma, dacp->dmamode | STM32_DMA_CR_EN | + STM32_DMA_CR_CIRC); +} +#endif /* HAL_USE_DAC */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h index 6fe873faa..0df5cc8cc 100644 --- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h +++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h @@ -1,2416 +1,397 @@ - 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rel="nofollow"> - <span class="octicon octicon-cloud-download"></span> - Download ZIP - </a> - </div> - </div><!-- /.repository-sidebar --> - - <div id="js-repo-pjax-container" class="repository-content context-loader-container" data-pjax-container> - - - -<!-- blob contrib key: blob_contributors:v21:58e24ef2ddff1b1c802b22a8bc249e54 --> - -<p title="This is a placeholder element" class="js-history-link-replace hidden"></p> - -<a href="/mobyfab/ChibiOS/find/dac-3.0" data-pjax data-hotkey="t" class="js-show-file-finder" style="display:none">Show File Finder</a> - -<div class="file-navigation"> +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +/** + * @file STM32/DACv1/dac_lld.h + * @brief STM32 DAC subsystem low level driver header. + * + * @addtogroup DAC + * @{ + */ + +#ifndef _DAC_LLD_H_ +#define _DAC_LLD_H_ + +#include "stm32_tim.h" + +#if HAL_USE_DAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define STM32_DAC_CR_EN DAC_CR_EN1 +#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1 +#define STM32_DAC_CR_TEN DAC_CR_TEN1 + +#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE + +#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000 +#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1 + +#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000 +#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2 +#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2 +#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 +#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1 +#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1 +#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0 +#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1 +#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2 +#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2 + +#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000 +#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0 +#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1 + +#define STM32_DAC_MAMP_1 (uint32_t)0x00000000 +#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0 +#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1 +#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 +#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2 +#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2 +#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2 +#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2 +#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3 +#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3 +#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3 +#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief DAC CHN1 driver enable switch. + * @details If set to @p TRUE the support for DAC CHN1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__) +#define STM32_DAC_USE_CHN1 FALSE +#endif + +/** + * @brief DAC CHN2 driver enable switch. + * @details If set to @p TRUE the support for DAC CHN2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__) +#define STM32_DAC_USE_CHN2 FALSE +#endif + +/** + * @brief DAC CHN3 driver enable switch. + * @details If set to @p TRUE the support for DAC CHN3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__) +#define STM32_DAC_USE_CHN3 FALSE +#endif + +/** + * @brief DAC CHN1 interrupt priority level setting. + */ +#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN1_IRQ_PRIORITY 10 +#endif + +/** + * @brief DAC CHN2 interrupt priority level setting. + */ +#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN2_IRQ_PRIORITY 10 +#endif + +/** + * @brief DAC CHN3 interrupt priority level setting. + */ +#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN3_IRQ_PRIORITY 10 +#endif + +/** + * @brief DAC CHN1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN1_DMA_PRIORITY 2 +#endif + +/** + * @brief DAC CHN2 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN2_DMA_PRIORITY 2 +#endif + +/** + * @brief DAC CHN3 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_DAC_CHN2_DMA_PRIORITY 2 +#endif + +/** + * @brief DAC DMA error hook. + */ +#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt() +#endif + +/** + * @brief DMA stream used for DAC CHN1 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#endif + +/** + * @brief DMA stream used for DAC CHN2 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#endif + +/** + * @brief DMA stream used for DAC CHN3 TX operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1 +#error "DAC CHN1 not present in the selected device" +#endif + +#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2 +#error "DAC CHN2 not present in the selected device" +#endif + +#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3 +#error "DAC CHN3 not present in the selected device" +#endif + +#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3 +#error "DAC driver activated but no DAC peripheral assigned" +#endif + +#if STM32_DAC_USE_CHN1 && \ + !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK) +#error "invalid DMA stream associated to DAC CHN1" +#endif + +#if STM32_DAC_USE_CHN2 && \ + !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK) +#error "invalid DMA stream associated to DAC CHN2" +#endif + +#if STM32_DAC_USE_CHN3 && \ + !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK) +#error "invalid DMA stream associated to DAC CHN3" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an DAC driver. + */ +typedef struct DACDriver DACDriver; + +/** + * @brief Type representing a DAC sample. + */ +typedef uint16_t dacsample_t; + +/** + * @brief DAC notification callback type. + * + * @param[in] dacp pointer to the @p DACDriver object triggering the + * callback + */ +typedef void (*daccallback_t)(DACDriver *dacp); + +typedef enum { + DAC_DHRM_12BIT_RIGHT = 0, + DAC_DHRM_12BIT_LEFT = 1, + DAC_DHRM_8BIT_RIGHT = 2, +#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__) + DAC_DHRM_12BIT_RIGHT_DUAL = 3, + DAC_DHRM_12BIT_LEFT_DUAL = 4, + DAC_DHRM_8BIT_RIGHT_DUAL = 5 +#endif +} dacdhrmode_t; + +/** + * @brief DAC Conversion group structure. + */ +typedef struct { + /** + * @brief Number of DAC channels. + */ + uint16_t num_channels; + /** + * @brief Operation complete callback or @p NULL. + */ + daccallback_t end_cb; + /** + * @brief Error handling callback or @p NULL. + */ + daccallback_t error_cb; - -<div class="select-menu js-menu-container js-select-menu" > - <span class="minibutton select-menu-button js-menu-target" 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rel="#L387">387</span> -<span id="L388" rel="#L388">388</span> -<span id="L389" rel="#L389">389</span> -<span id="L390" rel="#L390">390</span> -<span id="L391" rel="#L391">391</span> -<span id="L392" rel="#L392">392</span> -<span id="L393" rel="#L393">393</span> -<span id="L394" rel="#L394">394</span> -<span id="L395" rel="#L395">395</span> -<span id="L396" rel="#L396">396</span> -<span id="L397" rel="#L397">397</span> - - </td> - <td class="blob-line-code"><div class="code-body highlight"><pre><div class='line' id='LC1'><span class="cm">/*</span></div><div class='line' id='LC2'><span class="cm"> ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,</span></div><div class='line' id='LC3'><span class="cm"> 2011,2012 Giovanni Di Sirio.</span></div><div class='line' id='LC4'><br/></div><div class='line' id='LC5'><span class="cm"> This file is part of ChibiOS/RT.</span></div><div class='line' id='LC6'><br/></div><div class='line' id='LC7'><span class="cm"> ChibiOS/RT is free software; you can redistribute it and/or modify</span></div><div class='line' id='LC8'><span class="cm"> it under the terms of the GNU General Public License as published by</span></div><div class='line' id='LC9'><span class="cm"> the Free Software Foundation; either version 3 of the License, or</span></div><div class='line' id='LC10'><span class="cm"> (at your option) any later version.</span></div><div class='line' id='LC11'><br/></div><div class='line' id='LC12'><span class="cm"> ChibiOS/RT is distributed in the hope that it will be useful,</span></div><div class='line' id='LC13'><span class="cm"> but WITHOUT ANY WARRANTY; without even the implied warranty of</span></div><div class='line' id='LC14'><span class="cm"> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span></div><div class='line' id='LC15'><span class="cm"> GNU General Public License for more details.</span></div><div class='line' id='LC16'><br/></div><div class='line' id='LC17'><span class="cm"> You should have received a copy of the GNU General Public License</span></div><div class='line' id='LC18'><span class="cm"> along with this program. If not, see <http://www.gnu.org/licenses/>.</span></div><div class='line' id='LC19'><span class="cm">*/</span></div><div class='line' id='LC20'><br/></div><div class='line' id='LC21'><span class="cm">/**</span></div><div class='line' id='LC22'><span class="cm"> * @file STM32/DACv1/dac_lld.h</span></div><div class='line' id='LC23'><span class="cm"> * @brief STM32 DAC subsystem low level driver header.</span></div><div class='line' id='LC24'><span class="cm"> *</span></div><div class='line' id='LC25'><span class="cm"> * @addtogroup DAC</span></div><div class='line' id='LC26'><span class="cm"> * @{</span></div><div class='line' id='LC27'><span class="cm"> */</span></div><div class='line' id='LC28'><br/></div><div class='line' id='LC29'><span class="cp">#ifndef _DAC_LLD_H_</span></div><div class='line' id='LC30'><span class="cp">#define _DAC_LLD_H_</span></div><div class='line' id='LC31'><br/></div><div class='line' id='LC32'><span class="cp">#include "stm32_tim.h"</span></div><div class='line' id='LC33'><br/></div><div class='line' id='LC34'><span class="cp">#if HAL_USE_DAC || defined(__DOXYGEN__)</span></div><div class='line' id='LC35'><br/></div><div class='line' id='LC36'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC37'><span class="cm">/* Driver constants. */</span></div><div class='line' id='LC38'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC39'><br/></div><div class='line' id='LC40'><span class="cp">#define STM32_DAC_CR_EN DAC_CR_EN1</span></div><div class='line' id='LC41'><span class="cp">#define STM32_DAC_CR_DMAEN DAC_CR_DMAEN1</span></div><div class='line' id='LC42'><span class="cp">#define STM32_DAC_CR_TEN DAC_CR_TEN1</span></div><div class='line' id='LC43'><br/></div><div class='line' id='LC44'><span class="cp">#define STM32_DAC_CR_MASK (uint32_t)0x00000FFE</span></div><div class='line' id='LC45'><br/></div><div class='line' id='LC46'><span class="cp">#define STM32_DAC_CR_BOFF_ENABLE (uint32_t)0x00000000</span></div><div class='line' id='LC47'><span class="cp">#define STM32_DAC_CR_BOFF_DISABLE DAC_CR_BOFF1</span></div><div class='line' id='LC48'><br/></div><div class='line' id='LC49'><span class="cp">#define STM32_DAC_CR_TSEL_NONE (uint32_t)0x00000000</span></div><div class='line' id='LC50'><span class="cp">#define STM32_DAC_CR_TSEL_TIM2 DAC_CR_TEN1 | DAC_CR_TSEL1_2</span></div><div class='line' id='LC51'><span class="cp">#define STM32_DAC_CR_TSEL_TIM4 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_2</span></div><div class='line' id='LC52'><span class="cp">#define STM32_DAC_CR_TSEL_TIM5 DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1</span></div><div class='line' id='LC53'><span class="cp">#define STM32_DAC_CR_TSEL_TIM6 DAC_CR_TEN1</span></div><div class='line' id='LC54'><span class="cp">#define STM32_DAC_CR_TSEL_TIM7 DAC_CR_TEN1 | DAC_CR_TSEL1_1</span></div><div class='line' id='LC55'><span class="cp">#define STM32_DAC_CR_TSEL_TIM3 DAC_CR_TEN1 | DAC_CR_TSEL1_0</span></div><div class='line' id='LC56'><span class="cp">#define STM32_DAC_CR_TSEL_TIM18 DAC_CR_TEN1 | DAC_CR_TSEL1_0 | DAC_CR_TSEL1_1</span></div><div class='line' id='LC57'><span class="cp">#define STM32_DAC_CR_TSEL_EXT_IT9 DAC_CR_TEN1 | DAC_CR_TEN1 | DAC_CR_TSEL1_2</span></div><div class='line' id='LC58'><span class="cp">#define STM32_DAC_CR_TSEL_SOFT DAC_CR_TEN1 | DAC_CR_TEN0 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_2</span></div><div class='line' id='LC59'><br/></div><div class='line' id='LC60'><span class="cp">#define STM32_DAC_CR_WAVE_NONE (uint32_t)0x00000000</span></div><div class='line' id='LC61'><span class="cp">#define STM32_DAC_CR_WAVE_NOISE DAC_CR_WAVE1_0</span></div><div class='line' id='LC62'><span class="cp">#define STM32_DAC_CR_WAVE_TRIANGLE DAC_CR_WAVE1_1</span></div><div class='line' id='LC63'><br/></div><div class='line' id='LC64'><span class="cp">#define STM32_DAC_MAMP_1 (uint32_t)0x00000000</span></div><div class='line' id='LC65'><span class="cp">#define STM32_DAC_MAMP_3 DAC_CR_MAMP1_0</span></div><div class='line' id='LC66'><span class="cp">#define STM32_DAC_MAMP_7 DAC_CR_MAMP1_1</span></div><div class='line' id='LC67'><span class="cp">#define STM32_DAC_MAMP_15 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1</span></div><div class='line' id='LC68'><span class="cp">#define STM32_DAC_MAMP_31 DAC_CR_MAMP1_2</span></div><div class='line' id='LC69'><span class="cp">#define STM32_DAC_MAMP_63 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_2</span></div><div class='line' id='LC70'><span class="cp">#define STM32_DAC_MAMP_127 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2</span></div><div class='line' id='LC71'><span class="cp">#define STM32_DAC_MAMP_255 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2</span></div><div class='line' id='LC72'><span class="cp">#define STM32_DAC_MAMP_511 DAC_CR_MAMP1_3</span></div><div class='line' id='LC73'><span class="cp">#define STM32_DAC_MAMP_1023 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_3</span></div><div class='line' id='LC74'><span class="cp">#define STM32_DAC_MAMP_2047 DAC_CR_MAMP1_1 | DAC_CR_MAMP1_3</span></div><div class='line' id='LC75'><span class="cp">#define STM32_DAC_MAMP_4095 DAC_CR_MAMP1_0 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_2</span></div><div class='line' id='LC76'><br/></div><div class='line' id='LC77'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC78'><span class="cm">/* Driver pre-compile time settings. */</span></div><div class='line' id='LC79'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC80'><br/></div><div class='line' id='LC81'><span class="cm">/**</span></div><div class='line' id='LC82'><span class="cm"> * @name Configuration options</span></div><div class='line' id='LC83'><span class="cm"> * @{</span></div><div class='line' id='LC84'><span class="cm"> */</span></div><div class='line' id='LC85'><span class="cm">/**</span></div><div class='line' id='LC86'><span class="cm"> * @brief DAC CHN1 driver enable switch.</span></div><div class='line' id='LC87'><span class="cm"> * @details If set to @p TRUE the support for DAC CHN1 is included.</span></div><div class='line' id='LC88'><span class="cm"> * @note The default is @p TRUE.</span></div><div class='line' id='LC89'><span class="cm"> */</span></div><div class='line' id='LC90'><span class="cp">#if !defined(STM32_DAC_USE_CHN1) || defined(__DOXYGEN__)</span></div><div class='line' id='LC91'><span class="cp">#define STM32_DAC_USE_CHN1 FALSE</span></div><div class='line' id='LC92'><span class="cp">#endif</span></div><div class='line' id='LC93'><br/></div><div class='line' id='LC94'><span class="cm">/**</span></div><div class='line' id='LC95'><span class="cm"> * @brief DAC CHN2 driver enable switch.</span></div><div class='line' id='LC96'><span class="cm"> * @details If set to @p TRUE the support for DAC CHN2 is included.</span></div><div class='line' id='LC97'><span class="cm"> * @note The default is @p TRUE.</span></div><div class='line' id='LC98'><span class="cm"> */</span></div><div class='line' id='LC99'><span class="cp">#if !defined(STM32_DAC_USE_CHN2) || defined(__DOXYGEN__)</span></div><div class='line' id='LC100'><span class="cp">#define STM32_DAC_USE_CHN2 FALSE</span></div><div class='line' id='LC101'><span class="cp">#endif</span></div><div class='line' id='LC102'><br/></div><div class='line' id='LC103'><span class="cm">/**</span></div><div class='line' id='LC104'><span class="cm"> * @brief DAC CHN3 driver enable switch.</span></div><div class='line' id='LC105'><span class="cm"> * @details If set to @p TRUE the support for DAC CHN3 is included.</span></div><div class='line' id='LC106'><span class="cm"> * @note The default is @p TRUE.</span></div><div class='line' id='LC107'><span class="cm"> */</span></div><div class='line' id='LC108'><span class="cp">#if !defined(STM32_DAC_USE_CHN3) || defined(__DOXYGEN__)</span></div><div class='line' id='LC109'><span class="cp">#define STM32_DAC_USE_CHN3 FALSE</span></div><div class='line' id='LC110'><span class="cp">#endif</span></div><div class='line' id='LC111'><br/></div><div class='line' id='LC112'><span class="cm">/**</span></div><div class='line' id='LC113'><span class="cm"> * @brief DAC CHN1 interrupt priority level setting.</span></div><div class='line' id='LC114'><span class="cm"> */</span></div><div class='line' id='LC115'><span class="cp">#if !defined(STM32_DAC_CHN1_IRQ_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC116'><span class="cp">#define STM32_DAC_CHN1_IRQ_PRIORITY 10</span></div><div class='line' id='LC117'><span class="cp">#endif</span></div><div class='line' id='LC118'><br/></div><div class='line' id='LC119'><span class="cm">/**</span></div><div class='line' id='LC120'><span class="cm"> * @brief DAC CHN2 interrupt priority level setting.</span></div><div class='line' id='LC121'><span class="cm"> */</span></div><div class='line' id='LC122'><span class="cp">#if !defined(STM32_DAC_CHN2_IRQ_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC123'><span class="cp">#define STM32_DAC_CHN2_IRQ_PRIORITY 10</span></div><div class='line' id='LC124'><span class="cp">#endif</span></div><div class='line' id='LC125'><br/></div><div class='line' id='LC126'><span class="cm">/**</span></div><div class='line' id='LC127'><span class="cm"> * @brief DAC CHN3 interrupt priority level setting.</span></div><div class='line' id='LC128'><span class="cm"> */</span></div><div class='line' id='LC129'><span class="cp">#if !defined(STM32_DAC_CHN3_IRQ_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC130'><span class="cp">#define STM32_DAC_CHN3_IRQ_PRIORITY 10</span></div><div class='line' id='LC131'><span class="cp">#endif</span></div><div class='line' id='LC132'><br/></div><div class='line' id='LC133'><span class="cm">/**</span></div><div class='line' id='LC134'><span class="cm"> * @brief DAC CHN1 DMA priority (0..3|lowest..highest).</span></div><div class='line' id='LC135'><span class="cm"> */</span></div><div class='line' id='LC136'><span class="cp">#if !defined(STM32_DAC_CHN1_DMA_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC137'><span class="cp">#define STM32_DAC_CHN1_DMA_PRIORITY 2</span></div><div class='line' id='LC138'><span class="cp">#endif</span></div><div class='line' id='LC139'><br/></div><div class='line' id='LC140'><span class="cm">/**</span></div><div class='line' id='LC141'><span class="cm"> * @brief DAC CHN2 DMA priority (0..3|lowest..highest).</span></div><div class='line' id='LC142'><span class="cm"> */</span></div><div class='line' id='LC143'><span class="cp">#if !defined(STM32_DAC_CHN2_DMA_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC144'><span class="cp">#define STM32_DAC_CHN2_DMA_PRIORITY 2</span></div><div class='line' id='LC145'><span class="cp">#endif</span></div><div class='line' id='LC146'><br/></div><div class='line' id='LC147'><span class="cm">/**</span></div><div class='line' id='LC148'><span class="cm"> * @brief DAC CHN3 DMA priority (0..3|lowest..highest).</span></div><div class='line' id='LC149'><span class="cm"> */</span></div><div class='line' id='LC150'><span class="cp">#if !defined(STM32_DAC_CHN3_DMA_PRIORITY) || defined(__DOXYGEN__)</span></div><div class='line' id='LC151'><span class="cp">#define STM32_DAC_CHN2_DMA_PRIORITY 2</span></div><div class='line' id='LC152'><span class="cp">#endif</span></div><div class='line' id='LC153'><br/></div><div class='line' id='LC154'><span class="cm">/**</span></div><div class='line' id='LC155'><span class="cm"> * @brief DAC DMA error hook.</span></div><div class='line' id='LC156'><span class="cm"> */</span></div><div class='line' id='LC157'><span class="cp">#if !defined(STM32_DAC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)</span></div><div class='line' id='LC158'><span class="cp">#define STM32_DAC_DMA_ERROR_HOOK(dacp) osalSysHalt()</span></div><div class='line' id='LC159'><span class="cp">#endif</span></div><div class='line' id='LC160'><br/></div><div class='line' id='LC161'><span class="cm">/**</span></div><div class='line' id='LC162'><span class="cm"> * @brief DMA stream used for DAC CHN1 TX operations.</span></div><div class='line' id='LC163'><span class="cm"> * @note This option is only available on platforms with enhanced DMA.</span></div><div class='line' id='LC164'><span class="cm"> */</span></div><div class='line' id='LC165'><span class="cp">#if !defined(STM32_DAC_CHN1_DMA_STREAM) || defined(__DOXYGEN__)</span></div><div class='line' id='LC166'><span class="cp">#define STM32_DAC_CHN1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)</span></div><div class='line' id='LC167'><span class="cp">#endif</span></div><div class='line' id='LC168'><br/></div><div class='line' id='LC169'><span class="cm">/**</span></div><div class='line' id='LC170'><span class="cm"> * @brief DMA stream used for DAC CHN2 TX operations.</span></div><div class='line' id='LC171'><span class="cm"> * @note This option is only available on platforms with enhanced DMA.</span></div><div class='line' id='LC172'><span class="cm"> */</span></div><div class='line' id='LC173'><span class="cp">#if !defined(STM32_DAC_CHN2_DMA_STREAM) || defined(__DOXYGEN__)</span></div><div class='line' id='LC174'><span class="cp">#define STM32_DAC_CHN2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)</span></div><div class='line' id='LC175'><span class="cp">#endif</span></div><div class='line' id='LC176'><br/></div><div class='line' id='LC177'><span class="cm">/**</span></div><div class='line' id='LC178'><span class="cm"> * @brief DMA stream used for DAC CHN3 TX operations.</span></div><div class='line' id='LC179'><span class="cm"> * @note This option is only available on platforms with enhanced DMA.</span></div><div class='line' id='LC180'><span class="cm"> */</span></div><div class='line' id='LC181'><span class="cp">#if !defined(STM32_DAC_CHN3_DMA_STREAM) || defined(__DOXYGEN__)</span></div><div class='line' id='LC182'><span class="cp">#define STM32_DAC_CHN3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)</span></div><div class='line' id='LC183'><span class="cp">#endif</span></div><div class='line' id='LC184'><br/></div><div class='line' id='LC185'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC186'><span class="cm">/* Derived constants and error checks. */</span></div><div class='line' id='LC187'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC188'><br/></div><div class='line' id='LC189'><span class="cp">#if STM32_DAC_USE_CHN1 && !STM32_HAS_DAC_CHN1</span></div><div class='line' id='LC190'><span class="cp">#error "DAC CHN1 not present in the selected device"</span></div><div class='line' id='LC191'><span class="cp">#endif</span></div><div class='line' id='LC192'><br/></div><div class='line' id='LC193'><span class="cp">#if STM32_DAC_USE_CHN2 && !STM32_HAS_DAC_CHN2</span></div><div class='line' id='LC194'><span class="cp">#error "DAC CHN2 not present in the selected device"</span></div><div class='line' id='LC195'><span class="cp">#endif</span></div><div class='line' id='LC196'><br/></div><div class='line' id='LC197'><span class="cp">#if STM32_DAC_USE_CHN3 && !STM32_HAS_DAC_CHN3</span></div><div class='line' id='LC198'><span class="cp">#error "DAC CHN3 not present in the selected device"</span></div><div class='line' id='LC199'><span class="cp">#endif</span></div><div class='line' id='LC200'><br/></div><div class='line' id='LC201'><span class="cp">#if !STM32_DAC_USE_CHN1 && !STM32_DAC_USE_CHN2 && !STM32_DAC_USE_CHN3</span></div><div class='line' id='LC202'><span class="cp">#error "DAC driver activated but no DAC peripheral assigned"</span></div><div class='line' id='LC203'><span class="cp">#endif</span></div><div class='line' id='LC204'><br/></div><div class='line' id='LC205'><span class="cp">#if STM32_DAC_USE_CHN1 && \</span></div><div class='line' id='LC206'><span class="cp"> !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN1_DMA_STREAM, STM32_DAC_CHN1_DMA_MSK)</span></div><div class='line' id='LC207'><span class="cp">#error "invalid DMA stream associated to DAC CHN1"</span></div><div class='line' id='LC208'><span class="cp">#endif</span></div><div class='line' id='LC209'><br/></div><div class='line' id='LC210'><span class="cp">#if STM32_DAC_USE_CHN2 && \</span></div><div class='line' id='LC211'><span class="cp"> !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN2_DMA_STREAM, STM32_DAC_CHN2_DMA_MSK)</span></div><div class='line' id='LC212'><span class="cp">#error "invalid DMA stream associated to DAC CHN2"</span></div><div class='line' id='LC213'><span class="cp">#endif</span></div><div class='line' id='LC214'><br/></div><div class='line' id='LC215'><span class="cp">#if STM32_DAC_USE_CHN3 && \</span></div><div class='line' id='LC216'><span class="cp"> !STM32_DMA_IS_VALID_ID(STM32_DAC_CHN3_DMA_STREAM, STM32_DAC_CHN3_DMA_MSK)</span></div><div class='line' id='LC217'><span class="cp">#error "invalid DMA stream associated to DAC CHN3"</span></div><div class='line' id='LC218'><span class="cp">#endif</span></div><div class='line' id='LC219'><br/></div><div class='line' id='LC220'><span class="cp">#if !defined(STM32_DMA_REQUIRED)</span></div><div class='line' id='LC221'><span class="cp">#define STM32_DMA_REQUIRED</span></div><div class='line' id='LC222'><span class="cp">#endif</span></div><div class='line' id='LC223'><br/></div><div class='line' id='LC224'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC225'><span class="cm">/* Driver data structures and types. */</span></div><div class='line' id='LC226'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC227'><br/></div><div class='line' id='LC228'><span class="cm">/**</span></div><div class='line' id='LC229'><span class="cm"> * @brief Type of a structure representing an DAC driver.</span></div><div class='line' id='LC230'><span class="cm"> */</span></div><div class='line' id='LC231'><span class="k">typedef</span> <span class="k">struct</span> <span class="n">DACDriver</span> <span class="n">DACDriver</span><span class="p">;</span></div><div class='line' id='LC232'><br/></div><div class='line' id='LC233'><span class="cm">/**</span></div><div class='line' id='LC234'><span class="cm"> * @brief Type representing a DAC sample.</span></div><div class='line' id='LC235'><span class="cm"> */</span></div><div class='line' id='LC236'><span class="k">typedef</span> <span class="kt">uint16_t</span> <span class="kt">dacsample_t</span><span class="p">;</span></div><div class='line' id='LC237'><br/></div><div class='line' id='LC238'><span class="cm">/**</span></div><div class='line' id='LC239'><span class="cm"> * @brief DAC notification callback type.</span></div><div class='line' id='LC240'><span class="cm"> *</span></div><div class='line' id='LC241'><span class="cm"> * @param[in] dacp pointer to the @p DACDriver object triggering the</span></div><div class='line' id='LC242'><span class="cm"> * callback</span></div><div class='line' id='LC243'><span class="cm"> */</span></div><div class='line' id='LC244'><span class="k">typedef</span> <span class="nf">void</span> <span class="p">(</span><span class="o">*</span><span class="kt">daccallback_t</span><span class="p">)(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC245'><br/></div><div class='line' id='LC246'><span class="k">typedef</span> <span class="k">enum</span> <span class="p">{</span> </div><div class='line' id='LC247'> <span class="n">DAC_DHRM_12BIT_RIGHT</span> <span class="o">=</span> <span class="mi">0</span><span class="p">,</span></div><div class='line' id='LC248'> <span class="n">DAC_DHRM_12BIT_LEFT</span> <span class="o">=</span> <span class="mi">1</span><span class="p">,</span></div><div class='line' id='LC249'> <span class="n">DAC_DHRM_8BIT_RIGHT</span> <span class="o">=</span> <span class="mi">2</span><span class="p">,</span></div><div class='line' id='LC250'><span class="cp">#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2 && !defined(__DOXYGEN__)</span></div><div class='line' id='LC251'> <span class="n">DAC_DHRM_12BIT_RIGHT_DUAL</span> <span class="o">=</span> <span class="mi">3</span><span class="p">,</span></div><div class='line' id='LC252'> <span class="n">DAC_DHRM_12BIT_LEFT_DUAL</span> <span class="o">=</span> <span class="mi">4</span><span class="p">,</span></div><div class='line' id='LC253'> <span class="n">DAC_DHRM_8BIT_RIGHT_DUAL</span> <span class="o">=</span> <span class="mi">5</span></div><div class='line' id='LC254'><span class="cp">#endif</span></div><div class='line' id='LC255'><span class="p">}</span> <span class="kt">dacdhrmode_t</span><span class="p">;</span></div><div class='line' id='LC256'><br/></div><div class='line' id='LC257'><span class="cm">/**</span></div><div class='line' id='LC258'><span class="cm"> * @brief DAC Conversion group structure.</span></div><div class='line' id='LC259'><span class="cm"> */</span></div><div class='line' id='LC260'><span class="k">typedef</span> <span class="k">struct</span> <span class="p">{</span></div><div class='line' id='LC261'> <span class="cm">/**</span></div><div class='line' id='LC262'><span class="cm"> * @brief Number of DAC channels.</span></div><div class='line' id='LC263'><span class="cm"> */</span></div><div class='line' id='LC264'> <span class="kt">uint16_t</span> <span class="n">num_channels</span><span class="p">;</span></div><div class='line' id='LC265'> <span class="cm">/**</span></div><div class='line' id='LC266'><span class="cm"> * @brief Operation complete callback or @p NULL.</span></div><div class='line' id='LC267'><span class="cm"> */</span></div><div class='line' id='LC268'> <span class="kt">daccallback_t</span> <span class="n">end_cb</span><span class="p">;</span></div><div class='line' id='LC269'> <span class="cm">/**</span></div><div class='line' id='LC270'><span class="cm"> * @brief Error handling callback or @p NULL.</span></div><div class='line' id='LC271'><span class="cm"> */</span></div><div class='line' id='LC272'> <span class="kt">daccallback_t</span> <span class="n">error_cb</span><span class="p">;</span></div><div class='line' id='LC273'> </div><div class='line' id='LC274'><span class="p">}</span> <span class="n">DACConversionGroup</span><span class="p">;</span></div><div class='line' id='LC275'><br/></div><div class='line' id='LC276'><span class="cm">/**</span></div><div class='line' id='LC277'><span class="cm"> * @brief Driver configuration structure.</span></div><div class='line' id='LC278'><span class="cm"> */</span></div><div class='line' id='LC279'><span class="k">typedef</span> <span class="k">struct</span> <span class="p">{</span></div><div class='line' id='LC280'> <span class="cm">/**</span></div><div class='line' id='LC281'><span class="cm"> * @brief Timer frequency in Hz.</span></div><div class='line' id='LC282'><span class="cm"> */</span></div><div class='line' id='LC283'> <span class="kt">uint32_t</span> <span class="n">frequency</span><span class="p">;</span></div><div class='line' id='LC284'> <span class="cm">/* End of the mandatory fields.*/</span></div><div class='line' id='LC285'> <span class="cm">/**</span></div><div class='line' id='LC286'><span class="cm"> * @brief DAC data holding register mode.</span></div><div class='line' id='LC287'><span class="cm"> */</span></div><div class='line' id='LC288'> <span class="kt">dacdhrmode_t</span> <span class="n">dhrm</span><span class="p">;</span></div><div class='line' id='LC289'> <span class="cm">/**</span></div><div class='line' id='LC290'><span class="cm"> * @brief DAC initialization data.</span></div><div class='line' id='LC291'><span class="cm"> */</span></div><div class='line' id='LC292'> <span class="kt">uint32_t</span> <span class="n">cr_flags</span><span class="p">;</span></div><div class='line' id='LC293'><span class="p">}</span> <span class="n">DACConfig</span><span class="p">;</span></div><div class='line' id='LC294'><br/></div><div class='line' id='LC295'><span class="cm">/**</span></div><div class='line' id='LC296'><span class="cm"> * @brief Structure representing a DAC driver.</span></div><div class='line' id='LC297'><span class="cm"> */</span></div><div class='line' id='LC298'><span class="k">struct</span> <span class="n">DACDriver</span> <span class="p">{</span></div><div class='line' id='LC299'> <span class="cm">/**</span></div><div class='line' id='LC300'><span class="cm"> * @brief Driver state.</span></div><div class='line' id='LC301'><span class="cm"> */</span></div><div class='line' id='LC302'> <span class="kt">dacstate_t</span> <span class="n">state</span><span class="p">;</span></div><div class='line' id='LC303'> <span class="cm">/**</span></div><div class='line' id='LC304'><span class="cm"> * @brief Conversion group.</span></div><div class='line' id='LC305'><span class="cm"> */</span></div><div class='line' id='LC306'> <span class="k">const</span> <span class="n">DACConversionGroup</span> <span class="o">*</span><span class="n">grpp</span><span class="p">;</span></div><div class='line' id='LC307'> <span class="cm">/**</span></div><div class='line' id='LC308'><span class="cm"> * @brief Samples buffer pointer.</span></div><div class='line' id='LC309'><span class="cm"> */</span></div><div class='line' id='LC310'> <span class="k">const</span> <span class="kt">dacsample_t</span> <span class="o">*</span><span class="n">samples</span><span class="p">;</span></div><div class='line' id='LC311'> <span class="cm">/**</span></div><div class='line' id='LC312'><span class="cm"> * @brief Samples buffer size.</span></div><div class='line' id='LC313'><span class="cm"> */</span></div><div class='line' id='LC314'> <span class="kt">uint16_t</span> <span class="n">depth</span><span class="p">;</span></div><div class='line' id='LC315'> <span class="cm">/**</span></div><div class='line' id='LC316'><span class="cm"> * @brief Current configuration data.</span></div><div class='line' id='LC317'><span class="cm"> */</span></div><div class='line' id='LC318'> <span class="k">const</span> <span class="n">DACConfig</span> <span class="o">*</span><span class="n">config</span><span class="p">;</span></div><div class='line' id='LC319'><span class="cp">#if DAC_USE_WAIT || defined(__DOXYGEN__)</span></div><div class='line' id='LC320'> <span class="cm">/**</span></div><div class='line' id='LC321'><span class="cm"> * @brief Waiting thread.</span></div><div class='line' id='LC322'><span class="cm"> */</span></div><div class='line' id='LC323'> <span class="kt">thread_reference_t</span> <span class="kr">thread</span><span class="p">;</span></div><div class='line' id='LC324'><span class="cp">#endif </span><span class="cm">/* DAC_USE_WAIT */</span><span class="cp"></span></div><div class='line' id='LC325'><span class="cp">#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)</span></div><div class='line' id='LC326'> <span class="cm">/**</span></div><div class='line' id='LC327'><span class="cm"> * @brief Mutex protecting the bus.</span></div><div class='line' id='LC328'><span class="cm"> */</span></div><div class='line' id='LC329'> <span class="kt">mutex_t</span> <span class="n">mutex</span><span class="p">;</span></div><div class='line' id='LC330'><span class="cp">#endif </span><span class="cm">/* DAC_USE_MUTUAL_EXCLUSION */</span><span class="cp"></span></div><div class='line' id='LC331'><span class="cp">#if defined(DAC_DRIVER_EXT_FIELDS)</span></div><div class='line' id='LC332'> <span class="n">DAC_DRIVER_EXT_FIELDS</span></div><div class='line' id='LC333'><span class="cp">#endif</span></div><div class='line' id='LC334'> <span class="cm">/* End of the mandatory fields.*/</span></div><div class='line' id='LC335'> <span class="cm">/**</span></div><div class='line' id='LC336'><span class="cm"> * @brief Pointer to the DAC registers block.</span></div><div class='line' id='LC337'><span class="cm"> */</span></div><div class='line' id='LC338'> <span class="n">DAC_TypeDef</span> <span class="o">*</span><span class="n">dac</span><span class="p">;</span></div><div class='line' id='LC339'> <span class="cm">/**</span></div><div class='line' id='LC340'><span class="cm"> * @brief Pointer to the TIMx registers block.</span></div><div class='line' id='LC341'><span class="cm"> */</span></div><div class='line' id='LC342'> <span class="kt">stm32_tim_t</span> <span class="o">*</span><span class="n">tim</span><span class="p">;</span></div><div class='line' id='LC343'> <span class="cm">/**</span></div><div class='line' id='LC344'><span class="cm"> * @brief The Timer IRQ priority.</span></div><div class='line' id='LC345'><span class="cm"> */</span></div><div class='line' id='LC346'> <span class="kt">uint32_t</span> <span class="n">irqprio</span><span class="p">;</span></div><div class='line' id='LC347'> <span class="cm">/**</span></div><div class='line' id='LC348'><span class="cm"> * @brief Transmit DMA stream.</span></div><div class='line' id='LC349'><span class="cm"> */</span></div><div class='line' id='LC350'> <span class="k">const</span> <span class="kt">stm32_dma_stream_t</span> <span class="o">*</span><span class="n">dma</span><span class="p">;</span></div><div class='line' id='LC351'> <span class="cm">/**</span></div><div class='line' id='LC352'><span class="cm"> * @brief TX DMA mode bit mask.</span></div><div class='line' id='LC353'><span class="cm"> */</span></div><div class='line' id='LC354'> <span class="kt">uint32_t</span> <span class="n">dmamode</span><span class="p">;</span></div><div class='line' id='LC355'> <span class="cm">/**</span></div><div class='line' id='LC356'><span class="cm"> * @brief Timer base clock.</span></div><div class='line' id='LC357'><span class="cm"> */</span></div><div class='line' id='LC358'> <span class="kt">uint32_t</span> <span class="n">clock</span><span class="p">;</span></div><div class='line' id='LC359'><span class="p">};</span></div><div class='line' id='LC360'><br/></div><div class='line' id='LC361'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC362'><span class="cm">/* Driver macros. */</span></div><div class='line' id='LC363'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC364'><br/></div><div class='line' id='LC365'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC366'><span class="cm">/* External declarations. */</span></div><div class='line' id='LC367'><span class="cm">/*===========================================================================*/</span></div><div class='line' id='LC368'><br/></div><div class='line' id='LC369'><span class="cp">#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__)</span></div><div class='line' id='LC370'><span class="k">extern</span> <span class="n">DACDriver</span> <span class="n">DACD1</span><span class="p">;</span></div><div class='line' id='LC371'><span class="cp">#endif</span></div><div class='line' id='LC372'><br/></div><div class='line' id='LC373'><span class="cp">#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__)</span></div><div class='line' id='LC374'><span class="k">extern</span> <span class="n">DACDriver</span> <span class="n">DACD2</span><span class="p">;</span></div><div class='line' id='LC375'><span class="cp">#endif</span></div><div class='line' id='LC376'><br/></div><div class='line' id='LC377'><span class="cp">#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__)</span></div><div class='line' id='LC378'><span class="k">extern</span> <span class="n">DACDriver</span> <span class="n">DACD3</span><span class="p">;</span></div><div class='line' id='LC379'><span class="cp">#endif</span></div><div class='line' id='LC380'><br/></div><div class='line' id='LC381'><span class="cp">#ifdef __cplusplus</span></div><div class='line' id='LC382'><span class="k">extern</span> <span class="s">"C"</span> <span class="p">{</span></div><div class='line' id='LC383'><span class="cp">#endif</span></div><div class='line' id='LC384'> <span class="kt">void</span> <span class="n">dac_lld_init</span><span class="p">(</span><span class="kt">void</span><span class="p">);</span></div><div class='line' id='LC385'> <span class="kt">void</span> <span class="nf">dac_lld_start</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC386'> <span class="kt">void</span> <span class="nf">dac_lld_stop</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC387'> <span class="kt">void</span> <span class="nf">dac_lld_start_conversion</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC388'> <span class="kt">void</span> <span class="nf">dac_lld_stop_conversion</span><span class="p">(</span><span class="n">DACDriver</span> <span class="o">*</span><span class="n">dacp</span><span class="p">);</span></div><div class='line' id='LC389'><span class="cp">#ifdef __cplusplus</span></div><div class='line' id='LC390'><span class="p">}</span></div><div class='line' id='LC391'><span class="cp">#endif</span></div><div class='line' id='LC392'><br/></div><div class='line' id='LC393'><span class="cp">#endif </span><span class="cm">/* HAL_USE_DAC */</span><span class="cp"></span></div><div class='line' id='LC394'><br/></div><div class='line' id='LC395'><span class="cp">#endif </span><span class="cm">/* _DAC_LLD_H_ */</span><span class="cp"></span></div><div class='line' id='LC396'><br/></div><div class='line' id='LC397'><span class="cm">/** @} */</span></div></pre></div></td> - </tr> - </table> - </div> - - </div> -</div> - -<a href="#jump-to-line" rel="facebox[.linejump]" data-hotkey="l" class="js-jump-to-line" style="display:none">Jump to Line</a> -<div id="jump-to-line" style="display:none"> - <form accept-charset="UTF-8" class="js-jump-to-line-form"> - <input class="linejump-input js-jump-to-line-field" type="text" placeholder="Jump to line…" autofocus> - <button type="submit" class="button">Go</button> - </form> -</div> - - </div> - - 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went wrong with that request. Please try again. - </div> - - </body> -</html> - +} DACConversionGroup; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Timer frequency in Hz. + */ + uint32_t frequency; + /* End of the mandatory fields.*/ + /** + * @brief DAC data holding register mode. + */ + dacdhrmode_t dhrm; + /** + * @brief DAC initialization data. + */ + uint32_t cr_flags; +} DACConfig; + +/** + * @brief Structure representing a DAC driver. + */ +struct DACDriver { + /** + * @brief Driver state. + */ + dacstate_t state; + /** + * @brief Conversion group. + */ + const DACConversionGroup *grpp; + /** + * @brief Samples buffer pointer. + */ + const dacsample_t *samples; + /** + * @brief Samples buffer size. + */ + uint16_t depth; + /** + * @brief Current configuration data. + */ + const DACConfig *config; +#if DAC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif /* DAC_USE_WAIT */ +#if DAC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* DAC_USE_MUTUAL_EXCLUSION */ +#if defined(DAC_DRIVER_EXT_FIELDS) + DAC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the DAC registers block. + */ + DAC_TypeDef *dac; + /** + * @brief Pointer to the TIMx registers block. + */ + stm32_tim_t *tim; + /** + * @brief The Timer IRQ priority. + */ + uint32_t irqprio; + /** + * @brief Transmit DMA stream. + */ + const stm32_dma_stream_t *dma; + /** + * @brief TX DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief Timer base clock. + */ + uint32_t clock; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_DAC_USE_CHN1 && !defined(__DOXYGEN__) +extern DACDriver DACD1; +#endif + +#if STM32_DAC_USE_CHN2 && !defined(__DOXYGEN__) +extern DACDriver DACD2; +#endif + +#if STM32_DAC_USE_CHN3 && !defined(__DOXYGEN__) +extern DACDriver DACD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void dac_lld_init(void); + void dac_lld_start(DACDriver *dacp); + void dac_lld_stop(DACDriver *dacp); + void dac_lld_start_conversion(DACDriver *dacp); + void dac_lld_stop_conversion(DACDriver *dacp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_DAC */ + +#endif /* _DAC_LLD_H_ */ + +/** @} */ |