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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2015-08-13 10:26:39 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2015-08-13 10:26:39 +0000
commitd46360e613ac879b9564346d683592a26718ad9b (patch)
tree98fd648bbb32b24495672ebb8a7c421dcf7215d8 /os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
parenta59a43bc288b159a32cd994b5dadb883cfa234ae (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8212 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h')
-rw-r--r--os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h18
1 files changed, 12 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
index e20ebe637..ab46ecf43 100644
--- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
+++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h
@@ -241,15 +241,21 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
* @note On devices without data cache this function does nothing.
* @note The function takes care of cache lines alignment.
*
- * @param[in] addr address of the DMA buffer
- * @param[in] size size of the DMA buffer
+ * @param[in] saddr start address of the DMA buffer, inclusive
+ * @param[in] eaddr end address of the DMA buffer, not inclusive
*
* @api
*/
-#define dmaBufferInvalidate(addr, size) { \
- uint32_t *aaddr = (uint32_t *)(((uint32_t)(addr)) & ~0x1FU); \
- uint32_t asize = (uint32_t)((((size) - 1) | 0x1FU) + 1U); \
- SCB_CleanInvalidateDCache_by_Addr(aaddr, asize); \
+#define dmaBufferInvalidate(saddr, eaddr) { \
+ uint8_t *start = (uint8_t *)(((uint32_t)(saddr)) & ~0x1FU); \
+ uint8_t *end = (uint8_t *)(((((uint32_t)(eaddr)) - 1U) | 0x1FU) + 1U); \
+ __DSB(); \
+ while (start < end) { \
+ SCB->DCCIMVAC = (uint32_t)start; \
+ start += 32U; \
+ } \
+ __DSB(); \
+ __ISB(); \
}
#else
#define dmaBufferInvalidate(addr, size) { \