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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
| commit | e9ffaf9bdc231c69adffd5486c2949f21390e6e1 (patch) | |
| tree | 6e70b0f2705345ca8a6d354dab9364ce07529659 /os/hal/ports/SPC5/LLD/EDMA_v1 | |
| parent | c0a616c52b6c00aeee8917329bf8659d3062a7bc (diff) | |
| download | ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.gz ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.bz2 ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.zip | |
Forked SPC5 drivers from SPC5-HAL project, not all of them, just the one needed for supporting the PPC port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10679 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/SPC5/LLD/EDMA_v1')
| -rw-r--r-- | os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c | 1397 | ||||
| -rw-r--r-- | os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h | 1005 |
2 files changed, 2402 insertions, 0 deletions
diff --git a/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c new file mode 100644 index 000000000..6a50b1d26 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c @@ -0,0 +1,1397 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_edma.c
+ * @brief EDMA helper driver code.
+ *
+ * @addtogroup SPC5xx_EDMA
+ * @{
+ */
+
+#include "hal.h"
+
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES};
+#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
+static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES};
+#endif
+#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
+static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES};
+static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES};
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Configurations for the various EDMA channels.
+ */
+static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA (channels 0..31) error interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector10) {
+ edma_channel_t channel;
+ uint32_t erl, esr = SPC5_EDMA.ESR.R;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Scanning for errors.*/
+ channel = 0;
+ while (((erl = SPC5_EDMA.ERL.R) != 0) &&
+ (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) {
+ if ((erl & (1U << channel)) != 0) {
+ /* Error flag cleared.*/
+ SPC5_EDMA.CER.R = channel;
+
+ /* If the channel is not associated then the error is simply discarded
+ else the error callback is invoked.*/
+ if ((channels[channel] != NULL) &&
+ (channels[channel]->dma_error_func != NULL))
+ channels[channel]->dma_error_func(channel,
+ channels[channel]->dma_param,
+ esr);
+ }
+ channel++;
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 0 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector11) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[0] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 0;
+ channels[0]->dma_func(0, channels[0]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 1 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector12) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[1] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 1;
+ channels[1]->dma_func(1, channels[1]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 2 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector13) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[2] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 2;
+ channels[2]->dma_func(2, channels[2]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 3 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector14) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[3] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 3;
+ channels[3]->dma_func(3, channels[3]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 4 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector15) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[4] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 4;
+ channels[4]->dma_func(4, channels[4]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 5 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector16) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[5] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 5;
+ channels[5]->dma_func(5, channels[5]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 6 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector17) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[6] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 6;
+ channels[6]->dma_func(6, channels[6]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 7 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector18) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[7] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 7;
+ channels[7]->dma_func(7, channels[7]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 8 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector19) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[8] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 8;
+ channels[8]->dma_func(8, channels[8]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 9 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector20) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[9] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 9;
+ channels[9]->dma_func(9, channels[9]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 10 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector21) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[10] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 10;
+ channels[10]->dma_func(10, channels[10]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 11 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector22) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[11] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 11;
+ channels[11]->dma_func(11, channels[11]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 12 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector23) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[12] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 12;
+ channels[12]->dma_func(12, channels[12]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 13 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector24) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[13] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 13;
+ channels[13]->dma_func(13, channels[13]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 14 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector25) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[14] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 14;
+ channels[14]->dma_func(14, channels[14]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 15 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector26) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[15] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 15;
+ channels[15]->dma_func(15, channels[15]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
+/**
+ * @brief EDMA channel 16 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector27) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[16] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 16;
+ channels[16]->dma_func(16, channels[16]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 17 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector28) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[17] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 17;
+ channels[17]->dma_func(17, channels[17]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 18 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector29) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[18] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 18;
+ channels[18]->dma_func(18, channels[18]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 19 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector30) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[19] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 19;
+ channels[19]->dma_func(19, channels[19]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 20 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector31) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[20] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 20;
+ channels[20]->dma_func(20, channels[20]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 21 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector32) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[21] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 21;
+ channels[21]->dma_func(21, channels[21]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 22 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector33) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[22] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 22;
+ channels[22]->dma_func(22, channels[22]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 23 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector34) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[23] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 23;
+ channels[23]->dma_func(23, channels[23]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 24 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector35) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[24] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 24;
+ channels[24]->dma_func(24, channels[24]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 25 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector36) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[25] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 25;
+ channels[25]->dma_func(25, channels[25]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 26 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector37) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[26] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 26;
+ channels[26]->dma_func(26, channels[26]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 27 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector38) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[27] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 27;
+ channels[27]->dma_func(27, channels[27]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 28 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector39) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[28] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 28;
+ channels[28]->dma_func(28, channels[28]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 29 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector40) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[29] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 29;
+ channels[29]->dma_func(29, channels[29]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 30 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector41) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[30] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 30;
+ channels[30]->dma_func(30, channels[30]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 31 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector42) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[31] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 31;
+ channels[31]->dma_func(31, channels[31]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
+/**
+ * @brief EDMA (channels 32..64) error interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector210) {
+ edma_channel_t channel;
+ uint32_t erh, esr = SPC5_EDMA.ESR.R;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Scanning for errors.*/
+ channel = 32;
+ while (((erh = SPC5_EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {
+
+ if ((erh & (1U << (channel - 32))) != 0) {
+ /* Error flag cleared.*/
+ SPC5_EDMA.CER.R = channel;
+
+ /* If the channel is not associated then the error is simply discarded
+ else the error callback is invoked.*/
+ if ((channels[channel] != NULL) &&
+ (channels[channel]->dma_error_func != NULL))
+ channels[channel]->dma_error_func(channel,
+ channels[channel]->dma_param,
+ esr);
+ channel++;
+ }
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 32 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector211) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[32] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 32;
+ channels[32]->dma_func(32, channels[32]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 33 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector212) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[33] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 33;
+ channels[33]->dma_func(33, channels[33]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 34 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector213) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[34] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 34;
+ channels[34]->dma_func(34, channels[34]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 35 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector214) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[35] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 35;
+ channels[35]->dma_func(35, channels[35]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 36 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector215) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[36] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 36;
+ channels[36]->dma_func(36, channels[36]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 37 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector216) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[37] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 37;
+ channels[37]->dma_func(37, channels[37]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 38 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector217) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[38] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 38;
+ channels[38]->dma_func(38, channels[38]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 39 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector218) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[39] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 39;
+ channels[39]->dma_func(39, channels[39]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 40 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector219) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[40] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 40;
+ channels[40]->dma_func(40, channels[40]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 41 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector220) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[41] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 41;
+ channels[41]->dma_func(41, channels[41]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 42 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector221) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[42] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 42;
+ channels[42]->dma_func(42, channels[42]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 43 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector222) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[43] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 43;
+ channels[43]->dma_func(43, channels[43]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 44 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector223) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[44] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 44;
+ channels[44]->dma_func(44, channels[44]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 45 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector224) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[45] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 45;
+ channels[45]->dma_func(45, channels[45]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 46 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector225) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[46] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 46;
+ channels[46]->dma_func(46, channels[46]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 47 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector226) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[47] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 47;
+ channels[47]->dma_func(47, channels[47]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 48 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector227) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[48] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 48;
+ channels[48]->dma_func(48, channels[48]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 49 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector228) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[49] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 49;
+ channels[49]->dma_func(49, channels[49]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 50 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector229) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[50] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 50;
+ channels[50]->dma_func(50, channels[50]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 51 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector230) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[51] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 51;
+ channels[51]->dma_func(51, channels[51]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 52 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector231) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[52] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 52;
+ channels[52]->dma_func(52, channels[52]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 53 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector232) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[53] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 53;
+ channels[53]->dma_func(53, channels[53]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 54 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector233) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[54] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 54;
+ channels[54]->dma_func(54, channels[54]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 55 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector234) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[55] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 55;
+ channels[55]->dma_func(55, channels[55]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 56 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector235) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[56] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 56;
+ channels[56]->dma_func(56, channels[56]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 57 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector236) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[57] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 57;
+ channels[57]->dma_func(57, channels[57]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 58 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector237) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[58] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 58;
+ channels[58]->dma_func(58, channels[58]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 59 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector238) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[59] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 59;
+ channels[59]->dma_func(59, channels[59]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 60 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector239) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[60] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 60;
+ channels[60]->dma_func(60, channels[60]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 61 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector240) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[61] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 61;
+ channels[61]->dma_func(61, channels[61]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 62 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector241) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[62] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 62;
+ channels[62]->dma_func(62, channels[62]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 63 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector242) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[63] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 63;
+ channels[63]->dma_func(63, channels[63]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_EDMA_NCHANNELS > 32 */
+#endif /* SPC5_EDMA_NCHANNELS > 16 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA driver initialization.
+ *
+ * @special
+ */
+void edmaInit(void) {
+ unsigned i;
+
+ SPC5_EDMA.CR.R = SPC5_EDMA_CR_SETTING;
+ SPC5_EDMA.ERQRL.R = 0x00000000;
+ SPC5_EDMA.EEIRL.R = 0x00000000;
+ SPC5_EDMA.IRQRL.R = 0xFFFFFFFF;
+ SPC5_EDMA.ERL.R = 0xFFFFFFFF;
+#if SPC5_EDMA_NCHANNELS > 32
+ SPC5_EDMA.ERQRH.R = 0x00000000;
+ SPC5_EDMA.EEIRH.R = 0x00000000;
+ SPC5_EDMA.IRQRH.R = 0xFFFFFFFF;
+ SPC5_EDMA.ERH.R = 0xFFFFFFFF;
+#endif
+ /* Initializing all the channels with a different priority withing the
+ channels group.*/
+ for (i = 0; i < 16; i++) {
+ SPC5_EDMA.CPR[i].R = g0[i];
+#if SPC5_EDMA_NCHANNELS > 16
+ SPC5_EDMA.CPR[i + 16].R = g1[i];
+#endif
+#if SPC5_EDMA_NCHANNELS > 32
+ SPC5_EDMA.CPR[i + 32].R = g2[i];
+ SPC5_EDMA.CPR[i + 48].R = g3[i];
+#endif
+ }
+
+ /* Error interrupt source.*/
+ INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;
+
+#if defined(SPC5_EDMA_MUX_PCTL)
+ /* DMA MUX PCTL setup, only if required.*/
+ halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL);
+#endif
+}
+
+/**
+ * @brief EDMA channel allocation.
+ *
+ * @param[in] ccfg channel configuration
+ * @return The channel number.
+ * @retval EDMA_ERROR if the channel cannot be allocated.
+ *
+ * @special
+ */
+edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
+
+ osalDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16));
+
+ /* If the channel is already taken then an error is returned.*/
+ if (channels[ccfg->dma_channel] != NULL)
+ return EDMA_ERROR; /* Already taken. */
+
+#if SPC5_EDMA_HAS_MUX
+ /* Programming the MUX.*/
+ SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |
+ ccfg->dma_periph);
+#endif /* !SPC5_EDMA_HAS_MUX */
+
+ /* Associating the configuration to the channel.*/
+ channels[ccfg->dma_channel] = ccfg;
+
+ /* If an error callback is defined then the error interrupt source is
+ enabled for the channel.*/
+ if (ccfg->dma_error_func != NULL)
+ SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel;
+
+ /* Setting up IRQ priority for the selected channel.*/
+ INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio;
+
+ return ccfg->dma_channel;
+}
+
+/**
+ * @brief EDMA channel release.
+ *
+ * @param[in] channel the channel number
+ *
+ * @special
+ */
+void edmaChannelRelease(edma_channel_t channel) {
+
+ osalDbgCheck((channel >= 0) && (channel < SPC5_EDMA_NCHANNELS));
+ osalDbgAssert(channels[channel] != NULL, "not allocated");
+
+ /* Enforcing a stop.*/
+ edmaChannelStop(channel);
+
+#if SPC5_EDMA_HAS_MUX
+ /* Disabling the MUX slot.*/
+ SPC5_DMAMUX.CHCONFIG[channel].R = 0;
+#endif
+
+ /* Clearing ISR sources for the channel.*/
+ SPC5_EDMA.CIRQR.R = channel;
+ SPC5_EDMA.CEEIR.R = channel;
+ SPC5_EDMA.CER.R = channel;
+
+ /* The channels is flagged as available.*/
+ channels[channel] = NULL;
+}
+
+#endif /* SPC5_HAS_EDMA */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h new file mode 100644 index 000000000..c621baea3 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h @@ -0,0 +1,1005 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_edma.h
+ * @brief EDMA helper driver header.
+ *
+ * @addtogroup SPC5xx_EDMA
+ * @{
+ */
+
+#ifndef _SPC5_EDMA_H_
+#define _SPC5_EDMA_H_
+
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA channel allocation error.
+ */
+#define EDMA_ERROR -1
+
+/**
+ * @name EDMA CR register definitions
+ * @{
+ */
+#define EDMA_CR_CX (1U << 17)
+#define EDMA_CR_ECX (1U << 16)
+#define EDMA_CR_GRP3PRI_MASK (3U << 14)
+#define EDMA_CR_GRP3PRI(n) ((n) << 14)
+#define EDMA_CR_GRP2PRI_MASK (3U << 12)
+#define EDMA_CR_GRP2PRI(n) ((n) << 12)
+#define EDMA_CR_GRP1PRI_MASK (3U << 10)
+#define EDMA_CR_GRP1PRI(n) ((n) << 10)
+#define EDMA_CR_GRP0PRI_MASK (3U << 8)
+#define EDMA_CR_GRP0PRI(n) ((n) << 8)
+#define EDMA_CR_EMLM (1U << 7)
+#define EDMA_CR_CLM (1U << 6)
+#define EDMA_CR_HALT (1U << 5)
+#define EDMA_CR_HOE (1U << 4)
+#define EDMA_CR_ERGA (1U << 3)
+#define EDMA_CR_ERCA (1U << 2)
+#define EDMA_CR_EDBG (1U << 1)
+#define EDMA_CR_EBW (1U << 0)
+/** @} */
+
+/**
+ * @name EDMA mode constants
+ * @{
+ */
+#define EDMA_TCD_MODE_START (1U << 0)
+#define EDMA_TCD_MODE_INT_END (1U << 1)
+#define EDMA_TCD_MODE_INT_HALF (1U << 2)
+#define EDMA_TCD_MODE_DREQ (1U << 3)
+#define EDMA_TCD_MODE_SG (1U << 4)
+#define EDMA_TCD_MODE_MELINK (1U << 5)
+#define EDMA_TCD_MODE_ACTIVE (1U << 6)
+#define EDMA_TCD_MODE_DONE (1U << 7)
+#define EDMA_TCD_MODE_MLINKCH_MASK (63U << 8)
+#define EDMA_TCD_MODE_MLINKCH(n) ((uint32_t)(n) << 8)
+#define EDMA_TCD_MODE_BWC_MASK (3U << 14)
+#define EDMA_TCD_MODE_BWC(n) ((uint32_t)(n) << 14)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default EDMA CR register initialization.
+ */
+#if !defined(SPC5_EDMA_CR_SETTING) || defined(__DOXYGEN__)
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#endif
+
+/**
+ * @brief Static priorities for channels group 0.
+ */
+#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 1.
+ */
+#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 2.
+ */
+#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 3.
+ */
+#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief EDMA error handler IRQ priority.
+ */
+#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EDMA peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EDMA_MUX_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief EDMA critical error handler, must not return.
+ */
+#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("EDMA failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of and eDMA channel number.
+ */
+typedef int32_t edma_channel_t;
+
+/**
+ * @brief Type of an eDMA TCD.
+ */
+typedef struct {
+ union {
+ uint32_t word[8];
+ };
+} edma_tcd_t;
+
+/**
+ * @brief Type of an eDMA peripheral.
+ */
+typedef struct {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :14;
+ vuint32_t CX :1;
+ vuint32_t ECX :1;
+ vuint32_t GRP3PRI :2;
+ vuint32_t GRP2PRI :2;
+ vuint32_t GRP1PRI :2;
+ vuint32_t GRP0PRI :2;
+ vuint32_t EMLM :1;
+ vuint32_t CLM :1;
+ vuint32_t HALT :1;
+ vuint32_t HOE :1;
+ vuint32_t ERGA :1;
+ vuint32_t ERCA :1;
+ vuint32_t EDBG :1;
+ vuint32_t :1;
+ } B;
+ } CR; /* DMA Control Register @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD :1;
+ vuint32_t :14;
+ vuint32_t ECX :1;
+ vuint32_t GPE :1;
+ vuint32_t CPE :1;
+ vuint32_t ERRCHN :6;
+ vuint32_t SAE :1;
+ vuint32_t SOE :1;
+ vuint32_t DAE :1;
+ vuint32_t DOE :1;
+ vuint32_t NCE :1;
+ vuint32_t SGE :1;
+ vuint32_t SBE :1;
+ vuint32_t DBE :1;
+ } B;
+ } ESR; /* Error Status Register @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ63 :1;
+ vuint32_t ERQ62 :1;
+ vuint32_t ERQ61 :1;
+ vuint32_t ERQ60 :1;
+ vuint32_t ERQ59 :1;
+ vuint32_t ERQ58 :1;
+ vuint32_t ERQ57 :1;
+ vuint32_t ERQ56 :1;
+ vuint32_t ERQ55 :1;
+ vuint32_t ERQ54 :1;
+ vuint32_t ERQ53 :1;
+ vuint32_t ERQ52 :1;
+ vuint32_t ERQ51 :1;
+ vuint32_t ERQ50 :1;
+ vuint32_t ERQ49 :1;
+ vuint32_t ERQ48 :1;
+ vuint32_t ERQ47 :1;
+ vuint32_t ERQ46 :1;
+ vuint32_t ERQ45 :1;
+ vuint32_t ERQ44 :1;
+ vuint32_t ERQ43 :1;
+ vuint32_t ERQ42 :1;
+ vuint32_t ERQ41 :1;
+ vuint32_t ERQ40 :1;
+ vuint32_t ERQ39 :1;
+ vuint32_t ERQ38 :1;
+ vuint32_t ERQ37 :1;
+ vuint32_t ERQ36 :1;
+ vuint32_t ERQ35 :1;
+ vuint32_t ERQ34 :1;
+ vuint32_t ERQ33 :1;
+ vuint32_t ERQ32 :1;
+ } B;
+ } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ31 :1;
+ vuint32_t ERQ30 :1;
+ vuint32_t ERQ29 :1;
+ vuint32_t ERQ28 :1;
+ vuint32_t ERQ27 :1;
+ vuint32_t ERQ26 :1;
+ vuint32_t ERQ25 :1;
+ vuint32_t ERQ24 :1;
+ vuint32_t ERQ23 :1;
+ vuint32_t ERQ22 :1;
+ vuint32_t ERQ21 :1;
+ vuint32_t ERQ20 :1;
+ vuint32_t ERQ19 :1;
+ vuint32_t ERQ18 :1;
+ vuint32_t ERQ17 :1;
+ vuint32_t ERQ16 :1;
+ vuint32_t ERQ15 :1;
+ vuint32_t ERQ14 :1;
+ vuint32_t ERQ13 :1;
+ vuint32_t ERQ12 :1;
+ vuint32_t ERQ11 :1;
+ vuint32_t ERQ10 :1;
+ vuint32_t ERQ09 :1;
+ vuint32_t ERQ08 :1;
+ vuint32_t ERQ07 :1;
+ vuint32_t ERQ06 :1;
+ vuint32_t ERQ05 :1;
+ vuint32_t ERQ04 :1;
+ vuint32_t ERQ03 :1;
+ vuint32_t ERQ02 :1;
+ vuint32_t ERQ01 :1;
+ vuint32_t ERQ00 :1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/
+
+ union {
+ vuint32_t R;
+ struct {
+
+ vuint32_t EEI63 :1;
+ vuint32_t EEI62 :1;
+ vuint32_t EEI61 :1;
+ vuint32_t EEI60 :1;
+ vuint32_t EEI59 :1;
+ vuint32_t EEI58 :1;
+ vuint32_t EEI57 :1;
+ vuint32_t EEI56 :1;
+ vuint32_t EEI55 :1;
+ vuint32_t EEI54 :1;
+ vuint32_t EEI53 :1;
+ vuint32_t EEI52 :1;
+ vuint32_t EEI51 :1;
+ vuint32_t EEI50 :1;
+ vuint32_t EEI49 :1;
+ vuint32_t EEI48 :1;
+ vuint32_t EEI47 :1;
+ vuint32_t EEI46 :1;
+ vuint32_t EEI45 :1;
+ vuint32_t EEI44 :1;
+ vuint32_t EEI43 :1;
+ vuint32_t EEI42 :1;
+ vuint32_t EEI41 :1;
+ vuint32_t EEI40 :1;
+ vuint32_t EEI39 :1;
+ vuint32_t EEI38 :1;
+ vuint32_t EEI37 :1;
+ vuint32_t EEI36 :1;
+ vuint32_t EEI35 :1;
+ vuint32_t EEI34 :1;
+ vuint32_t EEI33 :1;
+ vuint32_t EEI32 :1;
+ } B;
+ } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EEI31 :1;
+ vuint32_t EEI30 :1;
+ vuint32_t EEI29 :1;
+ vuint32_t EEI28 :1;
+ vuint32_t EEI27 :1;
+ vuint32_t EEI26 :1;
+ vuint32_t EEI25 :1;
+ vuint32_t EEI24 :1;
+ vuint32_t EEI23 :1;
+ vuint32_t EEI22 :1;
+ vuint32_t EEI21 :1;
+ vuint32_t EEI20 :1;
+ vuint32_t EEI19 :1;
+ vuint32_t EEI18 :1;
+ vuint32_t EEI17 :1;
+ vuint32_t EEI16 :1;
+ vuint32_t EEI15 :1;
+ vuint32_t EEI14 :1;
+ vuint32_t EEI13 :1;
+ vuint32_t EEI12 :1;
+ vuint32_t EEI11 :1;
+ vuint32_t EEI10 :1;
+ vuint32_t EEI09 :1;
+ vuint32_t EEI08 :1;
+ vuint32_t EEI07 :1;
+ vuint32_t EEI06 :1;
+ vuint32_t EEI05 :1;
+ vuint32_t EEI04 :1;
+ vuint32_t EEI03 :1;
+ vuint32_t EEI02 :1;
+ vuint32_t EEI01 :1;
+ vuint32_t EEI00 :1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SERQ :7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CERQ :7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SEEI :7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CEEI :7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CINT :7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CERR :7;
+ } B;
+ } CER; /* DMA Clear error Register @baseaddress + 0x1D */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SSB :7;
+ } B;
+ } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CDSB :7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT63 :1;
+ vuint32_t INT62 :1;
+ vuint32_t INT61 :1;
+ vuint32_t INT60 :1;
+ vuint32_t INT59 :1;
+ vuint32_t INT58 :1;
+ vuint32_t INT57 :1;
+ vuint32_t INT56 :1;
+ vuint32_t INT55 :1;
+ vuint32_t INT54 :1;
+ vuint32_t INT53 :1;
+ vuint32_t INT52 :1;
+ vuint32_t INT51 :1;
+ vuint32_t INT50 :1;
+ vuint32_t INT49 :1;
+ vuint32_t INT48 :1;
+ vuint32_t INT47 :1;
+ vuint32_t INT46 :1;
+ vuint32_t INT45 :1;
+ vuint32_t INT44 :1;
+ vuint32_t INT43 :1;
+ vuint32_t INT42 :1;
+ vuint32_t INT41 :1;
+ vuint32_t INT40 :1;
+ vuint32_t INT39 :1;
+ vuint32_t INT38 :1;
+ vuint32_t INT37 :1;
+ vuint32_t INT36 :1;
+ vuint32_t INT35 :1;
+ vuint32_t INT34 :1;
+ vuint32_t INT33 :1;
+ vuint32_t INT32 :1;
+ } B;
+ } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT31 :1;
+ vuint32_t INT30 :1;
+ vuint32_t INT29 :1;
+ vuint32_t INT28 :1;
+ vuint32_t INT27 :1;
+ vuint32_t INT26 :1;
+ vuint32_t INT25 :1;
+ vuint32_t INT24 :1;
+ vuint32_t INT23 :1;
+ vuint32_t INT22 :1;
+ vuint32_t INT21 :1;
+ vuint32_t INT20 :1;
+ vuint32_t INT19 :1;
+ vuint32_t INT18 :1;
+ vuint32_t INT17 :1;
+ vuint32_t INT16 :1;
+ vuint32_t INT15 :1;
+ vuint32_t INT14 :1;
+ vuint32_t INT13 :1;
+ vuint32_t INT12 :1;
+ vuint32_t INT11 :1;
+ vuint32_t INT10 :1;
+ vuint32_t INT09 :1;
+ vuint32_t INT08 :1;
+ vuint32_t INT07 :1;
+ vuint32_t INT06 :1;
+ vuint32_t INT05 :1;
+ vuint32_t INT04 :1;
+ vuint32_t INT03 :1;
+ vuint32_t INT02 :1;
+ vuint32_t INT01 :1;
+ vuint32_t INT00 :1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR63 :1;
+ vuint32_t ERR62 :1;
+ vuint32_t ERR61 :1;
+ vuint32_t ERR60 :1;
+ vuint32_t ERR59 :1;
+ vuint32_t ERR58 :1;
+ vuint32_t ERR57 :1;
+ vuint32_t ERR56 :1;
+ vuint32_t ERR55 :1;
+ vuint32_t ERR54 :1;
+ vuint32_t ERR53 :1;
+ vuint32_t ERR52 :1;
+ vuint32_t ERR51 :1;
+ vuint32_t ERR50 :1;
+ vuint32_t ERR49 :1;
+ vuint32_t ERR48 :1;
+ vuint32_t ERR47 :1;
+ vuint32_t ERR46 :1;
+ vuint32_t ERR45 :1;
+ vuint32_t ERR44 :1;
+ vuint32_t ERR43 :1;
+ vuint32_t ERR42 :1;
+ vuint32_t ERR41 :1;
+ vuint32_t ERR40 :1;
+ vuint32_t ERR39 :1;
+ vuint32_t ERR38 :1;
+ vuint32_t ERR37 :1;
+ vuint32_t ERR36 :1;
+ vuint32_t ERR35 :1;
+ vuint32_t ERR34 :1;
+ vuint32_t ERR33 :1;
+ vuint32_t ERR32 :1;
+ } B;
+ } ERH; /* DMA Error High @baseaddress + 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR31 :1;
+ vuint32_t ERR30 :1;
+ vuint32_t ERR29 :1;
+ vuint32_t ERR28 :1;
+ vuint32_t ERR27 :1;
+ vuint32_t ERR26 :1;
+ vuint32_t ERR25 :1;
+ vuint32_t ERR24 :1;
+ vuint32_t ERR23 :1;
+ vuint32_t ERR22 :1;
+ vuint32_t ERR21 :1;
+ vuint32_t ERR20 :1;
+ vuint32_t ERR19 :1;
+ vuint32_t ERR18 :1;
+ vuint32_t ERR17 :1;
+ vuint32_t ERR16 :1;
+ vuint32_t ERR15 :1;
+ vuint32_t ERR14 :1;
+ vuint32_t ERR13 :1;
+ vuint32_t ERR12 :1;
+ vuint32_t ERR11 :1;
+ vuint32_t ERR10 :1;
+ vuint32_t ERR09 :1;
+ vuint32_t ERR08 :1;
+ vuint32_t ERR07 :1;
+ vuint32_t ERR06 :1;
+ vuint32_t ERR05 :1;
+ vuint32_t ERR04 :1;
+ vuint32_t ERR03 :1;
+ vuint32_t ERR02 :1;
+ vuint32_t ERR01 :1;
+ vuint32_t ERR00 :1;
+ } B;
+ } ERL; /* DMA Error Low @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS63 :1;
+ vuint32_t HRS62 :1;
+ vuint32_t HRS61 :1;
+ vuint32_t HRS60 :1;
+ vuint32_t HRS59 :1;
+ vuint32_t HRS58 :1;
+ vuint32_t HRS57 :1;
+ vuint32_t HRS56 :1;
+ vuint32_t HRS55 :1;
+ vuint32_t HRS54 :1;
+ vuint32_t HRS53 :1;
+ vuint32_t HRS52 :1;
+ vuint32_t HRS51 :1;
+ vuint32_t HRS50 :1;
+ vuint32_t HRS49 :1;
+ vuint32_t HRS48 :1;
+ vuint32_t HRS47 :1;
+ vuint32_t HRS46 :1;
+ vuint32_t HRS45 :1;
+ vuint32_t HRS44 :1;
+ vuint32_t HRS43 :1;
+ vuint32_t HRS42 :1;
+ vuint32_t HRS41 :1;
+ vuint32_t HRS40 :1;
+ vuint32_t HRS39 :1;
+ vuint32_t HRS38 :1;
+ vuint32_t HRS37 :1;
+ vuint32_t HRS36 :1;
+ vuint32_t HRS35 :1;
+ vuint32_t HRS34 :1;
+ vuint32_t HRS33 :1;
+ vuint32_t HRS32 :1;
+ } B;
+ } HRSH; /* hardware request status high @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS31 :1;
+ vuint32_t HRS30 :1;
+ vuint32_t HRS29 :1;
+ vuint32_t HRS28 :1;
+ vuint32_t HRS27 :1;
+ vuint32_t HRS26 :1;
+ vuint32_t HRS25 :1;
+ vuint32_t HRS24 :1;
+ vuint32_t HRS23 :1;
+ vuint32_t HRS22 :1;
+ vuint32_t HRS21 :1;
+ vuint32_t HRS20 :1;
+ vuint32_t HRS19 :1;
+ vuint32_t HRS18 :1;
+ vuint32_t HRS17 :1;
+ vuint32_t HRS16 :1;
+ vuint32_t HRS15 :1;
+ vuint32_t HRS14 :1;
+ vuint32_t HRS13 :1;
+ vuint32_t HRS12 :1;
+ vuint32_t HRS11 :1;
+ vuint32_t HRS10 :1;
+ vuint32_t HRS09 :1;
+ vuint32_t HRS08 :1;
+ vuint32_t HRS07 :1;
+ vuint32_t HRS06 :1;
+ vuint32_t HRS05 :1;
+ vuint32_t HRS04 :1;
+ vuint32_t HRS03 :1;
+ vuint32_t HRS02 :1;
+ vuint32_t HRS01 :1;
+ vuint32_t HRS00 :1;
+ } B;
+ } HRSL; /* hardware request status low @baseaddress + 0x34 */
+
+ uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP :1;
+ vuint8_t DPA :1;
+ vuint8_t GRPPRI :2;
+ vuint8_t CHPRI :4;
+ } B;
+ } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */
+
+ uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */
+
+ edma_tcd_t TCD[64];
+} edma_t;
+
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+/**
+ * @brief Type of a DMA-MUX peripheral.
+ */
+typedef struct {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[SPC5_EDMA_NCHANNELS];
+} dma_mux_t;
+#endif /* SPC5_EDMA_HAS_MUX */
+
+/**
+ * @brief DMA callback type.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ */
+typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
+
+/**
+ * @brief DMA error callback type.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ * @param[in] esr content of the ESR register
+ */
+typedef void (*edma_error_callback_t)(edma_channel_t channel,
+ void *p,
+ uint32_t esr);
+
+/**
+ * @brief Type of an EDMA channel configuration structure.
+ */
+typedef struct {
+ edma_channel_t dma_channel; /**< @brief Channel to be allocated.*/
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+ uint8_t dma_periph; /**< @brief Peripheral to be
+ associated to the channel. */
+#endif
+ uint8_t dma_irq_prio; /**< @brief IRQ priority level for
+ this channel. */
+ edma_callback_t dma_func; /**< @brief Channel callback,
+ can be NULL if not required. */
+ edma_error_callback_t dma_error_func; /**< @brief Channel error callback,
+ can be NULL if not required. */
+ void *dma_param; /**< @brief Channel callback param. */
+} edma_channel_config_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Peripherals references
+ *
+ * @{
+ */
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+#define SPC5_EDMA (*(edma_t *)0xFFF44000U)
+#endif
+
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+#define SPC5_DMAMUX (*(dma_mux_t *)0xFFFDC000UL)
+#endif
+/** @} */
+
+/**
+ * @brief Returns the TCD address associated to a channel.
+ *
+ * @param[in] channel the channel number
+ * @return A pointer to an @p edma_tcd_t structure.
+ *
+ * @api
+ */
+#define edmaGetTCD(channel) ((edma_tcd_t *)&SPC5_EDMA.TCD[channel])
+
+/**
+ * @brief Sets the word 0 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] src the source address
+ *
+ * @api
+ */
+#define edmaTCDSetWord0(tcdp, src) \
+ ((tcdp)->word[0] = (uint32_t)(src))
+
+/**
+ * @brief Sets the word 1 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] ssize the source width
+ * @param[in] dst the destination width
+ * @param[in] soff the source increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord1(tcdp, ssize, dsize, soff) \
+ ((tcdp)->word[1] = (((uint32_t)(ssize) << 24) | \
+ ((uint32_t)(dsize) << 16) | \
+ ((uint32_t)(soff) << 0)))
+
+/**
+ * @brief Sets the word 2 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] nbytes the inner counter value
+ *
+ * @api
+ */
+#define edmaTCDSetWord2(tcdp, nbytes) \
+ ((tcdp)->word[2] = (uint32_t)(nbytes))
+
+/**
+ * @brief Sets the word 3 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] slast the adjustment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord3(tcdp, slast) \
+ ((tcdp)->word[3] = (uint32_t)(slast))
+
+/**
+ * @brief Sets the word 4 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] dst the destination address
+ *
+ * @api
+ */
+#define edmaTCDSetWord4(tcdp, dst) \
+ ((tcdp)->word[4] = (uint32_t)(dst))
+
+/**
+ * @brief Sets the word 5 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] citer the current outer counter value
+ * @param[in] doff the destination increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord5(tcdp, citer, doff) \
+ ((tcdp)->word[5] = (((uint32_t)(citer) << 16) | \
+ ((uint32_t)(doff) << 0)))
+
+/**
+ * @brief Sets the word 5 fields into a TCD.
+ * @note Transfers are limited to 512 operations using this modality
+ * (citer parameter).
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] citer the current outer counter value
+ * @param[in] doff the destination increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord5Linked(tcdp, linkch, citer, doff) \
+ ((tcdp)->word[5] = (((uint32_t)0x80000000) | \
+ ((uint32_t)(linkch) << 25) | \
+ ((uint32_t)(citer) << 16) | \
+ ((uint32_t)(doff) << 0)))
+
+/**
+ * @brief Sets the word 6 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] dlast the adjustment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord6(tcdp, dlast) \
+ ((tcdp)->word[6] = (uint32_t)(dlast))
+
+/**
+ * @brief Sets the word 7 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] biter the base outer counter value
+ * @param[in] mode the mode value
+ *
+ * @api
+ */
+#define edmaTCDSetWord7(tcdp, biter, mode) \
+ ((tcdp)->word[7] = (((uint32_t)(biter) << 16) | \
+ ((uint32_t)(mode) << 0)))
+
+/**
+ * @brief Sets the word 7 fields into a TCD.
+ * @note Transfers are limited to 512 operations using this modality
+ * (biter parameter).
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] biter the base outer counter value
+ * @param[in] mode the mode value
+ *
+ * @api
+ */
+#define edmaTCDSetWord7Linked(tcdp, linkch, biter, mode) \
+ ((tcdp)->word[7] = (((uint32_t)0x80000000) | \
+ ((uint32_t)(linkch) << 25) | \
+ ((uint32_t)(biter) << 16) | \
+ ((uint32_t)(mode) << 0)))
+
+/**
+ * @brief Starts or restarts an EDMA channel.
+ *
+ * @param[in] channel the channel number
+ *
+ * @api
+ */
+#define edmaChannelStart(channel) (SPC5_EDMA.SERQR.R = (channel))
+
+/**
+ * @brief Stops an EDMA channel.
+ *
+ * @param[in] channel the channel number
+ *
+ * @api
+ */
+#define edmaChannelStop(channel) { \
+ SPC5_EDMA.CERQR.R = (channel); \
+ SPC5_EDMA.CDSBR.R = (channel); \
+}
+
+/**
+ * @brief EDMA channel setup.
+ *
+ * @param[in] channel eDMA channel number
+ * @param[in] src source address
+ * @param[in] dst destination address
+ * @param[in] soff source address offset
+ * @param[in] doff destination address offset
+ * @param[in] ssize source transfer size
+ * @param[in] dsize destination transfer size
+ * @param[in] nbytes minor loop count
+ * @param[in] iter major loop count
+ * @param[in] dlast last destination address adjustment
+ * @param[in] slast last source address adjustment
+ * @param[in] mode LSW of TCD register 7
+ *
+ * @api
+ */
+#define edmaChannelSetup(channel, src, dst, soff, doff, ssize, dsize, \
+ nbytes, iter, slast, dlast, mode) { \
+ edma_tcd_t *tcdp = edmaGetTCD(channel); \
+ edmaTCDSetWord0(tcdp, src); \
+ edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
+ edmaTCDSetWord2(tcdp, nbytes); \
+ edmaTCDSetWord3(tcdp, slast); \
+ edmaTCDSetWord4(tcdp, dst); \
+ edmaTCDSetWord5(tcdp, iter, doff); \
+ edmaTCDSetWord6(tcdp, dlast); \
+ edmaTCDSetWord7(tcdp, iter, mode); \
+}
+
+/**
+ * @brief EDMA channel setup with linked channel on both minor and major
+ * loop counters.
+ * @note Transfers are limited to 512 operations using this modality
+ * (iter parameter).
+ *
+ * @param[in] channel eDMA channel number
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] src source address
+ * @param[in] dst destination address
+ * @param[in] soff source address offset
+ * @param[in] doff destination address offset
+ * @param[in] ssize source transfer size
+ * @param[in] dsize destination transfer size
+ * @param[in] nbytes minor loop count
+ * @param[in] iter major loop count
+ * @param[in] dlast last destination address adjustment
+ * @param[in] slast last source address adjustment
+ * @param[in] mode LSW of TCD register 7
+ *
+ * @api
+ */
+#define edmaChannelSetupLinked(channel, linkch, src, dst, soff, \
+ doff, ssize, dsize, nbytes, iter, \
+ slast, dlast, mode) { \
+ edma_tcd_t *tcdp = edmaGetTCD(channel); \
+ edmaTCDSetWord0(tcdp, src); \
+ edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
+ edmaTCDSetWord2(tcdp, nbytes); \
+ edmaTCDSetWord3(tcdp, slast); \
+ edmaTCDSetWord4(tcdp, dst); \
+ edmaTCDSetWord5Linked(tcdp, linkch, iter, doff); \
+ edmaTCDSetWord6(tcdp, dlast); \
+ edmaTCDSetWord7Linked(tcdp, linkch, iter, (mode) | \
+ EDMA_TCD_MODE_MELINK | \
+ EDMA_TCD_MODE_MLINKCH(linkch)); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void edmaInit(void);
+ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg);
+ void edmaChannelRelease(edma_channel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SPC5_HAS_EDMA */
+
+#endif /* _SPC5_EDMA_H_ */
+
+/** @} */
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