Updated SAMA drivers (still incomplete)

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12543 110e8d01-0319-4d1e-a829-52ad28d1bb01

5 files changed, 78 insertions, 5 deletions

diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_aes_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_aes_lld.c
index 0ed4af4a2..a6cb4ee12 100644
--- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_aes_lld.c
+++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_aes_lld.c
@@ -165,9 +165,29 @@ cryerror_t sama_aes_lld_process_dma(CRYDriver *cryp,  aesparams *params,
 	cryerror_t ret;

 

 	osalDbgAssert(cryp->thread == NULL, "already waiting");

+  osalDbgAssert(!((uint32_t) in & (L1_CACHE_BYTES - 1)), "in address not cache aligned");

+  osalDbgAssert(!((uint32_t) out & (L1_CACHE_BYTES - 1)), "out address not cache aligned");

+

+#if 0

+  osalDbgAssert(!(indata_len & (L1_CACHE_BYTES - 1)), "size not multiple of cache line");

+#endif

+

+  /*

+   * If size is not multiple of cache line, clean cache region is required.

+   * TODO: remove when size assert works

+   */

+  if (indata_len & (L1_CACHE_BYTES - 1)) {

+    cacheCleanRegion((uint8_t *) out, indata_len);

+  }

 

 	osalMutexLock(&cryp->mutex);

 

+  cacheCleanRegion((uint8_t *) in, indata_len);

+

+  cryp->out = out;

+  cryp->in = in;

+  cryp->len = indata_len;

+

 	//set chunk size

 	cryp->dmachunksize = DMA_CHUNK_SIZE_4;

 

diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_crypto_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_crypto_lld.c
index a4e19d7c7..764b1b915 100644
--- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_crypto_lld.c
+++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_crypto_lld.c
@@ -19,8 +19,6 @@
 

 #include "sama_crypto_lld.h"

 

-

-

 #if defined(SAMA_DMA_REQUIRED)

 static void crypto_lld_serve_read_interrupt(CRYDriver *cryp, uint32_t flags);

 static void crypto_lld_serve_write_interrupt(CRYDriver *cryp, uint32_t flags);

@@ -50,7 +48,7 @@ static void crypto_lld_serve_write_interrupt(CRYDriver *cryp, uint32_t flags);
  * @note    This macro is meant to be used in the low level drivers

  *          implementation only.

  *

- * @param[in] spip      pointer to the @p SPIDriver object

+ * @param[in] cryp      pointer to the @p CRYDriver object

  *

  * @notapi

  */

@@ -132,6 +130,9 @@ static void crypto_lld_serve_read_interrupt(CRYDriver *cryp, uint32_t flags) {
   (void)flags;

 #endif

 

+  /* D-Cache L1 is enabled */

+  cacheInvalidateRegion(cryp->out, cryp->len);

+

   /* Stop everything.*/

   dmaChannelDisable(cryp->dmarx);

   /* Portable CRY ISR code defined in the high level driver, note, it is

diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_gcm_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_gcm_lld.c
index 2496c03d3..3e9471a2a 100644
--- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_gcm_lld.c
+++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_gcm_lld.c
@@ -36,8 +36,27 @@ static cryerror_t sama_gcm_lld_process_dma(CRYDriver *cryp,cgmcontext * cxt)
 {

 #if defined(SAMA_DMA_REQUIRED)

 

+  osalDbgAssert(!((uint32_t) cxt->in & (L1_CACHE_BYTES - 1)), "in address not cache aligned");

+  osalDbgAssert(!((uint32_t) cxt->out & (L1_CACHE_BYTES - 1)), "out address not cache aligned");

 	osalDbgAssert(cryp->thread == NULL, "already waiting");

 

+#if 0

+  osalDbgAssert(!(cxt->c_size & (L1_CACHE_BYTES - 1)), "size not multiple of cache line");

+#endif

+

+  cacheCleanRegion((uint8_t *) cxt->in, cxt->c_size);

+

+  /*

+   * If size is not multiple of cache line, clean cache region is required.

+   * TODO: remove when size assert works

+   */

+  if (cxt->c_size & (L1_CACHE_BYTES - 1)) {

+    cacheCleanRegion((uint8_t *) cxt->out, cxt->c_size);

+  }

+

+  cryp->out = cxt->out;

+  cryp->in = cxt->in;

+  cryp->len = cxt->c_size;

 

 	//set chunk size

 	cryp->dmachunksize = DMA_CHUNK_SIZE_4;

diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c
index b88386366..cf38e75d0 100644
--- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c
+++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c
@@ -357,10 +357,22 @@ static uint32_t processBlockPolling(const uint8_t *data,uint32_t len, uint32_t b
 	return processed;

 }

 

-static uint32_t processBlockDMA(CRYDriver *cryp, const uint8_t *data,uint32_t len, uint32_t block_size)

-{

+static uint32_t processBlockDMA(CRYDriver *cryp, const uint8_t *data,uint32_t len, uint32_t block_size) {

+

+  osalDbgAssert(!((uint32_t) data & (L1_CACHE_BYTES - 1)), "data address not cache aligned");

+

+#if 0

+  osalDbgAssert(!(block_size & (L1_CACHE_BYTES - 1)), "size not multiple of cache line");

+#endif

+

 	uint32_t processed = 0;

 

+  cryp->out = 0;

+  cryp->in = data;

+  cryp->len = len;

+

+  cacheCleanRegion((uint8_t *) data, len);

+

 	while ((len - processed) >= block_size) {

 

 		// load data in the sha input registers

diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_tdes_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_tdes_lld.c
index fbe000e47..bfbfffe7a 100644
--- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_tdes_lld.c
+++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_tdes_lld.c
@@ -142,11 +142,32 @@ cryerror_t sama_tdes_lld_dma(CRYDriver *cryp, tdes_config_t *params,
 		bool encrypt, const uint8_t *data, size_t data_len, uint8_t * out,

 		const uint8_t *iv) {

 

+  osalDbgAssert(!((uint32_t) data & (L1_CACHE_BYTES - 1)), "data address not cache aligned");

+  osalDbgAssert(!((uint32_t) out & (L1_CACHE_BYTES - 1)), "out address not cache aligned");

+

+#if 0

+  osalDbgAssert(!(data_len & (L1_CACHE_BYTES - 1)), "size not multiple of cache line");

+#endif

+

+  /*

+   * If size is not multiple of cache line, clean cache region is required.

+   * TODO: remove when size assert works

+   */

+  if (data_len & (L1_CACHE_BYTES - 1)) {

+    cacheCleanRegion((uint8_t *) out, data_len);

+  }

+

 	uint32_t mode = 0;

 	uint32_t *vectors = (uint32_t *) iv;

 

 	osalMutexLock(&cryp->mutex);

 

+  cacheCleanRegion((uint8_t *) data, data_len);

+

+  cryp->out = out;

+  cryp->in = data;

+  cryp->len = data_len;

+

 	cryp->dmachunksize = DMA_CHUNK_SIZE_1;

 

 	cryp->dmawith = DMA_DATA_WIDTH_WORD;