diff options
Diffstat (limited to 'os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c')
| -rw-r--r-- | os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c index b88386366..cf38e75d0 100644 --- a/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c +++ b/os/hal/ports/SAMA/LLD/CRYPTOv1/sama_sha_lld.c @@ -357,10 +357,22 @@ static uint32_t processBlockPolling(const uint8_t *data,uint32_t len, uint32_t b return processed;
}
-static uint32_t processBlockDMA(CRYDriver *cryp, const uint8_t *data,uint32_t len, uint32_t block_size)
-{
+static uint32_t processBlockDMA(CRYDriver *cryp, const uint8_t *data,uint32_t len, uint32_t block_size) {
+
+ osalDbgAssert(!((uint32_t) data & (L1_CACHE_BYTES - 1)), "data address not cache aligned");
+
+#if 0
+ osalDbgAssert(!(block_size & (L1_CACHE_BYTES - 1)), "size not multiple of cache line");
+#endif
+
uint32_t processed = 0;
+ cryp->out = 0;
+ cryp->in = data;
+ cryp->len = len;
+
+ cacheCleanRegion((uint8_t *) data, len);
+
while ((len - processed) >= block_size) {
// load data in the sha input registers
|