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author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-07 13:26:44 +0000 |
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committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-07 13:26:44 +0000 |
commit | 7a3a252875ed5a09bc62abe5a3b40c1b0f0d273e (patch) | |
tree | 3cb67a55a3b6b3e0590e3a1cc956826d7f422e7b /os/hal/platforms | |
parent | f85a97a786a176d088f807d3de4a2ec93030ef8e (diff) | |
download | ChibiOS-7a3a252875ed5a09bc62abe5a3b40c1b0f0d273e.tar.gz ChibiOS-7a3a252875ed5a09bc62abe5a3b40c1b0f0d273e.tar.bz2 ChibiOS-7a3a252875ed5a09bc62abe5a3b40c1b0f0d273e.zip |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5819 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
-rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.c | 12 | ||||
-rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.h | 42 | ||||
-rw-r--r-- | os/hal/platforms/SPC560Pxx/platform.mk | 2 | ||||
-rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 114 | ||||
-rw-r--r-- | os/hal/platforms/SPC563Mxx/spc563m_registry.h | 1 | ||||
-rw-r--r-- | os/hal/platforms/SPC564Axx/spc564a_registry.h | 1 | ||||
-rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h | 4 |
7 files changed, 168 insertions, 8 deletions
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c index a5e0fbd5a..1a6cc24af 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.c +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -142,14 +142,22 @@ void spc_clock_init(void) { #endif /* SPC5_OSC_BYPASS */
/* Setting the various dividers and source selectors.*/
+#if SPC5_HAS_AC0
CGM.AC0DC.R = SPC5_CGM_AC0_DC0;
CGM.AC0SC.R = SPC5_AUX0CLK_SRC;
+#endif
+#if SPC5_HAS_AC1
CGM.AC1DC.R = SPC5_CGM_AC1_DC0;
CGM.AC1SC.R = SPC5_AUX1CLK_SRC;
+#endif
+#if SPC5_HAS_AC2
CGM.AC2DC.R = SPC5_CGM_AC2_DC0;
CGM.AC2SC.R = SPC5_AUX2CLK_SRC;
+#endif
+#if SPC5_HAS_AC3
CGM.AC3DC.R = SPC5_CGM_AC3_DC0;
CGM.AC3SC.R = SPC5_AUX3CLK_SRC;
+#endif
/* Enables the XOSC in order to check its functionality before proceeding
with the initialization.*/
@@ -165,10 +173,12 @@ void spc_clock_init(void) { ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL0_NDIV_VALUE << 16);
CGM.FMPLL[0].MR.R = 0; /* TODO: Add a setting. */
+#if SPC5_HAS_FMPLL1
CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
(SPC5_FMPLL1_NDIV_VALUE << 16);
CGM.FMPLL[1].MR.R = 0; /* TODO: Add a setting. */
+#endif
/* Run modes initialization.*/
ME.IS.R = 8; /* Resetting I_ICONF status.*/
@@ -281,8 +291,10 @@ uint32_t halSPCGetSystemClock(void) { return SPC5_XOSC_CLK;
case SPC5_ME_GS_SYSCLK_FMPLL0:
return SPC5_FMPLL0_CLK;
+#if SPC5_HAS_FMPLL1
case SPC5_ME_GS_SYSCLK_FMPLL1:
return SPC5_FMPLL1_CLK;
+#endif
default:
return 0;
}
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index 2d86e0d62..4486b76cb 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -46,7 +46,11 @@ * @name Platform identification
* @{
*/
+#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "SPC56APxx Chassis and Safety"
+#else
#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
+#endif
/** @} */
/**
@@ -90,11 +94,13 @@ /**
* @brief Maximum FMPLL1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
*/
#define SPC5_FMPLL1_CLK_MAX 120000000
/**
* @brief Maximum FMPLL1 1D1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
*/
#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
/** @} */
@@ -381,7 +387,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -402,7 +407,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -416,7 +420,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -430,7 +433,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -444,7 +446,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -458,7 +459,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -472,7 +472,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -486,7 +485,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -738,6 +736,7 @@ #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif
+#if SPC5_HAS_FMPLL1
/* Check on SPC5_FMPLL1_IDF_VALUE.*/
#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
@@ -783,7 +782,9 @@ #if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
#endif
+#endif /* SPC5_HAS_FMPLL1 */
+#if SPC5_HAS_AC0 || defined(__DOXYGEN__)
/**
* @brief AUX0 clock point.
*/
@@ -799,6 +800,10 @@ #error "invalid SPC5_AUX0CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1)
+#error "SPC5_AUX0CLK_SRC, FMPLL1 not present"
+#endif
+
/* Check on the AUX0 divider 0 settings.*/
#if SPC5_MCONTROL_DIVIDER_VALUE == 0
#define SPC5_CGM_AC0_DC0 0
@@ -816,7 +821,9 @@ #else
#define SPC5_MCONTROL_CLK 0
#endif
+#endif /* #if SPC5_HAS_AC0 */
+#if SPC5_HAS_AC1 || defined(__DOXYGEN__)
/**
* @brief AUX1 clock point.
*/
@@ -826,6 +833,10 @@ #error "invalid SPC5_AUX1CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1
+#error "SPC5_AUX1_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX1 divider 0 settings.*/
#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC1_DC0 0
@@ -843,7 +854,9 @@ #else
#define SPC5_FMPLL1_DIV_CLK 0
#endif
+#endif /* SPC5_HAS_AC1 */
+#if SPC5_HAS_AC2 || defined(__DOXYGEN__)
/**
* @brief AUX2 clock point.
*/
@@ -861,6 +874,11 @@ #error "invalid SPC5_AUX2CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1) || \
+ (SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1_1D1))
+#error "SPC5_AUX2_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX2 divider 0 settings.*/
#if SPC5_SP_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC2_DC0 0
@@ -878,7 +896,9 @@ #else
#define SPC5_SP_CLK 0
#endif
+#endif /* SPC5_HAS_AC2 */
+#if SPC5_HAS_AC3 || defined(__DOXYGEN__)
/**
* @brief AUX3 clock point.
*/
@@ -896,6 +916,11 @@ #error "invalid SPC5_AUX3CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) || \
+ (SPC5_AUX3_CLK == SPC5_CGM_SS_FMPLL1_1D1))
+#error "SPC5_AUX3_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX3 divider 0 settings.*/
#if SPC5_FR_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC3_DC0 0
@@ -913,6 +938,7 @@ #else
#define SPC5_FR_CLK 0
#endif
+#endif /* SPC5_HAS_AC3 */
/*===========================================================================*/
/* Driver data structures and types. */
diff --git a/os/hal/platforms/SPC560Pxx/platform.mk b/os/hal/platforms/SPC560Pxx/platform.mk index 36636f0ef..2e82732d1 100644 --- a/os/hal/platforms/SPC560Pxx/platform.mk +++ b/os/hal/platforms/SPC560Pxx/platform.mk @@ -1,5 +1,6 @@ # List of all the SPC560Pxx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1/icu_lld.c \
${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c \
@@ -8,6 +9,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \ # Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \
+ ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/eTimer_v1 \
${CHIBIOS}/os/hal/platforms/SPC5xx/FlexPWM_v1 \
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index f97db2b2c..f4d9462e5 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -26,6 +26,32 @@ #define _SPC560P_REGISTRY_H_
/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_)
+#define _SPC560P34_
+#define _SPC560PXX_SMALL_
+#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_)
+#define _SPC560P40_
+#define _SPC560PXX_SMALL_
+#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_)
+#define _SPC560P44_
+#define _SPC560PXX_MEDIUM_
+#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_)
+#define _SPC560P50_
+#define _SPC560PXX_MEDIUM_
+#elif defined(_SPC560P54L5_) || defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_)
+#define _SPC560P54_
+#define _SPC560PXX_LARGE_
+#elif defined(_SPC560P60L5_) || defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_)
+#define _SPC560P60_
+#define _SPC560PXX_LARGE_
+#else
+#error "SPC56xPxx platform not defined"
+#endif
+
+/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
@@ -33,6 +59,85 @@ * @name SPC560Pxx capabilities
* @{
*/
+/* Clock attributes.*/
+#if defined(_SPC560PXX_SMALL_)
+#define SPC5_HAS_FMPLL1 FALSE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 FALSE
+#define SPC5_HAS_AC1 FALSE
+#define SPC5_HAS_AC2 FALSE
+#define SPC5_HAS_AC3 FALSE
+
+#elif defined(_SPC560PXX_MEDIUM_)
+#define SPC5_HAS_FMPLL1 TRUE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 TRUE
+#define SPC5_HAS_AC1 TRUE
+#define SPC5_HAS_AC2 TRUE
+#define SPC5_HAS_AC3 TRUE
+
+#else /* defined(_SPC560PXX_LARGE_) */
+#define SPC5_HAS_FMPLL1 FALSE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 FALSE
+#define SPC5_HAS_AC1 FALSE
+#define SPC5_HAS_AC2 FALSE
+#define SPC5_HAS_AC3 TRUE
+#endif
+
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI_FIFO_DEPTH 5
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI0_ENABLE_CLOCK()
+#define SPC5_DSPI0_DISABLE_CLOCK()
+#define SPC5_DSPI1_ENABLE_CLOCK()
+#define SPC5_DSPI1_DISABLE_CLOCK()
+#define SPC5_DSPI2_ENABLE_CLOCK()
+#define SPC5_DSPI2_DISABLE_CLOCK()
+
+#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
+#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI3_RX_DMA_DEV_ID 8
+#define SPC5_DSPI3_TFFF_HANDLER vector219
+#define SPC5_DSPI3_TFFF_NUMBER 219
+#define SPC5_DSPI3_ENABLE_CLOCK()
+#define SPC5_DSPI3_DISABLE_CLOCK()
+#else
+#define SPC5_HAS_DSPI3 FALSE
+#endif
+
+#if defined(_SPC560PXX_LARGE_)
+#define SPC5_HAS_DSPI4 TRUE
+#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
+#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI4_RX_DMA_DEV_ID 21
+#define SPC5_DSPI4_TFFF_HANDLER vector258
+#define SPC5_DSPI4_TFFF_NUMBER 258
+#define SPC5_DSPI4_ENABLE_CLOCK()
+#define SPC5_DSPI4_DISABLE_CLOCK()
+#else
+#define SPC5_HAS_DSPI4 FALSE
+#endif
+
/* eDMA attributes.*/
#define SPC5_HAS_EDMA TRUE
#define SPC5_EDMA_NCHANNELS 16
@@ -70,6 +175,7 @@ #define SPC5_SIUL_NUM_PADSELS 36
/* FlexPWM attributes.*/
+#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_)
#define SPC5_HAS_FLEXPWM0 TRUE
#define SPC5_FLEXPWM0_PCTL 41
#define SPC5_FLEXPWM0_RF0_HANDLER vector179
@@ -101,6 +207,9 @@ #define SPC5_FLEXPWM0_FFLAG_NUMBER 191
#define SPC5_FLEXPWM0_REF_NUMBER 192
#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
+#else /* defined(_SPC560PXX_LARGE_) */
+#define SPC5_HAS_FLEXPWM0 FALSE
+#endif /* defined(_SPC560PXX_LARGE_) */
#define SPC5_HAS_FLEXPWM1 FALSE
@@ -125,6 +234,7 @@ #define SPC5_ETIMER0_RCF_NUMBER 167
#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
+#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_ETIMER1 TRUE
#define SPC5_ETIMER1_PCTL 39
#define SPC5_ETIMER1_TC0IR_HANDLER vector168
@@ -143,6 +253,10 @@ #define SPC5_ETIMER1_RCF_NUMBER 178
#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
+#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
+#define SPC5_HAS_ETIMER1 FALSE
+#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
+
#define SPC5_HAS_ETIMER2 FALSE
/* FlexCAN attributes.*/
diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h index ce2da4e20..dc1145532 100644 --- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h +++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h @@ -38,6 +38,7 @@ #define SPC5_HAS_DSPI1 TRUE
#define SPC5_HAS_DSPI2 TRUE
#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
#define SPC5_DSPI1_TX2_DMA_DEV_ID 25
diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h index 578b658ed..bcdd6753b 100644 --- a/os/hal/platforms/SPC564Axx/spc564a_registry.h +++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h @@ -52,6 +52,7 @@ #define SPC5_HAS_DSPI1 TRUE
#define SPC5_HAS_DSPI2 TRUE
#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
#define SPC5_DSPI1_TX1_DMA_DEV_ID 12
#define SPC5_DSPI1_TX2_DMA_DEV_ID 24
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h index f04e7eb60..addaf67cb 100644 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h @@ -270,6 +270,10 @@ struct spc5_dspi { #if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U)
#endif
+
+#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
+#define SPC5_DSPI4 (*(struct spc5_dspi *)0x8FFA0000U)
+#endif
/** @} */
#endif /* _SPC5_DSPI_H_ */
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