diff options
Diffstat (limited to 'os/hal/platforms/SPC560Pxx/hal_lld.h')
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/hal_lld.h | 42 |
1 files changed, 34 insertions, 8 deletions
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index 2d86e0d62..4486b76cb 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -46,7 +46,11 @@ * @name Platform identification
* @{
*/
+#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "SPC56APxx Chassis and Safety"
+#else
#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
+#endif
/** @} */
/**
@@ -90,11 +94,13 @@ /**
* @brief Maximum FMPLL1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
*/
#define SPC5_FMPLL1_CLK_MAX 120000000
/**
* @brief Maximum FMPLL1 1D1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
*/
#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
/** @} */
@@ -381,7 +387,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -402,7 +407,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -416,7 +420,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -430,7 +433,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -444,7 +446,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -458,7 +459,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -472,7 +472,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -486,7 +485,6 @@ SPC5_ME_MC_IRCON | \
SPC5_ME_MC_XOSC0ON | \
SPC5_ME_MC_PLL0ON | \
- SPC5_ME_MC_PLL1ON | \
SPC5_ME_MC_CFLAON_NORMAL | \
SPC5_ME_MC_DFLAON_NORMAL | \
SPC5_ME_MC_MVRON)
@@ -738,6 +736,7 @@ #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
#endif
+#if SPC5_HAS_FMPLL1
/* Check on SPC5_FMPLL1_IDF_VALUE.*/
#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
@@ -783,7 +782,9 @@ #if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
#endif
+#endif /* SPC5_HAS_FMPLL1 */
+#if SPC5_HAS_AC0 || defined(__DOXYGEN__)
/**
* @brief AUX0 clock point.
*/
@@ -799,6 +800,10 @@ #error "invalid SPC5_AUX0CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1)
+#error "SPC5_AUX0CLK_SRC, FMPLL1 not present"
+#endif
+
/* Check on the AUX0 divider 0 settings.*/
#if SPC5_MCONTROL_DIVIDER_VALUE == 0
#define SPC5_CGM_AC0_DC0 0
@@ -816,7 +821,9 @@ #else
#define SPC5_MCONTROL_CLK 0
#endif
+#endif /* #if SPC5_HAS_AC0 */
+#if SPC5_HAS_AC1 || defined(__DOXYGEN__)
/**
* @brief AUX1 clock point.
*/
@@ -826,6 +833,10 @@ #error "invalid SPC5_AUX1CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1
+#error "SPC5_AUX1_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX1 divider 0 settings.*/
#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC1_DC0 0
@@ -843,7 +854,9 @@ #else
#define SPC5_FMPLL1_DIV_CLK 0
#endif
+#endif /* SPC5_HAS_AC1 */
+#if SPC5_HAS_AC2 || defined(__DOXYGEN__)
/**
* @brief AUX2 clock point.
*/
@@ -861,6 +874,11 @@ #error "invalid SPC5_AUX2CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1) || \
+ (SPC5_AUX2_CLK == SPC5_CGM_SS_FMPLL1_1D1))
+#error "SPC5_AUX2_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX2 divider 0 settings.*/
#if SPC5_SP_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC2_DC0 0
@@ -878,7 +896,9 @@ #else
#define SPC5_SP_CLK 0
#endif
+#endif /* SPC5_HAS_AC2 */
+#if SPC5_HAS_AC3 || defined(__DOXYGEN__)
/**
* @brief AUX3 clock point.
*/
@@ -896,6 +916,11 @@ #error "invalid SPC5_AUX3CLK_SRC value specified"
#endif
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) || \
+ (SPC5_AUX3_CLK == SPC5_CGM_SS_FMPLL1_1D1))
+#error "SPC5_AUX3_CLK, FMPLL1 not present"
+#endif
+
/* Check on the AUX3 divider 0 settings.*/
#if SPC5_FR_CLK_DIVIDER_VALUE == 0
#define SPC5_CGM_AC3_DC0 0
@@ -913,6 +938,7 @@ #else
#define SPC5_FR_CLK 0
#endif
+#endif /* SPC5_HAS_AC3 */
/*===========================================================================*/
/* Driver data structures and types. */
|