GPT driver model, STM32 GPT driver implementation, not tested, documentation not done yet.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2779 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 698 insertions, 23 deletions

diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c
new file mode 100644
index 000000000..1278400a1
--- /dev/null
+++ b/os/hal/platforms/STM32/gpt_lld.c
@@ -0,0 +1,415 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    STM32/gpt_lld.c

+ * @brief   STM32 GPT subsystem low level driver source.

+ *

+ * @addtogroup GPT

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+#if HAL_USE_GPT || defined(__DOXYGEN__)

+

+/* There are differences in vector names in the ST header for devices

+   including TIM15, TIM16, TIM17.*/

+#if STM32_HAS_TIM15

+#define TIM1_BRK_IRQn       TIM1_BRK_TIM15_IRQn

+#endif

+#if STM32_HAS_TIM16

+#define TIM1_UP_IRQn        TIM1_UP_TIM16_IRQn

+#endif

+#if STM32_HAS_TIM17

+#define TIM1_TRG_COM_IRQn   TIM1_TRG_COM_TIM17_IRQn

+#endif

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   GPT1 driver identifier.

+ * @note    The driver GPT1 allocates the complex timer TIM1 when enabled.

+ */

+#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)

+GPTDriver GPTD1;

+#endif

+

+/**

+ * @brief   GPT2 driver identifier.

+ * @note    The driver GPT2 allocates the timer TIM2 when enabled.

+ */

+#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)

+GPTDriver GPTD2;

+#endif

+

+/**

+ * @brief   GPT3 driver identifier.

+ * @note    The driver GPT3 allocates the timer TIM3 when enabled.

+ */

+#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)

+GPTDriver GPTD3;

+#endif

+

+/**

+ * @brief   GPT4 driver identifier.

+ * @note    The driver GPT4 allocates the timer TIM4 when enabled.

+ */

+#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)

+GPTDriver GPTD4;

+#endif

+

+/**

+ * @brief   GPT5 driver identifier.

+ * @note    The driver GPT5 allocates the timer TIM5 when enabled.

+ */

+#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)

+GPTDriver GPTD5;

+#endif

+

+/*===========================================================================*/

+/* Driver local variables.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/**

+ * @brief   Shared IRQ handler.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ */

+static void gpt_lld_serve_interrupt(GPTDriver *gptp) {

+

+  gptp->tim->SR = 0;

+  if (gptp->state == GPT_ONESHOT) {

+    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */

+    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */

+  }

+  gptp->config->callback(gptp);

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+#if STM32_GPT_USE_TIM1

+/**

+ * @brief   TIM2 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM1_UP_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD1);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_GPT_USE_TIM1 */

+

+#if STM32_GPT_USE_TIM2

+/**

+ * @brief   TIM2 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM2_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD2);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_GPT_USE_TIM2 */

+

+#if STM32_GPT_USE_TIM3

+/**

+ * @brief   TIM3 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM3_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD3);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_GPT_USE_TIM3 */

+

+#if STM32_GPT_USE_TIM4

+/**

+ * @brief   TIM4 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM4_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD4);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_GPT_USE_TIM4 */

+

+#if STM32_GPT_USE_TIM5

+/**

+ * @brief   TIM5 interrupt handler.

+ *

+ * @isr

+ */

+CH_IRQ_HANDLER(TIM5_IRQHandler) {

+

+  CH_IRQ_PROLOGUE();

+

+  gpt_lld_serve_interrupt(&GPTD5);

+

+  CH_IRQ_EPILOGUE();

+}

+#endif /* STM32_GPT_USE_TIM5 */

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level GPT driver initialization.

+ *

+ * @notapi

+ */

+void gpt_lld_init(void) {

+

+#if STM32_GPT_USE_TIM1

+  /* Driver initialization.*/

+  GPTD1.tim = TIM1;

+  gptObjectInit(&GPTD1);

+#endif

+

+#if STM32_GPT_USE_TIM2

+  /* Driver initialization.*/

+  GPTD2.tim = TIM2;

+  gptObjectInit(&GPTD2);

+#endif

+

+#if STM32_GPT_USE_TIM3

+  /* Driver initialization.*/

+  GPTD3.tim = TIM3;

+  gptObjectInit(&GPTD3);

+#endif

+

+#if STM32_GPT_USE_TIM4

+  /* Driver initialization.*/

+  GPTD4.tim = TIM4;

+  gptObjectInit(&GPTD4);

+#endif

+

+#if STM32_GPT_USE_TIM5

+  /* Driver initialization.*/

+  GPTD5.tim = TIM5;

+  gptObjectInit(&GPTD5);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the GPT peripheral.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_start(GPTDriver *gptp) {

+  uint16_t psc;

+

+  if (gptp->state == GPT_STOP) {

+    /* Clock activation.*/

+#if STM32_GPT_USE_TIM1

+    if (&GPTD1 == gptp) {

+      RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;

+      RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;

+      RCC->APB2RSTR = 0;

+      NVICEnableVector(TIM1_UP_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));

+      gptp->clock = STM32_TIMCLK2;

+    }

+#endif

+#if STM32_GPT_USE_TIM2

+    if (&GPTD2 == gptp) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM2_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));

+      gptp->clock = STM32_TIMCLK1;

+    }

+#endif

+#if STM32_GPT_USE_TIM3

+    if (&GPTD3 == gptp) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM3_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));

+      gptp->clock = STM32_TIMCLK1;

+    }

+#endif

+#if STM32_GPT_USE_TIM4

+    if (&GPTD4 == gptp) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM4_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));

+      gptp->clock = STM32_TIMCLK1;

+    }

+#endif

+

+#if STM32_GPT_USE_TIM5

+    if (&GPTD5 == gptp) {

+      RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;

+      RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;

+      RCC->APB1RSTR = 0;

+      NVICEnableVector(TIM5_IRQn,

+                       CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));

+      gptp->clock = STM32_TIMCLK1;

+    }

+#endif

+  }

+

+  /* Prescaler value calculation.*/

+  psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);

+  chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,

+              "gpt_lld_start(), #1", "invalid frequency");

+

+  /* Timer configuration.*/

+  gptp->tim->CR1  = 0;                      /* Initially stopped.           */

+  gptp->tim->CR2  = TIM_CR2_CCDS;           /* DMA on UE (if any).          */

+  gptp->tim->PSC  = psc;                    /* Prescaler value.             */

+  gptp->tim->DIER = 0;

+}

+

+/**

+ * @brief   Deactivates the GPT peripheral.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_stop(GPTDriver *gptp) {

+

+  if (gptp->state == GPT_READY) {

+    gptp->tim->CR1  = 0;                    /* Timer disabled.              */

+    gptp->tim->DIER = 0;                    /* All IRQs disabled.           */

+

+#if STM32_GPT_USE_TIM1

+    if (&GPTD1 == gptp) {

+      NVICDisableVector(TIM1_UP_IRQn);

+      RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;

+    }

+#endif

+#if STM32_GPT_USE_TIM2

+    if (&GPTD2 == gptp) {

+      NVICDisableVector(TIM2_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;

+    }

+#endif

+#if STM32_GPT_USE_TIM3

+    if (&GPTD3 == gptp) {

+      NVICDisableVector(TIM3_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;

+    }

+#endif

+#if STM32_GPT_USE_TIM4

+    if (&GPTD4 == gptp) {

+      NVICDisableVector(TIM4_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;

+    }

+#endif

+#if STM32_GPT_USE_TIM5

+    if (&GPTD5 == gptp) {

+      NVICDisableVector(TIM5_IRQn);

+      RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;

+    }

+#endif

+  }

+}

+

+/**

+ * @brief   Starts the timer in continuous mode.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ * @param[in] interval  period in ticks

+ *

+ * @notapi

+ */

+void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {

+

+  gptp->tim->ARR  = interval - 1;           /* Time constant.               */

+  gptp->tim->EGR  = TIM_EGR_UG;             /* Update event.                */

+  gptp->tim->SR   = 0;                      /* Clear pending IRQs (if any). */

+  gptp->tim->DIER = TIM_DIER_UIE;           /* Update Event IRQ enabled.    */

+  gptp->tim->CR1  = TIM_CR1_URS | TIM_CR1_CEN;

+}

+

+/**

+ * @brief   Stops the timer.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ *

+ * @notapi

+ */

+void gpt_lld_stop_timer(GPTDriver *gptp) {

+

+  gptp->tim->CR1  = 0;                      /* Initially stopped.           */

+  gptp->tim->SR   = 0;                      /* Clear pending IRQs (if any). */

+  gptp->tim->DIER = 0;                      /* Interrupts disabled.         */

+}

+

+/**

+ * @brief   Starts the timer in one shot mode and waits for completion.

+ * @details This function specifically polls the timer waiting for completion

+ *          in order to not have extra delays caused by interrupt servicing,

+ *          this function is only recommended for short delays.

+ *

+ * @param[in] gptp      pointer to the @p GPTDriver object

+ * @param[in] interval  time interval in ticks

+ *

+ * @notapi

+ */

+void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {

+

+  gptp->tim->ARR  = interval - 1;           /* Time constant.               */

+  gptp->tim->EGR  = TIM_EGR_UG;             /* Update event.                */

+  gptp->tim->SR   = 0;                      /* Clear pending IRQs (if any). */

+  gptp->tim->CR1  = TIM_CR1_OPM | TIM_CR1_URS | TIM_CR1_CEN;

+  while (!(gptp->tim->SR & TIM_SR_UIF))

+    ;

+}

+

+#endif /* HAL_USE_GPT */

+

+/** @} */

diff --git a/os/hal/platforms/STM32/gpt_lld.h b/os/hal/platforms/STM32/gpt_lld.h
new file mode 100644
index 000000000..1eb67318b
--- /dev/null
+++ b/os/hal/platforms/STM32/gpt_lld.h
@@ -0,0 +1,264 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    STM32/gpt_lld.h

+ * @brief   STM32 GPT subsystem low level driver header.

+ *

+ * @addtogroup GPT

+ * @{

+ */

+

+#ifndef _GPT_LLD_H_

+#define _GPT_LLD_H_

+

+#if HAL_USE_GPT || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   GPT1 driver enable switch.

+ * @details If set to @p TRUE the support for GPT1 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM1) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM1                  TRUE

+#endif

+

+/**

+ * @brief   GPT2 driver enable switch.

+ * @details If set to @p TRUE the support for GPT2 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM2) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM2                  TRUE

+#endif

+

+/**

+ * @brief   GPT3 driver enable switch.

+ * @details If set to @p TRUE the support for GPT3 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM3) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM3                  TRUE

+#endif

+

+/**

+ * @brief   GPT4 driver enable switch.

+ * @details If set to @p TRUE the support for GPT4 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM4) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM4                  TRUE

+#endif

+

+/**

+ * @brief   GPT5 driver enable switch.

+ * @details If set to @p TRUE the support for GPT5 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM5) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM5                  TRUE

+#endif

+

+/**

+ * @brief   GPT1 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM1_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPT2 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM2_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPT3 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM3_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPT4 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM4_IRQ_PRIORITY         7

+#endif

+

+/**

+ * @brief   GPT5 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM5_IRQ_PRIORITY         7

+#endif

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if STM32_GPT_USE_TIM1 && !STM32_HAS_TIM1

+#error "TIM1 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM2 && !STM32_HAS_TIM2

+#error "TIM2 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM3 && !STM32_HAS_TIM3

+#error "TIM3 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM4 && !STM32_HAS_TIM4

+#error "TIM4 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM5 && !STM32_HAS_TIM5

+#error "TIM5 not present in the selected device"

+#endif

+

+#if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 &&                           \

+    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&                           \

+    !STM32_GPT_USE_TIM5

+#error "GPT driver activated but no TIM peripheral assigned"

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   GPT frequency type.

+ */

+typedef uint32_t gptfreq_t;

+

+/**

+ * @brief   GPT counter type.

+ */

+typedef uint16_t gptcnt_t;

+

+/**

+ * @brief   Type of a structure representing a GPT driver.

+ */

+typedef struct GPTDriver GPTDriver;

+

+/**

+ * @brief   GPT notification callback type.

+ *

+ * @param[in] gptp      pointer to a @p GPTDriver object

+ */

+typedef void (*gptcallback_t)(GPTDriver *gptp);

+

+/**

+ * @brief   Driver configuration structure.

+ * @note    It could be empty on some architectures.

+ */

+typedef struct {

+  /**

+   * @brief   Timer clock in Hz.

+   * @note    The low level can use assertions in order to catch invalid

+   *          frequency specifications.

+   */

+  gptfreq_t                 frequency;

+  /**

+   * @brief   Timer callback pointer.

+   * @note    This callback is invoked on GPT counter events.

+   */

+  gptcallback_t             callback;

+  /* End of the mandatory fields.*/

+} GPTConfig;

+

+/**

+ * @brief   Structure representing a GPT driver.

+ */

+struct GPTDriver {

+  /**

+   * @brief Driver state.

+   */

+  gptstate_t                state;

+  /**

+   * @brief Current configuration data.

+   */

+  const GPTConfig           *config;

+  /* End of the mandatory fields.*/

+  /**

+   * @brief Timer base clock.

+   */

+  uint32_t                  clock;

+  /**

+   * @brief Pointer to the TIMx registers block.

+   */

+  TIM_TypeDef               *tim;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if STM32_GPT_USE_TIM1 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD1;

+#endif

+

+#if STM32_GPT_USE_TIM2 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD2;

+#endif

+

+#if STM32_GPT_USE_TIM3 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD3;

+#endif

+

+#if STM32_GPT_USE_TIM4 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD4;

+#endif

+

+#if STM32_GPT_USE_TIM5 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD5;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void gpt_lld_init(void);

+  void gpt_lld_start(GPTDriver *gptp);

+  void gpt_lld_stop(GPTDriver *gptp);

+  void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);

+  void gpt_lld_stop_timer(GPTDriver *gptp);

+  void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_GPT */

+

+#endif /* _GPT_LLD_H_ */

+

+/** @} */

diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c
index 8d8322033..cbbdf1587 100644
--- a/os/hal/platforms/STM32/hal_lld.c
+++ b/os/hal/platforms/STM32/hal_lld.c
@@ -57,6 +57,12 @@
  */

 void hal_lld_init(void) {

 

+  /* Reset of all the peripherals.*/

+  RCC->APB1RSTR = 0xFFFFFFFF;

+  RCC->APB2RSTR = 0xFFFFFFFF;

+  RCC->APB1RSTR = 0;

+  RCC->APB2RSTR = 0;

+

   /* SysTick initialization using the system clock.*/

   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

   SysTick->VAL = 0;

diff --git a/os/hal/platforms/STM32/platform.mk b/os/hal/platforms/STM32/platform.mk
index ceadcea62..469b85c79 100644
--- a/os/hal/platforms/STM32/platform.mk
+++ b/os/hal/platforms/STM32/platform.mk
@@ -2,6 +2,7 @@
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/adc_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \

+              ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/pal_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \

diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index f78896e95..a101b284a 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -101,6 +101,8 @@ PWMDriver PWMD5;
  * @note    It is assumed that the various sources are only activated if the

  *          associated callback pointer is not equal to @p NULL in order to not

  *          perform an extra check in a potentially critical interrupt handler.

+ *

+ * @param[in] pwmp      pointer to a @p PWMDriver object

  */

 static void serve_interrupt(PWMDriver *pwmp) {

   uint16_t sr;

@@ -249,10 +251,6 @@ CH_IRQ_HANDLER(TIM5_IRQHandler) {
 void pwm_lld_init(void) {

 

 #if STM32_PWM_USE_TIM1

-  /* TIM1 reset, ensures reset state in order to avoid trouble with JTAGs.*/

-  RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;

-  RCC->APB2RSTR = 0;

-

   /* Driver initialization.*/

   pwmObjectInit(&PWMD1);

   PWMD1.pd_enabled_channels = 0;

@@ -260,10 +258,6 @@ void pwm_lld_init(void) {
 #endif

 

 #if STM32_PWM_USE_TIM2

-  /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

-  RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;

-  RCC->APB1RSTR = 0;

-

   /* Driver initialization.*/

   pwmObjectInit(&PWMD2);

   PWMD2.pd_enabled_channels = 0;

@@ -271,10 +265,6 @@ void pwm_lld_init(void) {
 #endif

 

 #if STM32_PWM_USE_TIM3

-  /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

-  RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;

-  RCC->APB1RSTR = 0;

-

   /* Driver initialization.*/

   pwmObjectInit(&PWMD3);

   PWMD3.pd_enabled_channels = 0;

@@ -282,10 +272,6 @@ void pwm_lld_init(void) {
 #endif

 

 #if STM32_PWM_USE_TIM4

-  /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

-  RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;

-  RCC->APB1RSTR = 0;

-

   /* Driver initialization.*/

   pwmObjectInit(&PWMD4);

   PWMD4.pd_enabled_channels = 0;

@@ -293,10 +279,6 @@ void pwm_lld_init(void) {
 #endif

 

 #if STM32_PWM_USE_TIM5

-  /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

-  RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;

-  RCC->APB1RSTR = 0;

-

   /* Driver initialization.*/

   pwmObjectInit(&PWMD5);

   PWMD5.pd_enabled_channels = 0;

@@ -368,7 +350,6 @@ void pwm_lld_start(PWMDriver *pwmp) {
     }

 #endif

 

-

     /* All channels configured in PWM1 mode with preload enabled and will

        stay that way until the driver is stopped.*/

     pwmp->pd_tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |

@@ -448,6 +429,7 @@ void pwm_lld_start(PWMDriver *pwmp) {
  * @notapi

  */

 void pwm_lld_stop(PWMDriver *pwmp) {

+

   /* If in ready state then disables the PWM clock.*/

   if (pwmp->pd_state == PWM_READY) {

     pwmp->pd_enabled_channels = 0;          /* All channels disabled.       */

diff --git a/os/hal/platforms/STM32/usb_lld.c b/os/hal/platforms/STM32/usb_lld.c
index eb3d6ab7a..ecd183171 100644
--- a/os/hal/platforms/STM32/usb_lld.c
+++ b/os/hal/platforms/STM32/usb_lld.c
@@ -29,7 +29,6 @@
 

 #include "ch.h"

 #include "hal.h"

-#include "usb.h"

 

 #if HAL_USE_USB || defined(__DOXYGEN__)

 

@@ -513,6 +512,10 @@ void usb_lld_disable_endpoints(USBDriver *usbp) {
  *

  * @param[in] usbp      pointer to the @p USBDriver object

  * @param[in] ep        endpoint number

+ * @return              The endpoint status.

+ * @retval EP_STATUS_DISABLED The endpoint is not active.

+ * @retval EP_STATUS_STALLED  The endpoint is stalled.

+ * @retval EP_STATUS_ACTIVE   The endpoint is active.

  *

  * @notapi

  */

@@ -534,6 +537,10 @@ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
  *

  * @param[in] usbp      pointer to the @p USBDriver object

  * @param[in] ep        endpoint number

+ * @return              The endpoint status.

+ * @retval EP_STATUS_DISABLED The endpoint is not active.

+ * @retval EP_STATUS_STALLED  The endpoint is stalled.

+ * @retval EP_STATUS_ACTIVE   The endpoint is active.

  *

  * @notapi

  */

diff --git a/os/hal/platforms/STM32/usb_lld.h b/os/hal/platforms/STM32/usb_lld.h
index a505e3e08..9c4c899b3 100644
--- a/os/hal/platforms/STM32/usb_lld.h
+++ b/os/hal/platforms/STM32/usb_lld.h
@@ -296,7 +296,7 @@ struct USBDriver {
  *

  * @notapi

  */

-#define usb_lld_fetch_word(p) (*(uint16_t *)p)

+#define usb_lld_fetch_word(p) (*(uint16_t *)(p))

 

 /**

  * @brief   Returns the current frame number.