Fixed bugs 3534767, 3534819, 3535887 and 3535938.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4293 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 39 insertions, 29 deletions

diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
index 2799aab85..2a91009c5 100644
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@@ -265,6 +265,9 @@ void mac_lld_init(void) {
 #else

   /* PHY soft reset procedure.*/

   mii_write(&ETHD1, MII_BMCR, BMCR_RESET);

+#if defined(BOARD_PHY_RESET_DELAY)

+  halPolledDelay(BOARD_PHY_RESET_DELAY);

+#endif

   while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)

     ;

 #endif

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 113b89fe1..06a2a2737 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -372,11 +372,14 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
 

   dmaStreamSetMemory0(spip->dmarx, &dummyrx);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);

 

   dmaStreamSetMemory0(spip->dmatx, &dummytx);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);

+

+  dmaStreamEnable(spip->dmarx);

+  dmaStreamEnable(spip->dmatx);

 }

 

 /**

@@ -399,12 +402,14 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
 

   dmaStreamSetMemory0(spip->dmarx, rxbuf);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC |

-                                                 STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);

+

   dmaStreamSetMemory0(spip->dmatx, txbuf);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |

-                                                  STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);

+

+  dmaStreamEnable(spip->dmarx);

+  dmaStreamEnable(spip->dmatx);

 }

 

 /**

@@ -424,12 +429,14 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
 

   dmaStreamSetMemory0(spip->dmarx, &dummyrx);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode);

 

   dmaStreamSetMemory0(spip->dmatx, txbuf);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |

-                                                  STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);

+

+  dmaStreamEnable(spip->dmarx);

+  dmaStreamEnable(spip->dmatx);

 }

 

 /**

@@ -449,11 +456,14 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
 

   dmaStreamSetMemory0(spip->dmarx, rxbuf);

   dmaStreamSetTransactionSize(spip->dmarx, n);

-  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC |

-                                                  STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);

+

   dmaStreamSetMemory0(spip->dmatx, &dummytx);

   dmaStreamSetTransactionSize(spip->dmatx, n);

-  dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);

+  dmaStreamSetMode(spip->dmatx, spip->txdmamode);

+

+  dmaStreamEnable(spip->dmarx);

+  dmaStreamEnable(spip->dmatx);

 }

 

 /**

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 7f8414743..dcc7c64f0 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -151,8 +151,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

   /* The shared vector is initialized on driver initialization and never

@@ -265,6 +264,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

                                             (uint32_t)adcp->depth);

   dmaStreamSetMode(adcp->dmastp, mode);

+  dmaStreamEnable(adcp->dmastp);

 

   /* ADC setup, if it is defined a callback for the analog watch dog then it

      is enabled.*/

diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c
index 6913cf8fa..c5fb252a8 100644
--- a/os/hal/platforms/STM32F1xx/adc_lld.c
+++ b/os/hal/platforms/STM32F1xx/adc_lld.c
@@ -97,7 +97,7 @@ void adc_lld_init(void) {
   ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_TEIE        | STM32_DMA_CR_EN;

+                  STM32_DMA_CR_TEIE;

 

   /* Temporary activation.*/

   rccEnableADC1(FALSE);

@@ -199,6 +199,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetMemory0(adcp->dmastp, adcp->samples);

   dmaStreamSetTransactionSize(adcp->dmastp, n);

   dmaStreamSetMode(adcp->dmastp, mode);

+  dmaStreamEnable(adcp->dmastp);

 

   /* ADC setup.*/

   adcp->adc->CR1   = grpp->cr1 | ADC_CR1_SCAN;

diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c
index 4601b6d74..937b26727 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.c
+++ b/os/hal/platforms/STM32F2xx/adc_lld.c
@@ -186,8 +186,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_ADC_USE_ADC2

@@ -200,8 +199,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_ADC_USE_ADC3

@@ -214,8 +212,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

   /* The shared vector is initialized on driver initialization and never

@@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

                                             (uint32_t)adcp->depth);

   dmaStreamSetMode(adcp->dmastp, mode);

+  dmaStreamEnable(adcp->dmastp);

 

   /* ADC setup.*/

   adcp->adc->SR    = 0;

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 64a139026..fbeaf22ec 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -186,8 +186,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_ADC_USE_ADC2

@@ -200,8 +199,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

 #if STM32_ADC_USE_ADC3

@@ -214,8 +212,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

   /* The shared vector is initialized on driver initialization and never

@@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

                                             (uint32_t)adcp->depth);

   dmaStreamSetMode(adcp->dmastp, mode);

+  dmaStreamEnable(adcp->dmastp);

 

   /* ADC setup.*/

   adcp->adc->SR    = 0;

diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c
index c8092589e..cd24b2583 100644
--- a/os/hal/platforms/STM32L1xx/adc_lld.c
+++ b/os/hal/platforms/STM32L1xx/adc_lld.c
@@ -129,8 +129,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |

                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |

-                  STM32_DMA_CR_EN;

+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

 #endif

 

   /* The shared vector is initialized on driver initialization and never

@@ -217,6 +216,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

                                             (uint32_t)adcp->depth);

   dmaStreamSetMode(adcp->dmastp, mode);

+  dmaStreamEnable(adcp->dmastp);

 

   /* ADC setup.*/

   adcp->adc->SR    = 0;