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-rw-r--r--boards/ST_STM32F4_DISCOVERY/board.h2
-rw-r--r--os/hal/include/adc.h6
-rw-r--r--os/hal/platforms/STM32/mac_lld.c3
-rw-r--r--os/hal/platforms/STM32/spi_lld.c34
-rw-r--r--os/hal/platforms/STM32F0xx/adc_lld.c4
-rw-r--r--os/hal/platforms/STM32F1xx/adc_lld.c3
-rw-r--r--os/hal/platforms/STM32F2xx/adc_lld.c10
-rw-r--r--os/hal/platforms/STM32F4xx/adc_lld.c10
-rw-r--r--os/hal/platforms/STM32L1xx/adc_lld.c4
-rw-r--r--os/hal/src/mmc_spi.c4
-rw-r--r--readme.txt6
11 files changed, 52 insertions, 34 deletions
diff --git a/boards/ST_STM32F4_DISCOVERY/board.h b/boards/ST_STM32F4_DISCOVERY/board.h
index 56511b6d7..07e84348e 100644
--- a/boards/ST_STM32F4_DISCOVERY/board.h
+++ b/boards/ST_STM32F4_DISCOVERY/board.h
@@ -259,7 +259,7 @@
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOC_ODR 0xFFFFFFFF
-#define VAL_GPIOC_AFRL PIN_AFIO_AF(GPIOC_MCLK, 6))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_MCLK, 6))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SCLK, 6) | \
PIN_AFIO_AF(GPIOC_SDIN, 6))
diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h
index 8f829d386..86209a89f 100644
--- a/os/hal/include/adc.h
+++ b/os/hal/include/adc.h
@@ -210,7 +210,8 @@ typedef enum {
if ((adcp)->depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->depth / 2; \
- (adcp)->grpp->end_cb(adcp, (adcp)->samples + half, half); \
+ size_t half_index = half * (adcp)->grpp->num_channels; \
+ (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \
@@ -226,7 +227,8 @@ typedef enum {
if ((adcp)->depth > 1) { \
/* Invokes the callback passing the 2nd half of the buffer.*/ \
size_t half = (adcp)->depth / 2; \
- (adcp)->grpp->end_cb(adcp, (adcp)->samples + half, half); \
+ size_t half_index = half * (adcp)->grpp->num_channels; \
+ (adcp)->grpp->end_cb(adcp, (adcp)->samples + half_index, half); \
} \
else { \
/* Invokes the callback passing the whole buffer.*/ \
diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
index 2799aab85..2a91009c5 100644
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@@ -265,6 +265,9 @@ void mac_lld_init(void) {
#else
/* PHY soft reset procedure.*/
mii_write(&ETHD1, MII_BMCR, BMCR_RESET);
+#if defined(BOARD_PHY_RESET_DELAY)
+ halPolledDelay(BOARD_PHY_RESET_DELAY);
+#endif
while (mii_read(&ETHD1, MII_BMCR) & BMCR_RESET)
;
#endif
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 113b89fe1..06a2a2737 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -372,11 +372,14 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
- dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
- dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+ dmaStreamEnable(spip->dmarx);
+ dmaStreamEnable(spip->dmatx);
}
/**
@@ -399,12 +402,14 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
- dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC |
- STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC);
+
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
- dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
- STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+ dmaStreamEnable(spip->dmarx);
+ dmaStreamEnable(spip->dmatx);
}
/**
@@ -424,12 +429,14 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
dmaStreamSetMemory0(spip->dmarx, &dummyrx);
dmaStreamSetTransactionSize(spip->dmarx, n);
- dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmarx, spip->rxdmamode);
dmaStreamSetMemory0(spip->dmatx, txbuf);
dmaStreamSetTransactionSize(spip->dmatx, n);
- dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC |
- STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_MINC);
+
+ dmaStreamEnable(spip->dmarx);
+ dmaStreamEnable(spip->dmatx);
}
/**
@@ -449,11 +456,14 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
dmaStreamSetMemory0(spip->dmarx, rxbuf);
dmaStreamSetTransactionSize(spip->dmarx, n);
- dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC |
- STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC);
+
dmaStreamSetMemory0(spip->dmatx, &dummytx);
dmaStreamSetTransactionSize(spip->dmatx, n);
- dmaStreamSetMode(spip->dmatx, spip->txdmamode | STM32_DMA_CR_EN);
+ dmaStreamSetMode(spip->dmatx, spip->txdmamode);
+
+ dmaStreamEnable(spip->dmarx);
+ dmaStreamEnable(spip->dmatx);
}
/**
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 7f8414743..dcc7c64f0 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -151,8 +151,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@@ -265,6 +264,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/
diff --git a/os/hal/platforms/STM32F1xx/adc_lld.c b/os/hal/platforms/STM32F1xx/adc_lld.c
index 6913cf8fa..c5fb252a8 100644
--- a/os/hal/platforms/STM32F1xx/adc_lld.c
+++ b/os/hal/platforms/STM32F1xx/adc_lld.c
@@ -97,7 +97,7 @@ void adc_lld_init(void) {
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_TEIE | STM32_DMA_CR_EN;
+ STM32_DMA_CR_TEIE;
/* Temporary activation.*/
rccEnableADC1(FALSE);
@@ -199,6 +199,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
dmaStreamSetTransactionSize(adcp->dmastp, n);
dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.c b/os/hal/platforms/STM32F2xx/adc_lld.c
index 4601b6d74..937b26727 100644
--- a/os/hal/platforms/STM32F2xx/adc_lld.c
+++ b/os/hal/platforms/STM32F2xx/adc_lld.c
@@ -186,8 +186,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC2
@@ -200,8 +199,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC3
@@ -214,8 +212,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 64a139026..fbeaf22ec 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -186,8 +186,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC2
@@ -200,8 +199,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
#if STM32_ADC_USE_ADC3
@@ -214,8 +212,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@@ -338,6 +335,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;
diff --git a/os/hal/platforms/STM32L1xx/adc_lld.c b/os/hal/platforms/STM32L1xx/adc_lld.c
index c8092589e..cd24b2583 100644
--- a/os/hal/platforms/STM32L1xx/adc_lld.c
+++ b/os/hal/platforms/STM32L1xx/adc_lld.c
@@ -129,8 +129,7 @@ void adc_lld_init(void) {
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
- STM32_DMA_CR_EN;
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
@@ -217,6 +216,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
+ dmaStreamEnable(adcp->dmastp);
/* ADC setup.*/
adcp->adc->SR = 0;
diff --git a/os/hal/src/mmc_spi.c b/os/hal/src/mmc_spi.c
index cb045bcb4..0be587d14 100644
--- a/os/hal/src/mmc_spi.c
+++ b/os/hal/src/mmc_spi.c
@@ -423,13 +423,13 @@ void mmcObjectInit(MMCDriver *mmcp) {
* @brief Configures and activates the MMC peripheral.
*
* @param[in] mmcp pointer to the @p MMCDriver object
- * @param[in] config pointer to the @p MMCConfig object. Must be @p NULL.
+ * @param[in] config pointer to the @p MMCConfig object.
*
* @api
*/
void mmcStart(MMCDriver *mmcp, const MMCConfig *config) {
- chDbgCheck((mmcp != NULL) && (config == NULL), "mmcStart");
+ chDbgCheck((mmcp != NULL) && (config != NULL), "mmcStart");
chSysLock();
chDbgAssert(mmcp->state == MMC_STOP, "mmcStart(), #1", "invalid state");
diff --git a/readme.txt b/readme.txt
index 0c98ab9d6..0dc65d935 100644
--- a/readme.txt
+++ b/readme.txt
@@ -81,6 +81,12 @@
*****************************************************************************
*** 2.5.0 ***
+- FIX: Fixed issue with DMA channel init in STM32 ADC and SPI drivers (bug
+ 3535938)(backported to 2.2.10 and 2.4.2).
+- FIX: Fixed issue debugging mmc_spi (bug 3535887)(trunk only).
+- FIX: Fixed unreliable PHY initialization (bug 3534819)(backported to 2.4.2).
+- FIX: Fixed wrong ADC callback buffer pointer in ADC driver (bug 3534767)
+ (backported to 2.2.10 and 2.4.2).
- FIX: Fixed STM32F2 RTC subseconds (bug 3533414)(trunk only).
- FIX: Fixed problem with arm-v6m and state checker (bug 3532591)(backported
to 2.4.2).
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 04:09:02 +0000