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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-04 22:00:44 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-04 22:00:44 +0000 |
| commit | 45c0b7f9bc8d295ac8bfd97cbe14f9bd10756a30 (patch) | |
| tree | fbe7dfe5a4b5b7ada42bb33d6153f4fdc1515a4b /os/hal/platforms/STM32F4xx | |
| parent | 05b919403101cc7395776aa24b92369564c91968 (diff) | |
| download | ChibiOS-45c0b7f9bc8d295ac8bfd97cbe14f9bd10756a30.tar.gz ChibiOS-45c0b7f9bc8d295ac8bfd97cbe14f9bd10756a30.tar.bz2 ChibiOS-45c0b7f9bc8d295ac8bfd97cbe14f9bd10756a30.zip | |
Documentation related fixes and updated all the mcuconf.h for the STM32.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3735 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F4xx')
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 14 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/stm32_rcc.h | 14 |
3 files changed, 15 insertions, 15 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index 71b8ad219..02905b6bd 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -78,7 +78,7 @@ void hal_lld_init(void) { dmaInit();
#endif
- /* Programmable voltage detector enable. */
+ /* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
rccEnablePWRInterface(FALSE);
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 953a7af45..43549fdd9 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -139,13 +139,13 @@ #define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
/** @} */
/**
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index a20274b26..be600e44f 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -256,7 +256,7 @@ /** @} */
/**
- * @brief ADC peripherals specific RCC operations
+ * @name ADC peripherals specific RCC operations
* @{
*/
/**
@@ -336,7 +336,7 @@ /** @} */
/**
- * @brief DMA peripheral specific RCC operations
+ * @name DMA peripheral specific RCC operations
* @{
*/
/**
@@ -391,7 +391,7 @@ /** @} */
/**
- * @brief PWR interface specific RCC operations
+ * @name PWR interface specific RCC operations
* @{
*/
/**
@@ -423,7 +423,7 @@ /** @} */
/**
- * @brief I2C peripherals specific RCC operations
+ * @name I2C peripherals specific RCC operations
* @{
*/
/**
@@ -503,7 +503,7 @@ /** @} */
/**
- * @brief SPI peripherals specific RCC operations
+ * @name SPI peripherals specific RCC operations
* @{
*/
/**
@@ -583,7 +583,7 @@ /** @} */
/**
- * @brief TIM peripherals specific RCC operations
+ * @name TIM peripherals specific RCC operations
* @{
*/
/**
@@ -744,7 +744,7 @@ /** @} */
/**
- * @brief USART/UART peripherals specific RCC operations
+ * @name USART/UART peripherals specific RCC operations
* @{
*/
/**
|