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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-16 17:04:28 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-05-16 17:04:28 +0000 |
| commit | b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee (patch) | |
| tree | dbc62d2195ea244aa5ef58e4af2a19ee5e737b83 /os/hal/platforms/STM32F1xx | |
| parent | 63f071bb5945b01f653ccceda09e48376dbc2263 (diff) | |
| download | ChibiOS-b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee.tar.gz ChibiOS-b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee.tar.bz2 ChibiOS-b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4201 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld.h | 1 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 13 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f103.h | 8 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 13 |
4 files changed, 23 insertions, 12 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index c8d87b7c5..466d389b8 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -25,6 +25,7 @@ * @p board.h file:
* - STM32_LSECLK.
* - STM32_HSECLK.
+ * - STM32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
* - STM32F10X_LD_VL for Value Line Low Density devices.
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 25dd3a186..5875279c2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -152,10 +152,10 @@ #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
-#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
-#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
-#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
-#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
+#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
@@ -168,7 +168,12 @@ #define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+/** @} */
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index deda9f67a..8e35114ff 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -159,10 +159,10 @@ #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
-#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
-#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
-#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
-#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
+#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 57b47f003..bce886c44 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -167,10 +167,10 @@ #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
-#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
-#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
-#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
-#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
+#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_PREDIV1 (1 << 16) /**< PLL clock source is
@@ -188,7 +188,12 @@ #define STM32_MCOSEL_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
#define STM32_MCOSEL_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
#define STM32_MCOSEL_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
+/** @} */
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
|