diff options
Diffstat (limited to 'os/hal/platforms/STM32F1xx/hal_lld_f100.h')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 25dd3a186..5875279c2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -152,10 +152,10 @@ #define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
-#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
-#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
-#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
-#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
+#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
+#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
+#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
+#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
@@ -168,7 +168,12 @@ #define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+/** @} */
+/**
+ * @name RCC_BDCR register bits definitions
+ * @{
+ */
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
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