diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-23 19:58:04 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-23 19:58:04 +0000 |
| commit | 4286b14a9e6d82823c8e5c759495575b1b7fa5ef (patch) | |
| tree | 95b7b32d5c28daf3c564dce1b7e4d5ad913c9359 /os/hal/platforms/STM32F1xx | |
| parent | e241378765ef67e3c804753a54a30e1e6b4431e3 (diff) | |
| download | ChibiOS-4286b14a9e6d82823c8e5c759495575b1b7fa5ef.tar.gz ChibiOS-4286b14a9e6d82823c8e5c759495575b1b7fa5ef.tar.bz2 ChibiOS-4286b14a9e6d82823c8e5c759495575b1b7fa5ef.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3520 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 29 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f103.h | 116 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 29 |
3 files changed, 174 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 91be2eadb..3f5d9502b 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -212,11 +212,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 FALSE
+#define STM32_USART3_RX_DMA_MSK 0
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK 0
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 FALSE
+#define STM32_UART4_RX_DMA_MSK 0
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK 0
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 FALSE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB FALSE
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 4090502a1..22d955c65 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -223,11 +223,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 FALSE
+#define STM32_USART3_RX_DMA_MSK 0
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK 0
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 FALSE
+#define STM32_UART4_RX_DMA_MSK 0
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK 0
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 FALSE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB FALSE
@@ -326,11 +355,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 FALSE
+#define STM32_UART4_RX_DMA_MSK 0
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK 0
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 FALSE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB TRUE
@@ -429,11 +487,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB TRUE
@@ -532,11 +619,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB TRUE
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index dff2f7b2e..882ec6094 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -215,11 +215,40 @@ /* USART attributes.*/
#define STM32_HAS_USART1 TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART2 TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART3 TRUE
+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART4 TRUE
+#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
+#define STM32_UART4_RX_DMA_CHN 0x00000000
+#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
+#define STM32_UART4_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_UART5 TRUE
+#define STM32_UART5_RX_DMA_MSK 0
+#define STM32_UART5_RX_DMA_CHN 0x00000000
+#define STM32_UART5_TX_DMA_MSK 0
+#define STM32_UART5_TX_DMA_CHN 0x00000000
+
#define STM32_HAS_USART6 FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB FALSE
|