git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3520 35acf78f-673a-0410-8e92-d51de3d6d3f4

10 files changed, 424 insertions, 56 deletions

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 2610031b6..34a892d48 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -99,7 +99,7 @@ static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) {
 

   /* DMA errors handling.*/

 #if defined(STM32_SPI_DMA_ERROR_HOOK)

-  if ((flags & STM32_DMA_ISR_TEIF) != 0) {

+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {

     STM32_SPI_DMA_ERROR_HOOK(spip);

   }

 #else

diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h
index e10a5edce..ee2586ea1 100644
--- a/os/hal/platforms/STM32/spi_lld.h
+++ b/os/hal/platforms/STM32/spi_lld.h
@@ -71,6 +71,27 @@
 #endif

 

 /**

+ * @brief   SPI1 interrupt priority level setting.

+ */

+#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

+#endif

+

+/**

+ * @brief   SPI2 interrupt priority level setting.

+ */

+#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

+#endif

+

+/**

+ * @brief   SPI3 interrupt priority level setting.

+ */

+#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

+#endif

+

+/**

  * @brief   SPI1 DMA priority (0..3|lowest..highest).

  * @note    The priority level is used for both the TX and RX DMA streams but

  *          because of the streams ordering the RX stream has always priority

@@ -101,27 +122,6 @@
 #endif

 

 /**

- * @brief   SPI1 interrupt priority level setting.

- */

-#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI_SPI1_IRQ_PRIORITY         10

-#endif

-

-/**

- * @brief   SPI2 interrupt priority level setting.

- */

-#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI_SPI2_IRQ_PRIORITY         10

-#endif

-

-/**

- * @brief   SPI3 interrupt priority level setting.

- */

-#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI_SPI3_IRQ_PRIORITY         10

-#endif

-

-/**

  * @brief   SPI DMA error hook.

  */

 #if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

@@ -175,7 +175,7 @@
  * @note    This option is only available on platforms with enhanced DMA.

  */

 #if !defined(STM32_SPI_SPI3_TX_DMA_STREAM) || defined(__DOXYGEN__)

-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

 #endif

 

 #else /* !STM32_ADVANCED_DMA */

diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c
index 3841be8fa..be63fc695 100644
--- a/os/hal/platforms/STM32/uart_lld.c
+++ b/os/hal/platforms/STM32/uart_lld.c
@@ -32,6 +32,34 @@
 #if HAL_USE_UART || defined(__DOXYGEN__)

 

 /*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+#define USART1_RX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_RX_DMA_STREAM,                     \

+                       STM32_USART1_RX_DMA_CHN)

+

+#define USART1_TX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART1_TX_DMA_STREAM,                     \

+                       STM32_USART1_TX_DMA_CHN)

+

+#define USART2_RX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_RX_DMA_STREAM,                     \

+                       STM32_USART2_RX_DMA_CHN)

+

+#define USART2_TX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART2_TX_DMA_STREAM,                     \

+                       STM32_USART2_TX_DMA_CHN)

+

+#define USART3_RX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_RX_DMA_STREAM,                     \

+                       STM32_USART3_RX_DMA_CHN)

+

+#define USART3_TX_DMA_CHANNEL                                               \

+  STM32_DMA_GETCHANNEL(STM32_UART_USART3_TX_DMA_STREAM,                     \

+                       STM32_USART3_TX_DMA_CHN)

+

+/*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

 

@@ -92,10 +120,9 @@ static void set_rx_idle_loop(UARTDriver *uartp) {
   /* RX DMA channel preparation, if the char callback is defined then the

      TCIE interrupt is enabled too.*/

   if (uartp->config->rxchar_cb == NULL)

-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE;

+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC;

   else

-    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TEIE |

-           STM32_DMA_CR_TCIE;

+    mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE;

   dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf);

   dmaStreamSetTransactionSize(uartp->dmarx, 1);

   dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode);

@@ -172,7 +199,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
 

   /* DMA errors handling.*/

 #if defined(STM32_UART_DMA_ERROR_HOOK)

-  if ((flags & STM32_DMA_ISR_TEIF) != 0) {

+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {

     STM32_UART_DMA_ERROR_HOOK(uartp);

   }

 #else

@@ -192,6 +219,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) {
     uartp->rxstate = UART_RX_COMPLETE;

     if (uartp->config->rxend_cb != NULL)

       uartp->config->rxend_cb(uartp);

+

     /* If the callback didn't explicitly change state then the receiver

        automatically returns to the idle state.*/

     if (uartp->rxstate == UART_RX_COMPLETE) {

@@ -211,7 +239,7 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
 

   /* DMA errors handling.*/

 #if defined(STM32_UART_DMA_ERROR_HOOK)

-  if ((flags & STM32_DMA_ISR_TEIF) != 0) {

+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {

     STM32_UART_DMA_ERROR_HOOK(uartp);

   }

 #else

@@ -219,10 +247,12 @@ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) {
 #endif

 

   dmaStreamDisable(uartp->dmatx);

+

   /* A callback is generated, if enabled, after a completed transfer.*/

   uartp->txstate = UART_TX_COMPLETE;

   if (uartp->config->txend1_cb != NULL)

     uartp->config->txend1_cb(uartp);

+

   /* If the callback didn't explicitly change state then the transmitter

      automatically returns to the idle state.*/

   if (uartp->txstate == UART_TX_COMPLETE)

@@ -248,6 +278,7 @@ static void serve_usart_irq(UARTDriver *uartp) {
   }

   if (sr & USART_SR_TC) {

     u->SR = ~USART_SR_TC;

+

     /* End of transmission, a callback is generated.*/

     if (uartp->config->txend2_cb != NULL)

       uartp->config->txend2_cb(uartp);

@@ -320,22 +351,22 @@ void uart_lld_init(void) {
 #if STM32_UART_USE_USART1

   uartObjectInit(&UARTD1);

   UARTD1.usart   = USART1;

-  UARTD1.dmarx   = STM32_DMA1_STREAM5;

-  UARTD1.dmatx   = STM32_DMA1_STREAM4;

+  UARTD1.dmarx   = STM32_DMA_STREAM(STM32_UART_USART1_RX_DMA_STREAM);

+  UARTD1.dmatx   = STM32_DMA_STREAM(STM32_UART_USART1_TX_DMA_STREAM);

 #endif

 

 #if STM32_UART_USE_USART2

   uartObjectInit(&UARTD2);

   UARTD2.usart   = USART2;

-  UARTD2.dmarx   = STM32_DMA1_STREAM6;

-  UARTD2.dmatx   = STM32_DMA1_STREAM7;

+  UARTD2.dmarx   = STM32_DMA_STREAM(STM32_UART_USART2_RX_DMA_STREAM);

+  UARTD2.dmatx   = STM32_DMA_STREAM(STM32_UART_USART2_TX_DMA_STREAM);

 #endif

 

 #if STM32_UART_USE_USART3

   uartObjectInit(&UARTD3);

   UARTD3.usart   = USART3;

-  UARTD3.dmarx   = STM32_DMA1_STREAM3;

-  UARTD3.dmatx   = STM32_DMA1_STREAM2;

+  UARTD3.dmarx   = STM32_DMA_STREAM(STM32_UART_USART3_RX_DMA_STREAM);

+  UARTD3.dmatx   = STM32_DMA_STREAM(STM32_UART_USART3_TX_DMA_STREAM);

 #endif

 }

 

@@ -348,35 +379,39 @@ void uart_lld_init(void) {
  */

 void uart_lld_start(UARTDriver *uartp) {

 

+  uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;

+

   if (uartp->state == UART_STOP) {

 #if STM32_UART_USE_USART1

     if (&UARTD1 == uartp) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA1_STREAM4,

+      b = dmaStreamAllocate(uartp->dmarx,

                             STM32_UART_USART1_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,

+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

                             (void *)uartp);

       chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA1_STREAM5,

+      b = dmaStreamAllocate(uartp->dmatx,

                             STM32_UART_USART1_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,

                             (void *)uartp);

       chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");

       rccEnableUSART1(FALSE);

       NVICEnableVector(USART1_IRQn,

                        CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));

+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |

+                        STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);

     }

 #endif

 

 #if STM32_UART_USE_USART2

     if (&UARTD2 == uartp) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA1_STREAM6,

+      b = dmaStreamAllocate(uartp->dmarx,

                             STM32_UART_USART2_IRQ_PRIORITY,

                             (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

                             (void *)uartp);

       chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA1_STREAM7,

+      b = dmaStreamAllocate(uartp->dmatx,

                             STM32_UART_USART2_IRQ_PRIORITY,

                             (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,

                             (void *)uartp);

@@ -384,31 +419,34 @@ void uart_lld_start(UARTDriver *uartp) {
       rccEnableUSART2(FALSE);

       NVICEnableVector(USART2_IRQn,

                        CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));

+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |

+                        STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);

     }

 #endif

 

 #if STM32_UART_USE_USART3

     if (&UARTD3 == uartp) {

       bool_t b;

-      b = dmaStreamAllocate(STM32_DMA1_STREAM2,

+      b = dmaStreamAllocate(uartp->dmarx,

                             STM32_UART_USART3_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,

+                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

                             (void *)uartp);

       chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");

-      b = dmaStreamAllocate(STM32_DMA1_STREAM3,

+      b = dmaStreamAllocate(uartp->dmatx,

                             STM32_UART_USART3_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,

+                            (stm32_dmaisr_t)uart_lld_serve_tx_end_irq,

                             (void *)uartp);

       chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");

       rccEnableUSART3(FALSE);

       NVICEnableVector(USART3_IRQn,

                        CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));

+      uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |

+                        STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);

     }

 #endif

 

     /* Static DMA setup, the transfer size depends on the USART settings,

        it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/

-    uartp->dmamode = STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);

     if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)

       uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;

     dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);

@@ -432,11 +470,11 @@ void uart_lld_stop(UARTDriver *uartp) {
 

   if (uartp->state == UART_READY) {

     usart_stop(uartp);

+    dmaStreamRelease(uartp->dmarx);

+    dmaStreamRelease(uartp->dmatx);

 

 #if STM32_UART_USE_USART1

     if (&UARTD1 == uartp) {

-      dmaStreamRelease(STM32_DMA1_STREAM4);

-      dmaStreamRelease(STM32_DMA1_STREAM5);

       NVICDisableVector(USART1_IRQn);

       rccDisableUSART1(FALSE);

       return;

@@ -445,8 +483,6 @@ void uart_lld_stop(UARTDriver *uartp) {
 

 #if STM32_UART_USE_USART2

     if (&UARTD2 == uartp) {

-      dmaStreamRelease(STM32_DMA1_STREAM6);

-      dmaStreamRelease(STM32_DMA1_STREAM7);

       NVICDisableVector(USART2_IRQn);

       rccDisableUSART2(FALSE);

       return;

@@ -455,8 +491,6 @@ void uart_lld_stop(UARTDriver *uartp) {
 

 #if STM32_UART_USE_USART3

     if (&UARTD3 == uartp) {

-      dmaStreamRelease(STM32_DMA1_STREAM2);

-      dmaStreamRelease(STM32_DMA1_STREAM3);

       NVICDisableVector(USART3_IRQn);

       rccDisableUSART3(FALSE);

       return;

@@ -482,8 +516,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
   dmaStreamSetMemory0(uartp->dmatx, txbuf);

   dmaStreamSetTransactionSize(uartp->dmatx, n);

   dmaStreamSetMode(uartp->dmatx, uartp->dmamode    | STM32_DMA_CR_DIR_M2P |

-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE    |

-                                 STM32_DMA_CR_TCIE);

+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);

   dmaStreamEnable(uartp->dmatx);

 }

 

@@ -526,8 +559,7 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
   dmaStreamSetMemory0(uartp->dmarx, rxbuf);

   dmaStreamSetTransactionSize(uartp->dmarx, n);

   dmaStreamSetMode(uartp->dmarx, uartp->dmamode    | STM32_DMA_CR_DIR_P2M |

-                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TEIE    |

-                                 STM32_DMA_CR_TCIE);

+                                 STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE);

   dmaStreamEnable(uartp->dmarx);

 }

 

diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h
index d97bea91b..742a8a37d 100644
--- a/os/hal/platforms/STM32/uart_lld.h
+++ b/os/hal/platforms/STM32/uart_lld.h
@@ -110,6 +110,7 @@
 #if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_UART_USART2_DMA_PRIORITY      0

 #endif

+

 /**

  * @brief   USART3 DMA priority (0..3|lowest..highest).

  * @note    The priority level is used for both the TX and RX DMA channels but

@@ -128,6 +129,69 @@
 #if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

 #define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

 #endif

+

+#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)

+

+/**

+ * @brief   DMA stream used for USART1 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)

+#endif

+

+/**

+ * @brief   DMA stream used for USART1 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)

+#endif

+

+/**

+ * @brief   DMA stream used for USART2 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

+#endif

+

+/**

+ * @brief   DMA stream used for USART2 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#endif

+

+/**

+ * @brief   DMA stream used for USART3 RX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)

+#endif

+

+/**

+ * @brief   DMA stream used for USART3 TX operations.

+ * @note    This option is only available on platforms with enhanced DMA.

+ */

+#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#endif

+

+#else /* !STM32_ADVANCED_DMA */

+

+/* Fixed streams for platforms using the old DMA peripheral, the values are

+   valid for both STM32F1xx and STM32L1xx.*/

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

+

+#endif /* !STM32_ADVANCED_DMA*/

 /** @} */

 

 /*===========================================================================*/

@@ -151,6 +215,42 @@
 #error "UART driver activated but no USART/UART peripheral assigned"

 #endif

 

+#if STM32_UART_USE_USART1 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM,                 \

+                           STM32_USART1_RX_DMA_MSK)

+#error "invalid DMA stream associated to USART1 RX"

+#endif

+

+#if STM32_UART_USE_USART1 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM,                 \

+                           STM32_USART1_TX_DMA_MSK)

+#error "invalid DMA stream associated to USART1 TX"

+#endif

+

+#if STM32_UART_USE_USART2 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM,                 \

+                           STM32_USART2_RX_DMA_MSK)

+#error "invalid DMA stream associated to USART2 RX"

+#endif

+

+#if STM32_UART_USE_USART2 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM,                 \

+                           STM32_USART2_TX_DMA_MSK)

+#error "invalid DMA stream associated to USART2 TX"

+#endif

+

+#if STM32_UART_USE_USART3 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM,                 \

+                           STM32_USART3_RX_DMA_MSK)

+#error "invalid DMA stream associated to USART3 RX"

+#endif

+

+#if STM32_UART_USE_USART3 &&                                                \

+    !STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM,                 \

+                           STM32_USART3_TX_DMA_MSK)

+#error "invalid DMA stream associated to USART3 TX"

+#endif

+

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

 #endif

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 91be2eadb..3f5d9502b 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -212,11 +212,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        FALSE

+#define STM32_USART3_RX_DMA_MSK 0

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK 0

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         FALSE

+#define STM32_UART4_RX_DMA_MSK  0

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  0

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         FALSE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           FALSE

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
index 4090502a1..22d955c65 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
@@ -223,11 +223,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        FALSE

+#define STM32_USART3_RX_DMA_MSK 0

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK 0

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         FALSE

+#define STM32_UART4_RX_DMA_MSK  0

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  0

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         FALSE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           FALSE

@@ -326,11 +355,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         FALSE

+#define STM32_UART4_RX_DMA_MSK  0

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  0

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         FALSE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           TRUE

@@ -429,11 +487,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         TRUE

+#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         TRUE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           TRUE

@@ -532,11 +619,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         TRUE

+#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         TRUE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           TRUE

diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index dff2f7b2e..882ec6094 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -215,11 +215,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         TRUE

+#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         TRUE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           FALSE

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index 5edac0163..a4bfac99f 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -80,7 +80,7 @@ ADCDriver ADCD3;
 static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {

 

   /* DMA errors handling.*/

-  if ((flags & STM32_DMA_ISR_TEIF) != 0) {

+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {

     /* DMA, this could help only if the DMA tries to access an unmapped

        address space or violates alignment rules.*/

     _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 71207efd5..bdb8cb86b 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -349,11 +349,44 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |            \

+                                 STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00400400

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_USART1_TX_DMA_CHN 0x40000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART2_RX_DMA_CHN 0x00400000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_TX_DMA_CHN 0x04000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))

+#define STM32_USART3_RX_DMA_CHN 0x00400400

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \

+                                 STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART3_TX_DMA_CHN 0x00074040

+

 #define STM32_HAS_UART4         TRUE

+#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_UART4_RX_DMA_CHN  0x00000400

+#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_UART4_TX_DMA_CHN  0x00040000

+

 #define STM32_HAS_UART5         TRUE

+#define STM32_UART5_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 0))

+#define STM32_UART5_RX_DMA_CHN  0x00000004

+#define STM32_UART5_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_UART5_TX_DMA_CHN  0x40000000

+

 #define STM32_HAS_USART6        TRUE

+#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |            \

+                                 STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_USART6_RX_DMA_CHN 0x00000550

+#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |            \

+                                 STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_USART6_TX_DMA_CHN 0x55000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           FALSE

diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index d62176a16..b6b0060d6 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -251,11 +251,40 @@
 

 /* USART attributes.*/

 #define STM32_HAS_USART1        TRUE

+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_USART1_RX_DMA_CHN 0x00000000

+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

+#define STM32_USART1_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART2        TRUE

+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_USART2_RX_DMA_CHN 0x00000000

+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_USART3        TRUE

+#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_USART3_RX_DMA_CHN 0x00000000

+#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_USART3_TX_DMA_CHN 0x00000000

+

 #define STM32_HAS_UART4         FALSE

+#define STM32_UART4_RX_DMA_MSK  0

+#define STM32_UART4_RX_DMA_CHN  0x00000000

+#define STM32_UART4_TX_DMA_MSK  0

+#define STM32_UART4_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_UART5         FALSE

+#define STM32_UART5_RX_DMA_MSK  0

+#define STM32_UART5_RX_DMA_CHN  0x00000000

+#define STM32_UART5_TX_DMA_MSK  0

+#define STM32_UART5_TX_DMA_CHN  0x00000000

+

 #define STM32_HAS_USART6        FALSE

+#define STM32_USART6_RX_DMA_MSK 0

+#define STM32_USART6_RX_DMA_CHN 0x00000000

+#define STM32_USART6_TX_DMA_MSK 0

+#define STM32_USART6_TX_DMA_CHN 0x00000000

 

 /* USB attributes.*/

 #define STM32_HAS_USB           TRUE