Backup domain and RTC clock initialization added.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3785 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 10 insertions, 16 deletions

diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index bf3baca8a..f5efeed5d 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
   /* Backup domain access enabled during initialization.*/

   PWR->CR |= PWR_CR_DBP;

 

-  /* RTC clock initialization.*/

-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK

-  /* RTC clock not required, backup domain reset as initialization.*/

-  RCC->BDCR = RCC_BDCR_BDRST;

-  RCC->BDCR = 0;

-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

-  /* If the backup domain hasn't been initialized yet then proceed with

-     initialization.*/

-  if (!(RCC->BDCR & RCC_BDCR_LSEON)) {

+  /* If enabled then the LSE is started.*/

+#if STM32_LSE_ENABLED

+  if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {

     /* Backup domain reset.*/

     RCC->BDCR = RCC_BDCR_BDRST;

-    RCC->BDCR = 0;

-

-    /* If enabled then the LSE is started.*/

-#if STM32_LSE_ENABLED

-    RCC->BDCR |= RCC_BDCR_LSEON;

+    RCC->BDCR = RCC_BDCR_LSEON;

     while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

       ;                                     /* Waits until LSE is stable.   */

+  }

 #endif

 

+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK

+  /* If the backup domain hasn't been initialized yet then proceed with

+     initialization.*/

+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {

     /* Selects clock source.*/

     RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;

 

-    /* RTC enabled regardless its previous status, this will also prevent

-       successive initializations.*/

+    /* RTC clock enabled.*/

     RCC->BDCR |= RCC_BDCR_RTCEN;

   }

 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */