aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld.c26
-rw-r--r--os/hal/platforms/STM32F2xx/hal_lld.c26
-rw-r--r--os/hal/platforms/STM32F4xx/hal_lld.c26
-rw-r--r--os/hal/platforms/STM32L1xx/hal_lld.c26
4 files changed, 40 insertions, 64 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index bf3baca8a..f5efeed5d 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled during initialization.*/
PWR->CR |= PWR_CR_DBP;
- /* RTC clock initialization.*/
-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
- /* RTC clock not required, backup domain reset as initialization.*/
- RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
- /* If the backup domain hasn't been initialized yet then proceed with
- initialization.*/
- if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
- RCC->BDCR |= RCC_BDCR_LSEON;
+ RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
+ }
#endif
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
- /* RTC enabled regardless its previous status, this will also prevent
- successive initializations.*/
+ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c
index b517795f2..b9af01a92 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.c
+++ b/os/hal/platforms/STM32F2xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled during initialization.*/
PWR->CR |= PWR_CR_DBP;
- /* RTC clock initialization.*/
-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
- /* RTC clock not required, backup domain reset as initialization.*/
- RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
- /* If the backup domain hasn't been initialized yet then proceed with
- initialization.*/
- if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
- RCC->BDCR |= RCC_BDCR_LSEON;
+ RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
+ }
#endif
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
- /* RTC enabled regardless its previous status, this will also prevent
- successive initializations.*/
+ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index a655231cd..d26059d70 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled during initialization.*/
PWR->CR |= PWR_CR_DBP;
- /* RTC clock initialization.*/
-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
- /* RTC clock not required, backup domain reset as initialization.*/
- RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
- /* If the backup domain hasn't been initialized yet then proceed with
- initialization.*/
- if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
- RCC->BDCR |= RCC_BDCR_LSEON;
+ RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
+ }
#endif
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
- /* RTC enabled regardless its previous status, this will also prevent
- successive initializations.*/
+ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c
index b87620293..01d61fbc2 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.c
+++ b/os/hal/platforms/STM32L1xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled during initialization.*/
PWR->CR |= PWR_CR_DBP;
- /* RTC clock initialization.*/
-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
- /* RTC clock not required, backup domain reset as initialization.*/
- RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
- /* If the backup domain hasn't been initialized yet then proceed with
- initialization.*/
- if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
- RCC->BDCR = 0;
-
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
- RCC->BDCR |= RCC_BDCR_LSEON;
+ RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
+ }
#endif
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+ /* If the backup domain hasn't been initialized yet then proceed with
+ initialization.*/
+ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
- /* RTC enabled regardless its previous status, this will also prevent
- successive initializations.*/
+ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 22:01:51 +0000