diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-03 18:02:48 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-03 18:02:48 +0000 |
| commit | 6d159cc390ec49136915ed124750a1c2f26b8f47 (patch) | |
| tree | dd9b173847b5a48694fd9cae609c363c4f37d053 /os/hal/platforms/STM32F1xx/hal_lld_f100.h | |
| parent | a8feb8613bd20eea8031ae6c8a62ac67ec750a02 (diff) | |
| download | ChibiOS-6d159cc390ec49136915ed124750a1c2f26b8f47.tar.gz ChibiOS-6d159cc390ec49136915ed124750a1c2f26b8f47.tar.bz2 ChibiOS-6d159cc390ec49136915ed124750a1c2f26b8f47.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3462 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32F1xx/hal_lld_f100.h')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f100.h | 185 |
1 files changed, 184 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 012cf0c11..864be581e 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -40,10 +40,35 @@ /* Driver constants. */
/*===========================================================================*/
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32 Value Line"
+
+#elif defined(STM32F10X_LD_VL)
+#define PLATFORM_NAME "STM32 Value Line Low Density"
+
+#elif defined(STM32F10X_MD_VL)
+#define PLATFORM_NAME "STM32 Value Line Medium Density"
+#else
+#error "unsupported STM32 Value Line member"
+#endif
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
+/** @} */
-/* RCC_CFGR register bits definitions.*/
+/**
+ * @name RCC_CFGR register bits definitions
+ * @{
+ */
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
@@ -92,11 +117,168 @@ #define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
+/** @} */
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F100 LD capabilities
+ * @{
+ */
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+
+#define STM32_HAS_DAC TRUE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+#define STM32_HAS_ETH FALSE
+
+#define STM32_EXTI_NUM_CHANNELS 19
+
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+#define STM32_HAS_I2C1 TRUE
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+
+#define STM32_HAS_RTC TRUE
+
+#define STM32_HAS_SDIO FALSE
+
+#define STM32_HAS_SPI1 TRUE
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_HAS_TIM2 TRUE
+#define STM32_HAS_TIM3 TRUE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 TRUE
+#define STM32_HAS_TIM7 TRUE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 TRUE
+#define STM32_HAS_TIM16 TRUE
+#define STM32_HAS_TIM17 TRUE
+
+#define STM32_HAS_USART1 TRUE
+#define STM32_HAS_USART2 TRUE
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_LD_VL) */
+
+#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
+/**
+ * @name STM32F100 MD capabilities
+ * @{
+ */
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+
+#define STM32_HAS_DAC TRUE
+
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+#define STM32_HAS_ETH FALSE
+
+#define STM32_EXTI_NUM_CHANNELS 19
+
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF FALSE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+#define STM32_HAS_I2C1 TRUE
+#define STM32_HAS_I2C2 TRUE
+#define STM32_HAS_I2C3 FALSE
+
+#define STM32_HAS_RTC TRUE
+
+#define STM32_HAS_SDIO FALSE
+
+#define STM32_HAS_SPI1 TRUE
+#define STM32_HAS_SPI2 TRUE
+#define STM32_HAS_SPI3 FALSE
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_HAS_TIM2 TRUE
+#define STM32_HAS_TIM3 TRUE
+#define STM32_HAS_TIM4 TRUE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 TRUE
+#define STM32_HAS_TIM7 TRUE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM15 TRUE
+#define STM32_HAS_TIM16 TRUE
+#define STM32_HAS_TIM17 TRUE
+
+#define STM32_HAS_USART1 TRUE
+#define STM32_HAS_USART2 TRUE
+#define STM32_HAS_USART3 TRUE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+/** @} */
+#endif /* defined(STM32F10X_MD_VL) */
/*===========================================================================*/
/* Platform specific friendly IRQ names. */
/*===========================================================================*/
+/**
+ * @name IRQ VECTOR names
+ * @{
+ */
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
detect. */
@@ -149,6 +331,7 @@ #define TIM12_IRQHandler VectorEC /**< TIM12. */
#define TIM13_IRQHandler VectorF0 /**< TIM13. */
#define TIM14_IRQHandler VectorF4 /**< TIM14. */
+/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
|