git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2808 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 48 insertions, 48 deletions

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 1987373ae..53f0ae1c7 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -66,8 +66,8 @@ static uint16_t dummyrx;
  * @param[in] spip      pointer to the @p SPIDriver object

  */

 #define dma_stop(spip) {                                                    \

-  dmaChannelDisable(spip->spd_dmatx);                                       \

-  dmaChannelDisable(spip->spd_dmarx);                                       \

+  dmaChannelDisable(spip->dmatx);                                           \

+  dmaChannelDisable(spip->dmarx);                                           \

 }

 

 /**

@@ -76,8 +76,8 @@ static uint16_t dummyrx;
  * @param[in] spip      pointer to the @p SPIDriver object

  */

 #define dma_start(spip) {                                                   \

-  dmaChannelEnable((spip)->spd_dmarx);                                      \

-  dmaChannelEnable((spip)->spd_dmatx);                                      \

+  dmaChannelEnable((spip)->dmarx);                                          \

+  dmaChannelEnable((spip)->dmatx);                                          \

 }

 

 /**

@@ -219,26 +219,26 @@ void spi_lld_init(void) {
 

 #if STM32_SPI_USE_SPI1

   spiObjectInit(&SPID1);

-  SPID1.spd_thread  = NULL;

-  SPID1.spd_spi     = SPI1;

-  SPID1.spd_dmarx   = STM32_DMA1_CH2;

-  SPID1.spd_dmatx   = STM32_DMA1_CH3;

+  SPID1.thread  = NULL;

+  SPID1.spi     = SPI1;

+  SPID1.dmarx   = STM32_DMA1_CH2;

+  SPID1.dmatx   = STM32_DMA1_CH3;

 #endif

 

 #if STM32_SPI_USE_SPI2

   spiObjectInit(&SPID2);

-  SPID2.spd_thread  = NULL;

-  SPID2.spd_spi     = SPI2;

-  SPID2.spd_dmarx   = STM32_DMA1_CH4;

-  SPID2.spd_dmatx   = STM32_DMA1_CH5;

+  SPID2.thread  = NULL;

+  SPID2.spi     = SPI2;

+  SPID2.dmarx   = STM32_DMA1_CH4;

+  SPID2.dmatx   = STM32_DMA1_CH5;

 #endif

 

 #if STM32_SPI_USE_SPI3

   spiObjectInit(&SPID3);

-  SPID3.spd_thread  = NULL;

-  SPID3.spd_spi     = SPI3;

-  SPID3.spd_dmarx   = STM32_DMA2_CH1;

-  SPID3.spd_dmatx   = STM32_DMA2_CH2;

+  SPID3.thread  = NULL;

+  SPID3.spi     = SPI3;

+  SPID3.dmarx   = STM32_DMA2_CH1;

+  SPID3.dmatx   = STM32_DMA2_CH2;

 #endif

 }

 

@@ -252,7 +252,7 @@ void spi_lld_init(void) {
 void spi_lld_start(SPIDriver *spip) {

 

   /* If in stopped state then enables the SPI and DMA clocks.*/

-  if (spip->spd_state == SPI_STOP) {

+  if (spip->state == SPI_STOP) {

 #if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

@@ -285,23 +285,23 @@ void spi_lld_start(SPIDriver *spip) {
 #endif

 

     /* DMA setup.*/

-    dmaChannelSetPeripheral(spip->spd_dmarx, &spip->spd_spi->DR);

-    dmaChannelSetPeripheral(spip->spd_dmatx, &spip->spd_spi->DR);

+    dmaChannelSetPeripheral(spip->dmarx, &spip->spi->DR);

+    dmaChannelSetPeripheral(spip->dmatx, &spip->spi->DR);

   }

 

   /* More DMA setup.*/

-  if ((spip->spd_config->spc_cr1 & SPI_CR1_DFF) == 0)

-    spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |

+  if ((spip->config->cr1 & SPI_CR1_DFF) == 0)

+    spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |

                        DMA_CCR1_TEIE;               /* 8 bits transfers.    */

   else

-    spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |

+    spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |

                        DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |

                        DMA_CCR1_PSIZE_0;            /* 16 bits transfers.   */

 

   /* SPI setup and enable.*/

-  spip->spd_spi->CR1 = 0;

-  spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;

-  spip->spd_spi->CR1 = spip->spd_config->spc_cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;

+  spip->spi->CR1 = 0;

+  spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;

+  spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;

 }

 

 /**

@@ -314,10 +314,10 @@ void spi_lld_start(SPIDriver *spip) {
 void spi_lld_stop(SPIDriver *spip) {

 

   /* If in ready state then disables the SPI clock.*/

-  if (spip->spd_state == SPI_READY) {

+  if (spip->state == SPI_READY) {

 

     /* SPI disable.*/

-    spip->spd_spi->CR1 = 0;

+    spip->spi->CR1 = 0;

 

 #if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

@@ -355,7 +355,7 @@ void spi_lld_stop(SPIDriver *spip) {
  */

 void spi_lld_select(SPIDriver *spip) {

 

-  palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);

+  palClearPad(spip->config->ssport, spip->config->sspad);

 }

 

 /**

@@ -368,7 +368,7 @@ void spi_lld_select(SPIDriver *spip) {
  */

 void spi_lld_unselect(SPIDriver *spip) {

 

-  palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);

+  palSetPad(spip->config->ssport, spip->config->sspad);

 }

 

 /**

@@ -384,10 +384,10 @@ void spi_lld_unselect(SPIDriver *spip) {
  */

 void spi_lld_ignore(SPIDriver *spip, size_t n) {

 

-  dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,

-                  spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);

-  dmaChannelSetup(spip->spd_dmatx, n, &dummytx,

-                  spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);

+  dmaChannelSetup(spip->dmarx, n, &dummyrx,

+                  spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);

+  dmaChannelSetup(spip->dmatx, n, &dummytx,

+                  spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);

 }

 

 /**

@@ -408,11 +408,11 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) {
 void spi_lld_exchange(SPIDriver *spip, size_t n,

                       const void *txbuf, void *rxbuf) {

 

-  dmaChannelSetup(spip->spd_dmarx, n, rxbuf,

-                  spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |

+  dmaChannelSetup(spip->dmarx, n, rxbuf,

+                  spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |

                   DMA_CCR1_EN);

-  dmaChannelSetup(spip->spd_dmatx, n, txbuf,

-                  spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |

+  dmaChannelSetup(spip->dmatx, n, txbuf,

+                  spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |

                   DMA_CCR1_EN);

 }

 

@@ -431,10 +431,10 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
  */

 void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {

 

-  dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,

-                  spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);

-  dmaChannelSetup(spip->spd_dmatx, n, txbuf,

-                  spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |

+  dmaChannelSetup(spip->dmarx, n, &dummyrx,

+                  spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);

+  dmaChannelSetup(spip->dmatx, n, txbuf,

+                  spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |

                   DMA_CCR1_EN);

 }

 

@@ -453,11 +453,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
  */

 void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {

 

-  dmaChannelSetup(spip->spd_dmarx, n, rxbuf,

-                  spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |

+  dmaChannelSetup(spip->dmarx, n, rxbuf,

+                  spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |

                   DMA_CCR1_EN);

-  dmaChannelSetup(spip->spd_dmatx, n, &dummytx,

-                  spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);

+  dmaChannelSetup(spip->dmatx, n, &dummytx,

+                  spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);

 }

 

 /**

@@ -474,10 +474,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
  */

 uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {

 

-  spip->spd_spi->DR = frame;

-  while ((spip->spd_spi->SR & SPI_SR_RXNE) == 0)

+  spip->spi->DR = frame;

+  while ((spip->spi->SR & SPI_SR_RXNE) == 0)

     ;

-  return spip->spd_spi->DR;

+  return spip->spi->DR;

 }

 

 #endif /* HAL_USE_SPI */