diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-03-08 10:09:57 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-03-08 10:09:57 +0000 |
| commit | 18fb8f676f0f650d83f69bc29ab45b04b73e86c1 (patch) | |
| tree | 5a5668b39a5ddec4981f6dd2d5815d1e706c8471 /os/hal/platforms/STM32 | |
| parent | c3cb79bec35415a930dd017f7c389c57784377ab (diff) | |
| download | ChibiOS-18fb8f676f0f650d83f69bc29ab45b04b73e86c1.tar.gz ChibiOS-18fb8f676f0f650d83f69bc29ab45b04b73e86c1.tar.bz2 ChibiOS-18fb8f676f0f650d83f69bc29ab45b04b73e86c1.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2808 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32')
| -rw-r--r-- | os/hal/platforms/STM32/adc_lld.c | 50 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/adc_lld.h | 46 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/can_lld.c | 136 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/can_lld.h | 80 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/pwm_lld.c | 140 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/pwm_lld.h | 28 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/spi_lld.c | 96 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/spi_lld.h | 26 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/uart_lld.c | 168 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/uart_lld.h | 50 |
10 files changed, 410 insertions, 410 deletions
diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c index d8822e0ab..bbe8051d4 100644 --- a/os/hal/platforms/STM32/adc_lld.c +++ b/os/hal/platforms/STM32/adc_lld.c @@ -95,9 +95,9 @@ void adc_lld_init(void) { #if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
- ADCD1.ad_adc = ADC1;
- ADCD1.ad_dmachp = STM32_DMA1_CH1;
- ADCD1.ad_dmaccr = (STM32_ADC_ADC1_DMA_PRIORITY << 12) |
+ ADCD1.adc = ADC1;
+ ADCD1.dmachp = STM32_DMA1_CH1;
+ ADCD1.dmaccr = (STM32_ADC_ADC1_DMA_PRIORITY << 12) |
DMA_CCR1_EN | DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0 |
DMA_CCR1_MINC | DMA_CCR1_TCIE | DMA_CCR1_TEIE;
@@ -132,21 +132,21 @@ void adc_lld_init(void) { void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then enables the ADC and DMA clocks.*/
- if (adcp->ad_state == ADC_STOP) {
+ if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
NVICEnableVector(DMA1_Channel1_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY));
- dmaChannelSetPeripheral(adcp->ad_dmachp, &ADC1->DR);
+ dmaChannelSetPeripheral(adcp->dmachp, &ADC1->DR);
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
}
#endif
/* ADC setup, the calibration procedure has already been performed
during initialization.*/
- adcp->ad_adc->CR1 = ADC_CR1_SCAN;
- adcp->ad_adc->CR2 = 0;
+ adcp->adc->CR1 = ADC_CR1_SCAN;
+ adcp->adc->CR2 = 0;
}
}
@@ -160,7 +160,7 @@ void adc_lld_start(ADCDriver *adcp) { void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock.*/
- if (adcp->ad_state == ADC_READY) {
+ if (adcp->state == ADC_READY) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
ADC1->CR1 = 0;
@@ -182,34 +182,34 @@ void adc_lld_stop(ADCDriver *adcp) { */
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t ccr, n;
- const ADCConversionGroup *grpp = adcp->ad_grpp;
+ const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
- ccr = adcp->ad_dmaccr;
- if (grpp->acg_circular)
+ ccr = adcp->dmaccr;
+ if (grpp->circular)
ccr |= DMA_CCR1_CIRC;
- if (adcp->ad_depth > 1) {
+ if (adcp->depth > 1) {
/* If the buffer depth is greater than one then the half transfer interrupt
interrupt is enabled in order to allows streaming processing.*/
ccr |= DMA_CCR1_HTIE;
- n = (uint32_t)grpp->acg_num_channels * (uint32_t)adcp->ad_depth;
+ n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth;
}
else
- n = (uint32_t)grpp->acg_num_channels;
- dmaChannelSetup(adcp->ad_dmachp, n, adcp->ad_samples, ccr);
+ n = (uint32_t)grpp->num_channels;
+ dmaChannelSetup(adcp->dmachp, n, adcp->samples, ccr);
/* ADC setup.*/
- adcp->ad_adc->CR1 = grpp->acg_cr1 | ADC_CR1_SCAN;
- adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
+ adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;
+ adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA |
ADC_CR2_CONT | ADC_CR2_ADON;
- adcp->ad_adc->SMPR1 = grpp->acg_smpr1;
- adcp->ad_adc->SMPR2 = grpp->acg_smpr2;
- adcp->ad_adc->SQR1 = grpp->acg_sqr1;
- adcp->ad_adc->SQR2 = grpp->acg_sqr2;
- adcp->ad_adc->SQR3 = grpp->acg_sqr3;
+ adcp->adc->SMPR1 = grpp->smpr1;
+ adcp->adc->SMPR2 = grpp->smpr2;
+ adcp->adc->SQR1 = grpp->sqr1;
+ adcp->adc->SQR2 = grpp->sqr2;
+ adcp->adc->SQR3 = grpp->sqr3;
/* ADC start by writing ADC_CR2_ADON a second time.*/
- adcp->ad_adc->CR2 = grpp->acg_cr2 | ADC_CR2_DMA |
+ adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA |
ADC_CR2_CONT | ADC_CR2_ADON;
}
@@ -222,8 +222,8 @@ void adc_lld_start_conversion(ADCDriver *adcp) { */
void adc_lld_stop_conversion(ADCDriver *adcp) {
- dmaChannelDisable(adcp->ad_dmachp);
- adcp->ad_adc->CR2 = 0;
+ dmaChannelDisable(adcp->dmachp);
+ adcp->adc->CR2 = 0;
}
#endif /* HAL_USE_ADC */
diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h index 876560fca..8f01607d8 100644 --- a/os/hal/platforms/STM32/adc_lld.h +++ b/os/hal/platforms/STM32/adc_lld.h @@ -94,8 +94,8 @@ /**
* @brief ADC1 DMA error hook.
- * @note The default action for DMA errors is a system halt because DMA error
- * can only happen because programming errors.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
*/
#if !defined(STM32_ADC1_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
@@ -154,56 +154,56 @@ typedef struct { /**
* @brief Enables the circular buffer mode for the group.
*/
- bool_t acg_circular;
+ bool_t circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
- adc_channels_num_t acg_num_channels;
+ adc_channels_num_t num_channels;
/**
* @brief Callback function associated to the group or @p NULL.
*/
- adccallback_t acg_endcb;
+ adccallback_t end_cb;
/* End of the mandatory fields.*/
/**
* @brief ADC CR1 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR1_SCAN that is enforced inside the driver.
*/
- uint32_t acg_cr1;
+ uint32_t cr1;
/**
* @brief ADC CR2 register initialization data.
* @note All the required bits must be defined into this field except
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
* enforced inside the driver.
*/
- uint32_t acg_cr2;
+ uint32_t cr2;
/**
* @brief ADC SMPR1 register initialization data.
* @details In this field must be specified the sample times for channels
* 10...17.
*/
- uint32_t acg_smpr1;
+ uint32_t smpr1;
/**
* @brief ADC SMPR2 register initialization data.
* @details In this field must be specified the sample times for channels
* 0...9.
*/
- uint32_t acg_smpr2;
+ uint32_t smpr2;
/**
* @brief ADC SQR1 register initialization data.
* @details Conversion group sequence 13...16 + sequence length.
*/
- uint32_t acg_sqr1;
+ uint32_t sqr1;
/**
* @brief ADC SQR2 register initialization data.
* @details Conversion group sequence 7...12.
*/
- uint32_t acg_sqr2;
+ uint32_t sqr2;
/**
* @brief ADC SQR3 register initialization data.
* @details Conversion group sequence 0...6.
*/
- uint32_t acg_sqr3;
+ uint32_t sqr3;
} ADCConversionGroup;
/**
@@ -221,37 +221,37 @@ struct ADCDriver { /**
* @brief Driver state.
*/
- adcstate_t ad_state;
+ adcstate_t state;
/**
* @brief Current configuration data.
*/
- const ADCConfig *ad_config;
+ const ADCConfig *config;
/**
* @brief Current samples buffer pointer or @p NULL.
*/
- adcsample_t *ad_samples;
+ adcsample_t *samples;
/**
* @brief Current samples buffer depth or @p 0.
*/
- size_t ad_depth;
+ size_t depth;
/**
* @brief Current conversion group pointer or @p NULL.
*/
- const ADCConversionGroup *ad_grpp;
+ const ADCConversionGroup *grpp;
#if ADC_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
- Thread *ad_thread;
+ Thread *thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
- Mutex ad_mutex;
+ Mutex mutex;
#elif CH_USE_SEMAPHORES
- Semaphore ad_semaphore;
+ Semaphore semaphore;
#endif
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
@@ -261,15 +261,15 @@ struct ADCDriver { /**
* @brief Pointer to the ADCx registers block.
*/
- ADC_TypeDef *ad_adc;
+ ADC_TypeDef *adc;
/**
* @brief Pointer to the DMA registers block.
*/
- stm32_dma_channel_t *ad_dmachp;
+ stm32_dma_channel_t *dmachp;
/**
* @brief DMA CCR register bit mask.
*/
- uint32_t ad_dmaccr;
+ uint32_t dmaccr;
};
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c index 5dc7dc572..594471482 100644 --- a/os/hal/platforms/STM32/can_lld.c +++ b/os/hal/platforms/STM32/can_lld.c @@ -63,9 +63,9 @@ CH_IRQ_HANDLER(CAN1_TX_IRQHandler) { /* No more events until a message is transmitted.*/
CAN1->TSR = CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2;
chSysLockFromIsr();
- while (chSemGetCounterI(&CAND1.cd_txsem) < 0)
- chSemSignalI(&CAND1.cd_txsem);
- chEvtBroadcastI(&CAND1.cd_txempty_event);
+ while (chSemGetCounterI(&CAND1.txsem) < 0)
+ chSemSignalI(&CAND1.txsem);
+ chEvtBroadcastI(&CAND1.txempty_event);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
@@ -86,9 +86,9 @@ CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) { /* No more receive events until the queue 0 has been emptied.*/
CAN1->IER &= ~CAN_IER_FMPIE0;
chSysLockFromIsr();
- while (chSemGetCounterI(&CAND1.cd_rxsem) < 0)
- chSemSignalI(&CAND1.cd_rxsem);
- chEvtBroadcastI(&CAND1.cd_rxfull_event);
+ while (chSemGetCounterI(&CAND1.rxsem) < 0)
+ chSemSignalI(&CAND1.rxsem);
+ chEvtBroadcastI(&CAND1.rxfull_event);
chSysUnlockFromIsr();
}
if ((rf0r & CAN_RF0R_FOVR0) > 0) {
@@ -96,7 +96,7 @@ CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) { CAN1->RF0R = CAN_RF0R_FOVR0;
canAddFlagsI(&CAND1, CAN_OVERFLOW_ERROR);
chSysLockFromIsr();
- chEvtBroadcastI(&CAND1.cd_error_event);
+ chEvtBroadcastI(&CAND1.error_event);
chSysUnlockFromIsr();
}
@@ -132,7 +132,7 @@ CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) { /* Wakeup event.*/
if (msr & CAN_MSR_WKUI) {
chSysLockFromIsr();
- chEvtBroadcastI(&CAND1.cd_wakeup_event);
+ chEvtBroadcastI(&CAND1.wakeup_event);
chSysUnlockFromIsr();
}
/* Error event.*/
@@ -146,7 +146,7 @@ CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) { flags |= CAN_FRAMING_ERROR;
chSysLockFromIsr();
canAddFlagsI(&CAND1, flags | (canstatus_t)(flags < 16));
- chEvtBroadcastI(&CAND1.cd_error_event);
+ chEvtBroadcastI(&CAND1.error_event);
chSysUnlockFromIsr();
}
@@ -167,7 +167,7 @@ void can_lld_init(void) { #if STM32_CAN_USE_CAN1
/* Driver initialization.*/
canObjectInit(&CAND1);
- CAND1.cd_can = CAN1;
+ CAND1.can = CAN1;
#endif
}
@@ -196,37 +196,37 @@ void can_lld_start(CANDriver *canp) { #endif
/* Entering initialization mode. */
- canp->cd_state = CAN_STARTING;
- canp->cd_can->MCR = CAN_MCR_INRQ;
- while ((canp->cd_can->MSR & CAN_MSR_INAK) == 0)
+ canp->state = CAN_STARTING;
+ canp->can->MCR = CAN_MCR_INRQ;
+ while ((canp->can->MSR & CAN_MSR_INAK) == 0)
chThdSleepS(1);
/* BTR initialization.*/
- canp->cd_can->BTR = canp->cd_config->cc_btr;
+ canp->can->BTR = canp->config->btr;
/* MCR initialization.*/
- canp->cd_can->MCR = canp->cd_config->cc_mcr;
+ canp->can->MCR = canp->config->mcr;
/* Filters initialization.*/
- canp->cd_can->FMR |= CAN_FMR_FINIT;
- if (canp->cd_config->cc_num > 0) {
+ canp->can->FMR |= CAN_FMR_FINIT;
+ if (canp->config->num > 0) {
uint32_t i, fmask;
CAN_FilterRegister_TypeDef *cfp;
- canp->cd_can->FA1R = 0;
- canp->cd_can->FM1R = 0;
- canp->cd_can->FS1R = 0;
- canp->cd_can->FFA1R = 0;
- cfp = canp->cd_can->sFilterRegister;
+ canp->can->FA1R = 0;
+ canp->can->FM1R = 0;
+ canp->can->FS1R = 0;
+ canp->can->FFA1R = 0;
+ cfp = canp->can->sFilterRegister;
fmask = 1;
for (i = 0; i < CAN_MAX_FILTERS; i++) {
- if (i < canp->cd_config->cc_num) {
- if (canp->cd_config->cc_filters[i].cf_mode)
- canp->cd_can->FM1R |= fmask;
- if (canp->cd_config->cc_filters[i].cf_scale)
- canp->cd_can->FS1R |= fmask;
- if (canp->cd_config->cc_filters[i].cf_assignment)
- canp->cd_can->FFA1R |= fmask;
- cfp->FR1 = canp->cd_config->cc_filters[i].cf_register1;
- cfp->FR2 = canp->cd_config->cc_filters[i].cf_register2;
- canp->cd_can->FA1R |= fmask;
+ if (i < canp->config->num) {
+ if (canp->config->filters[i].mode)
+ canp->can->FM1R |= fmask;
+ if (canp->config->filters[i].scale)
+ canp->can->FS1R |= fmask;
+ if (canp->config->filters[i].assignment)
+ canp->can->FFA1R |= fmask;
+ cfp->FR1 = canp->config->filters[i].register1;
+ cfp->FR2 = canp->config->filters[i].register2;
+ canp->can->FA1R |= fmask;
}
else {
cfp->FR1 = 0;
@@ -241,16 +241,16 @@ void can_lld_start(CANDriver *canp) { }
else {
/* Setup a default filter.*/
- canp->cd_can->sFilterRegister[0].FR1 = 0;
- canp->cd_can->sFilterRegister[0].FR2 = 0;
- canp->cd_can->FM1R = 0;
- canp->cd_can->FFA1R = 0;
- canp->cd_can->FS1R = 1;
- canp->cd_can->FA1R = 1;
+ canp->can->sFilterRegister[0].FR1 = 0;
+ canp->can->sFilterRegister[0].FR2 = 0;
+ canp->can->FM1R = 0;
+ canp->can->FFA1R = 0;
+ canp->can->FS1R = 1;
+ canp->can->FA1R = 1;
}
- canp->cd_can->FMR &= ~CAN_FMR_FINIT;
+ canp->can->FMR &= ~CAN_FMR_FINIT;
/* Interrupt sources initialization.*/
- canp->cd_can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
+ canp->can->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1 |
CAN_IER_WKUIE | CAN_IER_ERRIE | CAN_IER_LECIE |
CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE |
CAN_IER_FOVIE0 | CAN_IER_FOVIE1;
@@ -266,7 +266,7 @@ void can_lld_start(CANDriver *canp) { void can_lld_stop(CANDriver *canp) {
/* If in ready state then disables the CAN peripheral.*/
- if (canp->cd_state == CAN_READY) {
+ if (canp->state == CAN_READY) {
#if STM32_CAN_USE_CAN1
if (&CAND1 == canp) {
CAN1->MCR = 0x00010002; /* Register reset value. */
@@ -294,7 +294,7 @@ void can_lld_stop(CANDriver *canp) { */
bool_t can_lld_can_transmit(CANDriver *canp) {
- return (canp->cd_can->TSR & CAN_TSR_TME) != 0;
+ return (canp->can->TSR & CAN_TSR_TME) != 0;
}
/**
@@ -310,18 +310,18 @@ void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { CAN_TxMailBox_TypeDef *tmbp;
/* Pointer to a free transmission mailbox.*/
- tmbp = &canp->cd_can->sTxMailBox[(canp->cd_can->TSR & CAN_TSR_CODE) >> 24];
+ tmbp = &canp->can->sTxMailBox[(canp->can->TSR & CAN_TSR_CODE) >> 24];
/* Preparing the message.*/
- if (ctfp->cf_IDE)
- tir = ((uint32_t)ctfp->cf_EID << 3) | ((uint32_t)ctfp->cf_RTR << 1) |
+ if (ctfp->IDE)
+ tir = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
CAN_TI0R_IDE;
else
- tir = ((uint32_t)ctfp->cf_SID << 21) | ((uint32_t)ctfp->cf_RTR << 1);
- tmbp->TDTR = ctfp->cf_DLC;
- tmbp->TDLR = ctfp->cf_data32[0];
- tmbp->TDHR = ctfp->cf_data32[1];
- tmbp->TIR = tir | CAN_TI0R_TXRQ;
+ tir = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
+ tmbp->TDTR = ctfp->DLC;
+ tmbp->TDLR = ctfp->data32[0];
+ tmbp->TDHR = ctfp->data32[1];
+ tmbp->TIR = tir | CAN_TI0R_TXRQ;
}
/**
@@ -337,7 +337,7 @@ void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) { */
bool_t can_lld_can_receive(CANDriver *canp) {
- return (canp->cd_can->RF0R & CAN_RF0R_FMP0) > 0;
+ return (canp->can->RF0R & CAN_RF0R_FMP0) > 0;
}
/**
@@ -352,27 +352,27 @@ void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { uint32_t r;
/* Fetches the message.*/
- r = canp->cd_can->sFIFOMailBox[0].RIR;
- crfp->cf_RTR = (r & CAN_RI0R_RTR) >> 1;
- crfp->cf_IDE = (r & CAN_RI0R_IDE) >> 2;
- if (crfp->cf_IDE)
- crfp->cf_EID = r >> 3;
+ r = canp->can->sFIFOMailBox[0].RIR;
+ crfp->RTR = (r & CAN_RI0R_RTR) >> 1;
+ crfp->IDE = (r & CAN_RI0R_IDE) >> 2;
+ if (crfp->IDE)
+ crfp->EID = r >> 3;
else
- crfp->cf_SID = r >> 21;
- r = canp->cd_can->sFIFOMailBox[0].RDTR;
- crfp->cf_DLC = r & CAN_RDT0R_DLC;
- crfp->cf_FMI = (uint8_t)(r >> 8);
- crfp->cf_TIME = (uint16_t)(r >> 16);
- crfp->cf_data32[0] = canp->cd_can->sFIFOMailBox[0].RDLR;
- crfp->cf_data32[1] = canp->cd_can->sFIFOMailBox[0].RDHR;
+ crfp->SID = r >> 21;
+ r = canp->can->sFIFOMailBox[0].RDTR;
+ crfp->DLC = r & CAN_RDT0R_DLC;
+ crfp->FMI = (uint8_t)(r >> 8);
+ crfp->TIME = (uint16_t)(r >> 16);
+ crfp->data32[0] = canp->can->sFIFOMailBox[0].RDLR;
+ crfp->data32[1] = canp->can->sFIFOMailBox[0].RDHR;
/* Releases the mailbox.*/
- canp->cd_can->RF0R = CAN_RF0R_RFOM0;
+ canp->can->RF0R = CAN_RF0R_RFOM0;
/* If the queue is empty re-enables the interrupt in order to generate
events again.*/
- if ((canp->cd_can->RF0R & CAN_RF0R_FMP0) == 0)
- canp->cd_can->IER |= CAN_IER_FMPIE0;
+ if ((canp->can->RF0R & CAN_RF0R_FMP0) == 0)
+ canp->can->IER |= CAN_IER_FMPIE0;
}
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
@@ -385,7 +385,7 @@ void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) { */
void can_lld_sleep(CANDriver *canp) {
- canp->cd_can->MCR |= CAN_MCR_SLEEP;
+ canp->can->MCR |= CAN_MCR_SLEEP;
}
/**
@@ -397,7 +397,7 @@ void can_lld_sleep(CANDriver *canp) { */
void can_lld_wakeup(CANDriver *canp) {
- canp->cd_can->MCR &= ~CAN_MCR_SLEEP;
+ canp->can->MCR &= ~CAN_MCR_SLEEP;
}
#endif /* CAN_USE_SLEEP_MODE */
diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h index 0d4c9b615..2e82c45e3 100644 --- a/os/hal/platforms/STM32/can_lld.h +++ b/os/hal/platforms/STM32/can_lld.h @@ -121,22 +121,22 @@ typedef uint32_t canstatus_t; */
typedef struct {
struct {
- uint8_t cf_DLC:4; /**< @brief Data length. */
- uint8_t cf_RTR:1; /**< @brief Frame type. */
- uint8_t cf_IDE:1; /**< @brief Identifier type. */
+ uint8_t DLC:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
};
union {
struct {
- uint32_t cf_SID:11; /**< @brief Standard identifier.*/
+ uint32_t SID:11; /**< @brief Standard identifier.*/
};
struct {
- uint32_t cf_EID:29; /**< @brief Extended identifier.*/
+ uint32_t EID:29; /**< @brief Extended identifier.*/
};
};
union {
- uint8_t cf_data8[8]; /**< @brief Frame data. */
- uint16_t cf_data16[4]; /**< @brief Frame data. */
- uint32_t cf_data32[2]; /**< @brief Frame data. */
+ uint8_t data8[8]; /**< @brief Frame data. */
+ uint16_t data16[4]; /**< @brief Frame data. */
+ uint32_t data32[2]; /**< @brief Frame data. */
};
} CANTxFrame;
@@ -147,26 +147,26 @@ typedef struct { */
typedef struct {
struct {
- uint8_t cf_FMI; /**< @brief Filter id. */
- uint16_t cf_TIME; /**< @brief Time stamp. */
+ uint8_t FMI; /**< @brief Filter id. */
+ uint16_t TIME; /**< @brief Time stamp. */
};
struct {
- uint8_t cf_DLC:4; /**< @brief Data length. */
- uint8_t cf_RTR:1; /**< @brief Frame type. */
- uint8_t cf_IDE:1; /**< @brief Identifier type. */
+ uint8_t DLC:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
};
union {
struct {
- uint32_t cf_SID:11; /**< @brief Standard identifier.*/
+ uint32_t SID:11; /**< @brief Standard identifier.*/
};
struct {
- uint32_t cf_EID:29; /**< @brief Extended identifier.*/
+ uint32_t EID:29; /**< @brief Extended identifier.*/
};
};
union {
- uint8_t cf_data8[8]; /**< @brief Frame data. */
- uint16_t cf_data16[4]; /**< @brief Frame data. */
- uint32_t cf_data32[2]; /**< @brief Frame data. */
+ uint8_t data8[8]; /**< @brief Frame data. */
+ uint16_t data16[4]; /**< @brief Frame data. */
+ uint32_t data32[2]; /**< @brief Frame data. */
};
} CANRxFrame;
@@ -180,27 +180,27 @@ typedef struct { * @note This bit represent the CAN_FM1R register bit associated to this
* filter (0=mask mode, 1=list mode).
*/
- uint32_t cf_mode:1;
+ uint32_t mode:1;
/**
* @brief Filter sclae.
* @note This bit represent the CAN_FS1R register bit associated to this
* filter (0=16 bits mode, 1=32 bits mode).
*/
- uint32_t cf_scale:1;
+ uint32_t scale:1;
/**
* @brief Filter mode.
* @note This bit represent the CAN_FFA1R register bit associated to this
* filter, must be set to zero in this version of the driver.
*/
- uint32_t cf_assignment:1;
+ uint32_t assignment:1;
/**
* @brief Filter register 1 (identifier).
*/
- uint32_t cf_register1;
+ uint32_t register1;
/**
- * @brief Filter register 2 (mask/identifier depending on cf_mode=0/1).
+ * @brief Filter register 2 (mask/identifier depending on mode=0/1).
*/
- uint32_t cf_register2;
+ uint32_t register2;
} CANFilter;
/**
@@ -212,25 +212,25 @@ typedef struct { * @note Some bits in this register are enforced by the driver regardless
* their status in this field.
*/
- uint32_t cc_mcr;
+ uint32_t mcr;
/**
* @brief CAN BTR register initialization data.
* @note Some bits in this register are enforced by the driver regardless
* their status in this field.
*/
- uint32_t cc_btr;
+ uint32_t btr;
/**
* @brief Number of elements into the filters array.
* @note By setting this field to zero a default filter is enabled that
* allows all frames, this should be adequate for simple applications.
*/
- uint32_t cc_num;
+ uint32_t num;
/**
* @brief Pointer to an array of @p CANFilter structures.
- * @note This field can be set to @p NULL if the field @p cc_num is set to
+ * @note This field can be set to @p NULL if the field @p num is set to
* zero.
*/
- const CANFilter *cc_filters;
+ const CANFilter *filters;
} CANConfig;
/**
@@ -240,19 +240,19 @@ typedef struct { /**
* @brief Driver state.
*/
- canstate_t cd_state;
+ canstate_t state;
/**
* @brief Current configuration data.
*/
- const CANConfig *cd_config;
+ const CANConfig *config;
/**
* @brief Transmission queue semaphore.
*/
- Semaphore cd_txsem;
+ Semaphore txsem;
/**
* @brief Receive queue semaphore.
*/
- Semaphore cd_rxsem;
+ Semaphore rxsem;
/**
* @brief One or more frames become available.
* @note After broadcasting this event it will not be broadcasted again
@@ -262,34 +262,34 @@ typedef struct { * invoking @p chReceive() when listening to this event. This behavior
* minimizes the interrupt served by the system because CAN traffic.
*/
- EventSource cd_rxfull_event;
+ EventSource rxfull_event;
/**
* @brief One or more transmission slots become available.
*/
- EventSource cd_txempty_event;
+ EventSource txempty_event;
/**
* @brief A CAN bus error happened.
*/
- EventSource cd_error_event;
+ EventSource error_event;
/**
* @brief Error flags set when an error event is broadcasted.
*/
- canstatus_t cd_status;
+ canstatus_t status;
#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
/**
* @brief Entering sleep state event.
*/
- EventSource cd_sleep_event;
+ EventSource sleep_event;
/**
* @brief Exiting sleep state event.
*/
- EventSource cd_wakeup_event;
+ EventSource wakeup_event;
#endif /* CAN_USE_SLEEP_MODE */
/* End of the mandatory fields.*/
/**
* @brief Pointer to the CAN registers.
*/
- CAN_TypeDef *cd_can;
+ CAN_TypeDef *can;
} CANDriver;
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index a101b284a..6a5b210df 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -107,20 +107,20 @@ PWMDriver PWMD5; static void serve_interrupt(PWMDriver *pwmp) {
uint16_t sr;
- sr = pwmp->pd_tim->SR;
- sr &= pwmp->pd_tim->DIER;
- pwmp->pd_tim->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF |
+ sr = pwmp->tim->SR;
+ sr &= pwmp->tim->DIER;
+ pwmp->tim->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF |
TIM_SR_CC4IF | TIM_SR_UIF);
if ((sr & TIM_SR_CC1IF) != 0)
- pwmp->pd_config->pc_channels[0].pcc_callback(pwmp);
+ pwmp->config->channels[0].callback(pwmp);
if ((sr & TIM_SR_CC2IF) != 0)
- pwmp->pd_config->pc_channels[1].pcc_callback(pwmp);
+ pwmp->config->channels[1].callback(pwmp);
if ((sr & TIM_SR_CC3IF) != 0)
- pwmp->pd_config->pc_channels[2].pcc_callback(pwmp);
+ pwmp->config->channels[2].callback(pwmp);
if ((sr & TIM_SR_CC4IF) != 0)
- pwmp->pd_config->pc_channels[3].pcc_callback(pwmp);
+ pwmp->config->channels[3].callback(pwmp);
if ((sr & TIM_SR_UIF) != 0)
- pwmp->pd_config->pc_callback(pwmp);
+ pwmp->config->callback(pwmp);
}
#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
@@ -142,7 +142,7 @@ CH_IRQ_HANDLER(TIM1_UP_IRQHandler) { CH_IRQ_PROLOGUE();
TIM1->SR = ~TIM_SR_UIF;
- PWMD1.pd_config->pc_callback(&PWMD1);
+ PWMD1.config->callback(&PWMD1);
CH_IRQ_EPILOGUE();
}
@@ -163,13 +163,13 @@ CH_IRQ_HANDLER(TIM1_CC_IRQHandler) { sr = TIM1->SR & TIM1->DIER;
TIM1->SR = ~(TIM_SR_CC1IF | TIM_SR_CC2IF | TIM_SR_CC3IF | TIM_SR_CC4IF);
if ((sr & TIM_SR_CC1IF) != 0)
- PWMD1.pd_config->pc_channels[0].pcc_callback(&PWMD1);
+ PWMD1.config->channels[0].callback(&PWMD1);
if ((sr & TIM_SR_CC2IF) != 0)
- PWMD1.pd_config->pc_channels[1].pcc_callback(&PWMD1);
+ PWMD1.config->channels[1].callback(&PWMD1);
if ((sr & TIM_SR_CC3IF) != 0)
- PWMD1.pd_config->pc_channels[2].pcc_callback(&PWMD1);
+ PWMD1.config->channels[2].callback(&PWMD1);
if ((sr & TIM_SR_CC4IF) != 0)
- PWMD1.pd_config->pc_channels[3].pcc_callback(&PWMD1);
+ PWMD1.config->channels[3].callback(&PWMD1);
CH_IRQ_EPILOGUE();
}
@@ -253,36 +253,36 @@ void pwm_lld_init(void) { #if STM32_PWM_USE_TIM1
/* Driver initialization.*/
pwmObjectInit(&PWMD1);
- PWMD1.pd_enabled_channels = 0;
- PWMD1.pd_tim = TIM1;
+ PWMD1.enabled_channels = 0;
+ PWMD1.tim = TIM1;
#endif
#if STM32_PWM_USE_TIM2
/* Driver initialization.*/
pwmObjectInit(&PWMD2);
- PWMD2.pd_enabled_channels = 0;
- PWMD2.pd_tim = TIM2;
+ PWMD2.enabled_channels = 0;
+ PWMD2.tim = TIM2;
#endif
#if STM32_PWM_USE_TIM3
/* Driver initialization.*/
pwmObjectInit(&PWMD3);
- PWMD3.pd_enabled_channels = 0;
- PWMD3.pd_tim = TIM3;
+ PWMD3.enabled_channels = 0;
+ PWMD3.tim = TIM3;
#endif
#if STM32_PWM_USE_TIM4
/* Driver initialization.*/
pwmObjectInit(&PWMD4);
- PWMD4.pd_enabled_channels = 0;
- PWMD4.pd_tim = TIM4;
+ PWMD4.enabled_channels = 0;
+ PWMD4.tim = TIM4;
#endif
#if STM32_PWM_USE_TIM5
/* Driver initialization.*/
pwmObjectInit(&PWMD5);
- PWMD5.pd_enabled_channels = 0;
- PWMD5.pd_tim = TIM5;
+ PWMD5.enabled_channels = 0;
+ PWMD5.tim = TIM5;
#endif
}
@@ -297,9 +297,9 @@ void pwm_lld_start(PWMDriver *pwmp) { uint16_t ccer;
/* Reset channels.*/
- pwmp->pd_enabled_channels = 0; /* All channels disabled. */
+ pwmp->enabled_channels = 0; /* All channels disabled. */
- if (pwmp->pd_state == PWM_STOP) {
+ if (pwmp->state == PWM_STOP) {
/* Clock activation and timer reset.*/
#if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {
@@ -352,11 +352,11 @@ void pwm_lld_start(PWMDriver *pwmp) { /* All channels configured in PWM1 mode with preload enabled and will
stay that way until the driver is stopped.*/
- pwmp->pd_tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
+ pwmp->tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
TIM_CCMR1_OC1PE |
TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 |
TIM_CCMR1_OC2PE;
- pwmp->pd_tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
+ pwmp->tim->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 |
TIM_CCMR2_OC3PE |
TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 |
TIM_CCMR2_OC4PE;
@@ -364,23 +364,23 @@ void pwm_lld_start(PWMDriver *pwmp) { else {
/* Driver re-configuration scenario, it must be stopped first.*/
/* Really required ?????????? */
- pwmp->pd_tim->CR1 = 0; /* Timer stopped. */
- pwmp->pd_tim->CR2 = 0; /* Timer stopped. */
- pwmp->pd_tim->SMCR = 0; /* Slave mode disabled. */
- pwmp->pd_tim->CCR1 = 0; /* Comparator 1 disabled. */
- pwmp->pd_tim->CCR2 = 0; /* Comparator 2 disabled. */
- pwmp->pd_tim->CCR3 = 0; /* Comparator 3 disabled. */
- pwmp->pd_tim->CCR4 = 0; /* Comparator 4 disabled. */
- pwmp->pd_tim->CNT = 0;
+ pwmp->tim->CR1 = 0; /* Timer stopped. */
+ pwmp->tim->CR2 = 0; /* Timer stopped. */
+ pwmp->tim->SMCR = 0; /* Slave mode disabled. */
+ pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
+ pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
+ pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
+ pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
+ pwmp->tim->CNT = 0;
}
/* Timer configuration.*/
- pwmp->pd_tim->CR2 = pwmp->pd_config->pc_cr2;
- pwmp->pd_tim->PSC = pwmp->pd_config->pc_psc;
- pwmp->pd_tim->ARR = pwmp->pd_config->pc_arr;
+ pwmp->tim->CR2 = pwmp->config->cr2;
+ pwmp->tim->PSC = pwmp->config->psc;
+ pwmp->tim->ARR = pwmp->config->arr;
/* Output enables and polarities setup.*/
ccer = 0;
- switch (pwmp->pd_config->pc_channels[0].pcc_mode) {
+ switch (pwmp->config->channels[0].mode) {
case PWM_OUTPUT_ACTIVE_LOW:
ccer |= TIM_CCER_CC1P;
case PWM_OUTPUT_ACTIVE_HIGH:
@@ -388,7 +388,7 @@ void pwm_lld_start(PWMDriver *pwmp) { default:
;
}
- switch (pwmp->pd_config->pc_channels[1].pcc_mode) {
+ switch (pwmp->config->channels[1].mode) {
case PWM_OUTPUT_ACTIVE_LOW:
ccer |= TIM_CCER_CC2P;
case PWM_OUTPUT_ACTIVE_HIGH:
@@ -396,7 +396,7 @@ void pwm_lld_start(PWMDriver *pwmp) { default:
;
}
- switch (pwmp->pd_config->pc_channels[2].pcc_mode) {
+ switch (pwmp->config->channels[2].mode) {
case PWM_OUTPUT_ACTIVE_LOW:
ccer |= TIM_CCER_CC3P;
case PWM_OUTPUT_ACTIVE_HIGH:
@@ -404,7 +404,7 @@ void pwm_lld_start(PWMDriver *pwmp) { default:
;
}
- switch (pwmp->pd_config->pc_channels[3].pcc_mode) {
+ switch (pwmp->config->channels[3].mode) {
case PWM_OUTPUT_ACTIVE_LOW:
ccer |= TIM_CCER_CC4P;
case PWM_OUTPUT_ACTIVE_HIGH:
@@ -412,13 +412,13 @@ void pwm_lld_start(PWMDriver *pwmp) { default:
;
}
- pwmp->pd_tim->CCER = ccer;
- pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */
- pwmp->pd_tim->SR = 0; /* Clear pending IRQs. */
- pwmp->pd_tim->DIER = pwmp->pd_config->pc_callback == NULL ? 0 : TIM_DIER_UIE;
- pwmp->pd_tim->BDTR = TIM_BDTR_MOE;
+ pwmp->tim->CCER = ccer;
+ pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */
+ pwmp->tim->SR = 0; /* Clear pending IRQs. */
+ pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE;
+ pwmp->tim->BDTR = TIM_BDTR_MOE;
/* Timer configured and started.*/
- pwmp->pd_tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN;
+ pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN;
}
/**
@@ -431,19 +431,19 @@ void pwm_lld_start(PWMDriver *pwmp) { void pwm_lld_stop(PWMDriver *pwmp) {
/* If in ready state then disables the PWM clock.*/
- if (pwmp->pd_state == PWM_READY) {
- pwmp->pd_enabled_channels = 0; /* All channels disabled. */
- pwmp->pd_tim->CR1 = 0;
- pwmp->pd_tim->CR2 = 0;
- pwmp->pd_tim->CCER = 0; /* Outputs disabled. */
- pwmp->pd_tim->CCR1 = 0; /* Comparator 1 disabled. */
- pwmp->pd_tim->CCR2 = 0; /* Comparator 2 disabled. */
- pwmp->pd_tim->CCR3 = 0; /* Comparator 3 disabled. */
- pwmp->pd_tim->CCR4 = 0; /* Comparator 4 disabled. */
- pwmp->pd_tim->BDTR = 0;
- pwmp->pd_tim->DIER = 0;
- pwmp->pd_tim->SR = 0;
- pwmp->pd_tim->EGR = TIM_EGR_UG; /* Update event. */
+ if (pwmp->state == PWM_READY) {
+ pwmp->enabled_channels = 0; /* All channels disabled. */
+ pwmp->tim->CR1 = 0;
+ pwmp->tim->CR2 = 0;
+ pwmp->tim->CCER = 0; /* Outputs disabled. */
+ pwmp->tim->CCR1 = 0; /* Comparator 1 disabled. */
+ pwmp->tim->CCR2 = 0; /* Comparator 2 disabled. */
+ pwmp->tim->CCR3 = 0; /* Comparator 3 disabled. */
+ pwmp->tim->CCR4 = 0; /* Comparator 4 disabled. */
+ pwmp->tim->BDTR = 0;
+ pwmp->tim->DIER = 0;
+ pwmp->tim->SR = 0;
+ pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */
#if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {
@@ -492,15 +492,15 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel,
pwmcnt_t width) {
- *(&pwmp->pd_tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */
- if ((pwmp->pd_enabled_channels & (1 << channel)) == 0) {
+ *(&pwmp->tim->CCR1 + (channel * 2)) = width; /* New duty cycle. */
+ if ((pwmp->enabled_channels & (1 << channel)) == 0) {
/* The channel is not enabled yet.*/
- pwmp->pd_enabled_channels |= (1 << channel);
+ pwmp->enabled_channels |= (1 << channel);
/* If there is a callback associated to the channel then the proper
interrupt is cleared and enabled.*/
- if (pwmp->pd_config->pc_channels[channel].pcc_callback) {
- pwmp->pd_tim->SR = ~(2 << channel);
- pwmp->pd_tim->DIER |= (2 << channel);
+ if (pwmp->config->channels[channel].callback) {
+ pwmp->tim->SR = ~(2 << channel);
+ pwmp->tim->DIER |= (2 << channel);
}
}
}
@@ -517,9 +517,9 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
- *(&pwmp->pd_tim->CCR1 + (channel * 2)) = 0;
- pwmp->pd_tim->DIER &= ~(2 << channel);
- pwmp->pd_enabled_channels &= ~(1 << channel);
+ *(&pwmp->tim->CCR1 + (channel * 2)) = 0;
+ pwmp->tim->DIER &= ~(2 << channel);
+ pwmp->enabled_channels &= ~(1 << channel);
}
#endif /* HAL_USE_PWM */
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 1e9dd855a..5954a29b0 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -186,13 +186,13 @@ typedef struct { /**
* @brief Channel active logic level.
*/
- pwmmode_t pcc_mode;
+ pwmmode_t mode;
/**
* @brief Channel callback pointer.
* @note This callback is invoked on the channel compare event. If set to
* @p NULL then the callback is disabled.
*/
- pwmcallback_t pcc_callback;
+ pwmcallback_t callback;
/* End of the mandatory fields.*/
} PWMChannelConfig;
@@ -205,25 +205,25 @@ typedef struct { * @note This callback is invoked on PWM counter reset. If set to
* @p NULL then the callback is disabled.
*/
- pwmcallback_t pc_callback;
+ pwmcallback_t callback;
/**
* @brief Channels configurations.
*/
- PWMChannelConfig pc_channels[PWM_CHANNELS];
+ PWMChannelConfig channels[PWM_CHANNELS];
/* End of the mandatory fields.*/
/**
* @brief TIM PSC (pre-scaler) register initialization data.
*/
- uint16_t pc_psc;
+ uint16_t psc;
/**
* @brief TIM ARR (auto-reload) register initialization data.
*/
- uint16_t pc_arr;
+ uint16_t arr;
/**
* @brief TIM CR2 register initialization data.
* @note The value of this field should normally be equal to zero.
*/
- uint16_t pc_cr2;
+ uint16_t cr2;
} PWMConfig;
/**
@@ -233,11 +233,11 @@ struct PWMDriver { /**
* @brief Driver state.
*/
- pwmstate_t pd_state;
+ pwmstate_t state;
/**
* @brief Current driver configuration data.
*/
- const PWMConfig *pd_config;
+ const PWMConfig *config;
#if defined(PWM_DRIVER_EXT_FIELDS)
PWM_DRIVER_EXT_FIELDS
#endif
@@ -245,11 +245,11 @@ struct PWMDriver { /**
* @brief Bit mask of the enabled channels.
*/
- uint32_t pd_enabled_channels;
+ uint32_t enabled_channels;
/**
* @brief Pointer to the TIMx registers block.
*/
- TIM_TypeDef *pd_tim;
+ TIM_TypeDef *tim;
};
/*===========================================================================*/
@@ -272,7 +272,7 @@ struct PWMDriver { * and/or the STM32 Reference Manual for the right clock
* source.
* @param[in] pwmclk PWM clock frequency in cycles
- * @return The value to be stored in the @p pc_psc field of the
+ * @return The value to be stored in the @p psc field of the
* @p PWMConfig structure.
*/
#define PWM_COMPUTE_PSC(clksrc, pwmclk) \
@@ -284,7 +284,7 @@ struct PWMDriver { *
* @param[in] pwmclk PWM clock frequency in cycles
* @param[in] pwmperiod PWM cycle period in nanoseconds
- * @return The value to be stored in the @p pc_arr field of the
+ * @return The value to be stored in the @p arr field of the
* @p PWMConfig structure.
*/
#define PWM_COMPUTE_ARR(pwmclk, pwmperiod) \
@@ -305,7 +305,7 @@ struct PWMDriver { * @api
*/
#define PWM_FRACTION_TO_WIDTH(pwmp, numerator, denominator) \
- ((uint16_t)((((uint32_t)(pwmp)->pd_config->pc_arr + 1UL) * \
+ ((uint16_t)((((uint32_t)(pwmp)->config->arr + 1UL) * \
(uint32_t)(denominator)) / (uint32_t)(numerator)))
/**
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 1987373ae..53f0ae1c7 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -66,8 +66,8 @@ static uint16_t dummyrx; * @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_stop(spip) { \
- dmaChannelDisable(spip->spd_dmatx); \
- dmaChannelDisable(spip->spd_dmarx); \
+ dmaChannelDisable(spip->dmatx); \
+ dmaChannelDisable(spip->dmarx); \
}
/**
@@ -76,8 +76,8 @@ static uint16_t dummyrx; * @param[in] spip pointer to the @p SPIDriver object
*/
#define dma_start(spip) { \
- dmaChannelEnable((spip)->spd_dmarx); \
- dmaChannelEnable((spip)->spd_dmatx); \
+ dmaChannelEnable((spip)->dmarx); \
+ dmaChannelEnable((spip)->dmatx); \
}
/**
@@ -219,26 +219,26 @@ void spi_lld_init(void) { #if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
- SPID1.spd_thread = NULL;
- SPID1.spd_spi = SPI1;
- SPID1.spd_dmarx = STM32_DMA1_CH2;
- SPID1.spd_dmatx = STM32_DMA1_CH3;
+ SPID1.thread = NULL;
+ SPID1.spi = SPI1;
+ SPID1.dmarx = STM32_DMA1_CH2;
+ SPID1.dmatx = STM32_DMA1_CH3;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
- SPID2.spd_thread = NULL;
- SPID2.spd_spi = SPI2;
- SPID2.spd_dmarx = STM32_DMA1_CH4;
- SPID2.spd_dmatx = STM32_DMA1_CH5;
+ SPID2.thread = NULL;
+ SPID2.spi = SPI2;
+ SPID2.dmarx = STM32_DMA1_CH4;
+ SPID2.dmatx = STM32_DMA1_CH5;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
- SPID3.spd_thread = NULL;
- SPID3.spd_spi = SPI3;
- SPID3.spd_dmarx = STM32_DMA2_CH1;
- SPID3.spd_dmatx = STM32_DMA2_CH2;
+ SPID3.thread = NULL;
+ SPID3.spi = SPI3;
+ SPID3.dmarx = STM32_DMA2_CH1;
+ SPID3.dmatx = STM32_DMA2_CH2;
#endif
}
@@ -252,7 +252,7 @@ void spi_lld_init(void) { void spi_lld_start(SPIDriver *spip) {
/* If in stopped state then enables the SPI and DMA clocks.*/
- if (spip->spd_state == SPI_STOP) {
+ if (spip->state == SPI_STOP) {
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
@@ -285,23 +285,23 @@ void spi_lld_start(SPIDriver *spip) { #endif
/* DMA setup.*/
- dmaChannelSetPeripheral(spip->spd_dmarx, &spip->spd_spi->DR);
- dmaChannelSetPeripheral(spip->spd_dmatx, &spip->spd_spi->DR);
+ dmaChannelSetPeripheral(spip->dmarx, &spip->spi->DR);
+ dmaChannelSetPeripheral(spip->dmatx, &spip->spi->DR);
}
/* More DMA setup.*/
- if ((spip->spd_config->spc_cr1 & SPI_CR1_DFF) == 0)
- spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
+ if ((spip->config->cr1 & SPI_CR1_DFF) == 0)
+ spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
DMA_CCR1_TEIE; /* 8 bits transfers. */
else
- spip->spd_dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
+ spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) |
DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 |
DMA_CCR1_PSIZE_0; /* 16 bits transfers. */
/* SPI setup and enable.*/
- spip->spd_spi->CR1 = 0;
- spip->spd_spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
- spip->spd_spi->CR1 = spip->spd_config->spc_cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;
+ spip->spi->CR1 = 0;
+ spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;
+ spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;
}
/**
@@ -314,10 +314,10 @@ void spi_lld_start(SPIDriver *spip) { void spi_lld_stop(SPIDriver *spip) {
/* If in ready state then disables the SPI clock.*/
- if (spip->spd_state == SPI_READY) {
+ if (spip->state == SPI_READY) {
/* SPI disable.*/
- spip->spd_spi->CR1 = 0;
+ spip->spi->CR1 = 0;
#if STM32_SPI_USE_SPI1
if (&SPID1 == spip) {
@@ -355,7 +355,7 @@ void spi_lld_stop(SPIDriver *spip) { */
void spi_lld_select(SPIDriver *spip) {
- palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);
+ palClearPad(spip->config->ssport, spip->config->sspad);
}
/**
@@ -368,7 +368,7 @@ void spi_lld_select(SPIDriver *spip) { */
void spi_lld_unselect(SPIDriver *spip) {
- palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad);
+ palSetPad(spip->config->ssport, spip->config->sspad);
}
/**
@@ -384,10 +384,10 @@ void spi_lld_unselect(SPIDriver *spip) { */
void spi_lld_ignore(SPIDriver *spip, size_t n) {
- dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, &dummytx,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmarx, n, &dummyrx,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, &dummytx,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
}
/**
@@ -408,11 +408,11 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { void spi_lld_exchange(SPIDriver *spip, size_t n,
const void *txbuf, void *rxbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, rxbuf,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, rxbuf,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, txbuf,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmatx, n, txbuf,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
DMA_CCR1_EN);
}
@@ -431,10 +431,10 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, */
void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, &dummyrx,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, txbuf,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, &dummyrx,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, txbuf,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
DMA_CCR1_EN);
}
@@ -453,11 +453,11 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { */
void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
- dmaChannelSetup(spip->spd_dmarx, n, rxbuf,
- spip->spd_dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
+ dmaChannelSetup(spip->dmarx, n, rxbuf,
+ spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC |
DMA_CCR1_EN);
- dmaChannelSetup(spip->spd_dmatx, n, &dummytx,
- spip->spd_dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
+ dmaChannelSetup(spip->dmatx, n, &dummytx,
+ spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN);
}
/**
@@ -474,10 +474,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { */
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
- spip->spd_spi->DR = frame;
- while ((spip->spd_spi->SR & SPI_SR_RXNE) == 0)
+ spip->spi->DR = frame;
+ while ((spip->spi->SR & SPI_SR_RXNE) == 0)
;
- return spip->spd_spi->DR;
+ return spip->spi->DR;
}
#endif /* HAL_USE_SPI */
diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index 9e29c5d68..306540ed7 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -187,20 +187,20 @@ typedef struct { /**
* @brief Operation complete callback or @p NULL.
*/
- spicallback_t spc_endcb;
+ spicallback_t end_cb;
/* End of the mandatory fields.*/
/**
* @brief The chip select line port.
*/
- ioportid_t spc_ssport;
+ ioportid_t ssport;
/**
* @brief The chip select line pad number.
*/
- uint16_t spc_sspad;
+ uint16_t sspad;
/**
* @brief SPI initialization data.
*/
- uint16_t spc_cr1;
+ uint16_t cr1;
} SPIConfig;
/**
@@ -210,25 +210,25 @@ struct SPIDriver{ /**
* @brief Driver state.
*/
- spistate_t spd_state;
+ spistate_t state;
/**
* @brief Current configuration data.
*/
- const SPIConfig *spd_config;
+ const SPIConfig *config;
#if SPI_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
- Thread *spd_thread;
+ Thread *thread;
#endif /* SPI_USE_WAIT */
#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the bus.
*/
- Mutex spd_mutex;
+ Mutex mutex;
#elif CH_USE_SEMAPHORES
- Semaphore spd_semaphore;
+ Semaphore semaphore;
#endif
#endif /* SPI_USE_MUTUAL_EXCLUSION */
#if defined(SPI_DRIVER_EXT_FIELDS)
@@ -238,19 +238,19 @@ struct SPIDriver{ /**
* @brief Pointer to the SPIx registers block.
*/
- SPI_TypeDef *spd_spi;
+ SPI_TypeDef *spi;
/**
* @brief Pointer to the receive DMA channel registers block.
*/
- stm32_dma_channel_t *spd_dmarx;
+ stm32_dma_channel_t *dmarx;
/**
* @brief Pointer to the transmit DMA channel registers block.
*/
- stm32_dma_channel_t *spd_dmatx;
+ stm32_dma_channel_t *dmatx;
/**
* @brief DMA priority bit mask.
*/
- uint32_t spd_dmaccr;
+ uint32_t dmaccr;
};
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c index e05051a73..2f25f6c56 100644 --- a/os/hal/platforms/STM32/uart_lld.c +++ b/os/hal/platforms/STM32/uart_lld.c @@ -90,13 +90,13 @@ static void set_rx_idle_loop(UARTDriver *uartp) { /* RX DMA channel preparation, if the char callback is defined then the
TCIE interrupt is enabled too.*/
- if (uartp->ud_config->uc_rxchar == NULL)
+ if (uartp->config->rxchar_cb == NULL)
ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE;
else
ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE | DMA_CCR1_TCIE;
- dmaSetupChannel(uartp->ud_dmap, uartp->ud_dmarx, 1,
- &uartp->ud_rxbuf, uartp->ud_dmaccr | ccr);
- dmaEnableChannel(uartp->ud_dmap, uartp->ud_dmarx);
+ dmaSetupChannel(uartp->dmap, uartp->dmarx, 1,
+ &uartp->rxbuf, uartp->dmaccr | ccr);
+ dmaEnableChannel(uartp->dmap, uartp->dmarx);
}
/**
@@ -108,15 +108,15 @@ static void set_rx_idle_loop(UARTDriver *uartp) { static void usart_stop(UARTDriver *uartp) {
/* Stops RX and TX DMA channels.*/
- dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmarx);
- dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmatx);
- dmaClearChannel(uartp->ud_dmap, uartp->ud_dmarx);
- dmaClearChannel(uartp->ud_dmap, uartp->ud_dmatx);
+ dmaDisableChannel(uartp->dmap, uartp->dmarx);
+ dmaDisableChannel(uartp->dmap, uartp->dmatx);
+ dmaClearChannel(uartp->dmap, uartp->dmarx);
+ dmaClearChannel(uartp->dmap, uartp->dmatx);
/* Stops USART operations.*/
- uartp->ud_usart->CR1 = 0;
- uartp->ud_usart->CR2 = 0;
- uartp->ud_usart->CR3 = 0;
+ uartp->usart->CR1 = 0;
+ uartp->usart->CR2 = 0;
+ uartp->usart->CR3 = 0;
}
/**
@@ -127,16 +127,16 @@ static void usart_stop(UARTDriver *uartp) { */
static void usart_start(UARTDriver *uartp) {
uint16_t cr1;
- USART_TypeDef *u = uartp->ud_usart;
+ USART_TypeDef *u = uartp->usart;
/* Defensive programming, starting from a clean state.*/
usart_stop(uartp);
/* Baud rate setting.*/
- if (uartp->ud_usart == USART1)
- u->BRR = STM32_PCLK2 / uartp->ud_config->uc_speed;
+ if (uartp->usart == USART1)
+ u->BRR = STM32_PCLK2 / uartp->config->speed;
else
- u->BRR = STM32_PCLK1 / uartp->ud_config->uc_speed;
+ u->BRR = STM32_PCLK1 / uartp->config->speed;
/* Resetting eventual pending status flags.*/
(void)u->SR; /* SR reset step 1.*/
@@ -145,14 +145,14 @@ static void usart_start(UARTDriver *uartp) { /* Note that some bits are enforced because required for correct driver
operations.*/
- if (uartp->ud_config->uc_txend2 == NULL)
+ if (uartp->config->txend2_cb == NULL)
cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE;
else
cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE |
USART_CR1_TCIE;
- u->CR1 = uartp->ud_config->uc_cr1 | cr1;
- u->CR2 = uartp->ud_config->uc_cr2 | USART_CR2_LBDIE;
- u->CR3 = uartp->ud_config->uc_cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
+ u->CR1 = uartp->config->cr1 | cr1;
+ u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE;
+ u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR |
USART_CR3_EIE;
/* Starting the receiver idle loop.*/
@@ -166,13 +166,13 @@ static void usart_start(UARTDriver *uartp) { */
static void serve_rx_end_irq(UARTDriver *uartp) {
- uartp->ud_rxstate = UART_RX_COMPLETE;
- if (uartp->ud_config->uc_rxend != NULL)
- uartp->ud_config->uc_rxend(uartp);
+ uartp->rxstate = UART_RX_COMPLETE;
+ if (uartp->config->rxend_cb != NULL)
+ uartp->config->rxend_cb(uartp);
/* If the callback didn't explicitly change state then the receiver
automatically returns to the idle state.*/
- if (uartp->ud_rxstate == UART_RX_COMPLETE) {
- uartp->ud_rxstate = UART_RX_IDLE;
+ if (uartp->rxstate == UART_RX_COMPLETE) {
+ uartp->rxstate = UART_RX_IDLE;
set_rx_idle_loop(uartp);
}
}
@@ -185,13 +185,13 @@ static void serve_rx_end_irq(UARTDriver *uartp) { static void serve_tx_end_irq(UARTDriver *uartp) {
/* A callback is generated, if enabled, after a completed transfer.*/
- uartp->ud_txstate = UART_TX_COMPLETE;
- if (uartp->ud_config->uc_txend1 != NULL)
- uartp->ud_config->uc_txend1(uartp);
+ uartp->txstate = UART_TX_COMPLETE;
+ if (uartp->config->txend1_cb != NULL)
+ uartp->config->txend1_cb(uartp);
/* If the callback didn't explicitly change state then the transmitter
automatically returns to the idle state.*/
- if (uartp->ud_txstate == UART_TX_COMPLETE)
- uartp->ud_txstate = UART_TX_IDLE;
+ if (uartp->txstate == UART_TX_COMPLETE)
+ uartp->txstate = UART_TX_IDLE;
}
/**
* @brief USART common service routine.
@@ -200,21 +200,21 @@ static void serve_tx_end_irq(UARTDriver *uartp) { */
static void serve_usart_irq(UARTDriver *uartp) {
uint16_t sr;
- USART_TypeDef *u = uartp->ud_usart;
+ USART_TypeDef *u = uartp->usart;
sr = u->SR; /* SR reset step 1.*/
(void)u->DR; /* SR reset step 2.*/
if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE |
USART_SR_FE | USART_SR_PE)) {
u->SR = ~USART_SR_LBD;
- if (uartp->ud_config->uc_rxerr != NULL)
- uartp->ud_config->uc_rxerr(uartp, translate_errors(sr));
+ if (uartp->config->rxerr_cb != NULL)
+ uartp->config->rxerr_cb(uartp, translate_errors(sr));
}
if (sr & USART_SR_TC) {
u->SR = ~USART_SR_TC;
/* End of transmission, a callback is generated.*/
- if (uartp->ud_config->uc_txend2 != NULL)
- uartp->ud_config->uc_txend2(uartp);
+ if (uartp->config->txend2_cb != NULL)
+ uartp->config->txend2_cb(uartp);
}
}
@@ -237,13 +237,13 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { if ((STM32_DMA1->ISR & DMA_ISR_TEIF5) != 0) {
STM32_UART_USART1_DMA_ERROR_HOOK();
}
- if (uartp->ud_rxstate == UART_RX_IDLE) {
+ if (uartp->rxstate == UART_RX_IDLE) {
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_5);
/* Fast IRQ path, this is why it is not centralized in serve_rx_end_irq().*/
/* Receiver in idle state, a callback is generated, if enabled, for each
received character and then the driver stays in the same state.*/
- if (uartp->ud_config->uc_rxchar != NULL)
- uartp->ud_config->uc_rxchar(uartp, uartp->ud_rxbuf);
+ if (uartp->config->rxchar_cb != NULL)
+ uartp->config->rxchar_cb(uartp, uartp->rxbuf);
}
else {
/* Receiver in active state, a callback is generated, if enabled, after
@@ -305,13 +305,13 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { if ((STM32_DMA1->ISR & DMA_ISR_TEIF6) != 0) {
STM32_UART_USART2_DMA_ERROR_HOOK();
}
- if (uartp->ud_rxstate == UART_RX_IDLE) {
+ if (uartp->rxstate == UART_RX_IDLE) {
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_6);
/* Fast IRQ path, this is why it is not centralized in serve_rx_end_irq().*/
/* Receiver in idle state, a callback is generated, if enabled, for each
received character and then the driver stays in the same state.*/
- if (uartp->ud_config->uc_rxchar != NULL)
- uartp->ud_config->uc_rxchar(uartp, uartp->ud_rxbuf);
+ if (uartp->config->rxchar_cb != NULL)
+ uartp->config->rxchar_cb(uartp, uartp->rxbuf);
}
else {
/* Receiver in active state, a callback is generated, if enabled, after
@@ -373,13 +373,13 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { if ((STM32_DMA1->ISR & DMA_ISR_TEIF3) != 0) {
STM32_UART_USART1_DMA_ERROR_HOOK();
}
- if (uartp->ud_rxstate == UART_RX_IDLE) {
+ if (uartp->rxstate == UART_RX_IDLE) {
dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_3);
/* Fast IRQ path, this is why it is not centralized in serve_rx_end_irq().*/
/* Receiver in idle state, a callback is generated, if enabled, for each
received character and then the driver stays in the same state.*/
- if (uartp->ud_config->uc_rxchar != NULL)
- uartp->ud_config->uc_rxchar(uartp, uartp->ud_rxbuf);
+ if (uartp->config->rxchar_cb != NULL)
+ uartp->config->rxchar_cb(uartp, uartp->rxbuf);
}
else {
/* Receiver in active state, a callback is generated, if enabled, after
@@ -439,29 +439,29 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART1
uartObjectInit(&UARTD1);
- UARTD1.ud_usart = USART1;
- UARTD1.ud_dmap = STM32_DMA1;
- UARTD1.ud_dmarx = STM32_DMA_CHANNEL_5;
- UARTD1.ud_dmatx = STM32_DMA_CHANNEL_4;
- UARTD1.ud_dmaccr = 0;
+ UARTD1.usart = USART1;
+ UARTD1.dmap = STM32_DMA1;
+ UARTD1.dmarx = STM32_DMA_CHANNEL_5;
+ UARTD1.dmatx = STM32_DMA_CHANNEL_4;
+ UARTD1.dmaccr = 0;
#endif
#if STM32_UART_USE_USART2
uartObjectInit(&UARTD2);
- UARTD2.ud_usart = USART2;
- UARTD2.ud_dmap = STM32_DMA1;
- UARTD2.ud_dmarx = STM32_DMA_CHANNEL_6;
- UARTD2.ud_dmatx = STM32_DMA_CHANNEL_7;
- UARTD2.ud_dmaccr = 0;
+ UARTD2.usart = USART2;
+ UARTD2.dmap = STM32_DMA1;
+ UARTD2.dmarx = STM32_DMA_CHANNEL_6;
+ UARTD2.dmatx = STM32_DMA_CHANNEL_7;
+ UARTD2.dmaccr = 0;
#endif
#if STM32_UART_USE_USART3
uartObjectInit(&UARTD3);
- UARTD3.ud_usart = USART3;
- UARTD3.ud_dmap = STM32_DMA1;
- UARTD3.ud_dmarx = STM32_DMA_CHANNEL_3;
- UARTD3.ud_dmatx = STM32_DMA_CHANNEL_2;
- UARTD3.ud_dmaccr = 0;
+ UARTD3.usart = USART3;
+ UARTD3.dmap = STM32_DMA1;
+ UARTD3.dmarx = STM32_DMA_CHANNEL_3;
+ UARTD3.dmatx = STM32_DMA_CHANNEL_2;
+ UARTD3.dmaccr = 0;
#endif
}
@@ -474,7 +474,7 @@ void uart_lld_init(void) { */
void uart_lld_start(UARTDriver *uartp) {
- if (uartp->ud_state == UART_STOP) {
+ if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
@@ -516,18 +516,18 @@ void uart_lld_start(UARTDriver *uartp) { /* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
- uartp->ud_dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12;
- if ((uartp->ud_config->uc_cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
- uartp->ud_dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0;
- dmaChannelSetPeripheral(&uartp->ud_dmap->channels[uartp->ud_dmarx],
- &uartp->ud_usart->DR);
- dmaChannelSetPeripheral(&uartp->ud_dmap->channels[uartp->ud_dmatx],
- &uartp->ud_usart->DR);
- uartp->ud_rxbuf = 0;
+ uartp->dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12;
+ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
+ uartp->dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0;
+ dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmarx],
+ &uartp->usart->DR);
+ dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmatx],
+ &uartp->usart->DR);
+ uartp->rxbuf = 0;
}
- uartp->ud_rxstate = UART_RX_IDLE;
- uartp->ud_txstate = UART_TX_IDLE;
+ uartp->rxstate = UART_RX_IDLE;
+ uartp->txstate = UART_TX_IDLE;
usart_start(uartp);
}
@@ -540,7 +540,7 @@ void uart_lld_start(UARTDriver *uartp) { */
void uart_lld_stop(UARTDriver *uartp) {
- if (uartp->ud_state == UART_READY) {
+ if (uartp->state == UART_READY) {
usart_stop(uartp);
#if STM32_UART_USE_USART1
@@ -592,10 +592,10 @@ void uart_lld_stop(UARTDriver *uartp) { void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) {
/* TX DMA channel preparation and start.*/
- dmaSetupChannel(uartp->ud_dmap, uartp->ud_dmatx, n, txbuf,
- uartp->ud_dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
+ dmaSetupChannel(uartp->dmap, uartp->dmatx, n, txbuf,
+ uartp->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC |
DMA_CCR1_TEIE | DMA_CCR1_TCIE);
- dmaEnableChannel(uartp->ud_dmap, uartp->ud_dmatx);
+ dmaEnableChannel(uartp->dmap, uartp->dmatx);
}
/**
@@ -611,9 +611,9 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { */
size_t uart_lld_stop_send(UARTDriver *uartp) {
- dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmatx);
- dmaClearChannel(uartp->ud_dmap, uartp->ud_dmatx);
- return (size_t)uartp->ud_dmap->channels[uartp->ud_dmatx].CNDTR;
+ dmaDisableChannel(uartp->dmap, uartp->dmatx);
+ dmaClearChannel(uartp->dmap, uartp->dmatx);
+ return (size_t)uartp->dmap->channels[uartp->dmatx].CNDTR;
}
/**
@@ -630,14 +630,14 @@ size_t uart_lld_stop_send(UARTDriver *uartp) { void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) {
/* Stopping previous activity (idle state).*/
- dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmarx);
- dmaClearChannel(uartp->ud_dmap, uartp->ud_dmarx);
+ dmaDisableChannel(uartp->dmap, uartp->dmarx);
+ dmaClearChannel(uartp->dmap, uartp->dmarx);
/* RX DMA channel preparation and start.*/
- dmaSetupChannel(uartp->ud_dmap, uartp->ud_dmarx, n, rxbuf,
- uartp->ud_dmaccr | DMA_CCR1_MINC |
+ dmaSetupChannel(uartp->dmap, uartp->dmarx, n, rxbuf,
+ uartp->dmaccr | DMA_CCR1_MINC |
DMA_CCR1_TEIE | DMA_CCR1_TCIE);
- dmaEnableChannel(uartp->ud_dmap, uartp->ud_dmarx);
+ dmaEnableChannel(uartp->dmap, uartp->dmarx);
}
/**
@@ -654,9 +654,9 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { size_t uart_lld_stop_receive(UARTDriver *uartp) {
size_t n;
- dmaDisableChannel(uartp->ud_dmap, uartp->ud_dmarx);
- dmaClearChannel(uartp->ud_dmap, uartp->ud_dmarx);
- n = (size_t)uartp->ud_dmap->channels[uartp->ud_dmarx].CNDTR;
+ dmaDisableChannel(uartp->dmap, uartp->dmarx);
+ dmaClearChannel(uartp->dmap, uartp->dmarx);
+ n = (size_t)uartp->dmap->channels[uartp->dmarx].CNDTR;
set_rx_idle_loop(uartp);
return n;
}
diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h index f09fe7cd4..8394d8421 100644 --- a/os/hal/platforms/STM32/uart_lld.h +++ b/os/hal/platforms/STM32/uart_lld.h @@ -117,8 +117,8 @@ /**
* @brief USART1 DMA error hook.
- * @note The default action for DMA errors is a system halt because DMA error
- * can only happen because programming errors.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
*/
#if !defined(STM32_UART_USART1_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_UART_USART1_DMA_ERROR_HOOK() chSysHalt()
@@ -126,8 +126,8 @@ /**
* @brief USART2 DMA error hook.
- * @note The default action for DMA errors is a system halt because DMA error
- * can only happen because programming errors.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
*/
#if !defined(STM32_UART_USART2_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_UART_USART2_DMA_ERROR_HOOK() chSysHalt()
@@ -135,8 +135,8 @@ /**
* @brief USART3 DMA error hook.
- * @note The default action for DMA errors is a system halt because DMA error
- * can only happen because programming errors.
+ * @note The default action for DMA errors is a system halt because DMA
+ * error can only happen because programming errors.
*/
#if !defined(STM32_UART_USART3_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_UART_USART3_DMA_ERROR_HOOK() chSysHalt()
@@ -208,40 +208,40 @@ typedef struct { /**
* @brief End of transmission buffer callback.
*/
- uartcb_t uc_txend1;
+ uartcb_t txend1_cb;
/**
* @brief Physical end of transmission callback.
*/
- uartcb_t uc_txend2;
+ uartcb_t txend2_cb;
/**
* @brief Receive buffer filled callback.
*/
- uartcb_t uc_rxend;
+ uartcb_t rxend_cb;
/**
* @brief Character received while out if the @p UART_RECEIVE state.
*/
- uartccb_t uc_rxchar;
+ uartccb_t rxchar_cb;
/**
* @brief Receive error callback.
*/
- uartecb_t uc_rxerr;
+ uartecb_t rxerr_cb;
/* End of the mandatory fields.*/
/**
* @brief Bit rate.
*/
- uint32_t uc_speed;
+ uint32_t speed;
/**
* @brief Initialization value for the CR1 register.
*/
- uint16_t uc_cr1;
+ uint16_t cr1;
/**
* @brief Initialization value for the CR2 register.
*/
- uint16_t uc_cr2;
+ uint16_t cr2;
/**
* @brief Initialization value for the CR3 register.
*/
- uint16_t uc_cr3;
+ uint16_t cr3;
} UARTConfig;
/**
@@ -251,19 +251,19 @@ struct UARTDriver { /**
* @brief Driver state.
*/
- uartstate_t ud_state;
+ uartstate_t state;
/**
* @brief Transmitter state.
*/
- uarttxstate_t ud_txstate;
+ uarttxstate_t txstate;
/**
* @brief Receiver state.
*/
- uartrxstate_t ud_rxstate;
+ uartrxstate_t rxstate;
/**
* @brief Current configuration data.
*/
- const UARTConfig *ud_config;
+ const UARTConfig *config;
#if defined(UART_DRIVER_EXT_FIELDS)
UART_DRIVER_EXT_FIELDS
#endif
@@ -271,27 +271,27 @@ struct UARTDriver { /**
* @brief Pointer to the USART registers block.
*/
- USART_TypeDef *ud_usart;
+ USART_TypeDef *usart;
/**
* @brief Pointer to the DMA registers block.
*/
- stm32_dma_t *ud_dmap;
+ stm32_dma_t *dmap;
/**
* @brief DMA priority bit mask.
*/
- uint32_t ud_dmaccr;
+ uint32_t dmaccr;
/**
* @brief Receive DMA channel.
*/
- uint8_t ud_dmarx;
+ uint8_t dmarx;
/**
* @brief Transmit DMA channel.
*/
- uint8_t ud_dmatx;
+ uint8_t dmatx;
/**
* @brief Default receive buffer while into @p UART_RX_IDLE state.
*/
- volatile uint16_t ud_rxbuf;
+ volatile uint16_t rxbuf;
};
/*===========================================================================*/
|