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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-27 19:16:40 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-27 19:16:40 +0000 |
| commit | 9b7b5ce6bfd67fc6317445651af4906c7a54c528 (patch) | |
| tree | b0afd0ce51034b7ada1dad66be5f554287703081 /os/hal/platforms/STM32/pwm_lld.h | |
| parent | 5401b0fa1c1d6799b8fde25254860b04afc0faa3 (diff) | |
| download | ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.tar.gz ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.tar.bz2 ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.zip | |
Fixed bug 3120785.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2439 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/pwm_lld.h')
| -rw-r--r-- | os/hal/platforms/STM32/pwm_lld.h | 43 |
1 files changed, 34 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 6da57f5e1..b716d77c2 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -80,31 +80,47 @@ #endif
/**
+ * @brief PWM5 driver enable switch.
+ * @details If set to @p TRUE the support for PWM5 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM5 TRUE
+#endif
+
+/**
* @brief PWM1 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM1_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#endif
/**
* @brief PWM2 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM2_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#endif
/**
* @brief PWM3 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM3_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#endif
/**
* @brief PWM4 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM4_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief PWM5 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#endif
/*===========================================================================*/
@@ -127,8 +143,13 @@ #error "TIM4 not present in the selected device"
#endif
+#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \
- !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4
+ !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \
+ !STM32_PWM_USE_TIM5
#error "PWM driver activated but no TIM peripheral assigned"
#endif
@@ -338,6 +359,10 @@ extern PWMDriver PWMD3; extern PWMDriver PWMD4;
#endif
+#if defined(STM32_PWM_USE_TIM5) && !defined(__DOXYGEN__)
+extern PWMDriver PWMD5;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
|