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author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-27 19:16:40 +0000 |
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committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-27 19:16:40 +0000 |
commit | 9b7b5ce6bfd67fc6317445651af4906c7a54c528 (patch) | |
tree | b0afd0ce51034b7ada1dad66be5f554287703081 /os/hal/platforms | |
parent | 5401b0fa1c1d6799b8fde25254860b04afc0faa3 (diff) | |
download | ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.tar.gz ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.tar.bz2 ChibiOS-9b7b5ce6bfd67fc6317445651af4906c7a54c528.zip |
Fixed bug 3120785.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2439 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms')
-rw-r--r-- | os/hal/platforms/STM32/pwm_lld.c | 67 | ||||
-rw-r--r-- | os/hal/platforms/STM32/pwm_lld.h | 43 |
2 files changed, 95 insertions, 15 deletions
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index 5e39d8cb6..2ede98142 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -78,6 +78,15 @@ PWMDriver PWMD3; PWMDriver PWMD4;
#endif
+/**
+ * @brief PWM5 driver identifier.
+ * @note The driver PWM5 allocates the timer TIM5 when enabled.
+ */
+#if defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
+PWMDriver PWMD5;
+#endif
+
+
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
@@ -212,6 +221,23 @@ CH_IRQ_HANDLER(TIM4_IRQHandler) { }
#endif /* STM32_PWM_USE_TIM4 */
+#if STM32_PWM_USE_TIM5
+/**
+ * @brief TIM5 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(TIM5_IRQHandler) {
+
+ CH_IRQ_PROLOGUE();
+
+ serve_interrupt(&PWMD5);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* STM32_PWM_USE_TIM5 */
+
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -266,6 +292,17 @@ void pwm_lld_init(void) { PWMD4.pd_enabled_channels = 0;
PWMD4.pd_tim = TIM4;
#endif
+
+#if STM32_PWM_USE_TIM5
+ /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/
+ RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
+ RCC->APB1RSTR = 0;
+
+ /* Driver initialization.*/
+ pwmObjectInit(&PWMD5);
+ PWMD5.pd_enabled_channels = 0;
+ PWMD5.pd_tim = TIM5;
+#endif
}
/**
@@ -289,9 +326,9 @@ void pwm_lld_start(PWMDriver *pwmp) { RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;
RCC->APB2RSTR = 0;
NVICEnableVector(TIM1_UP_IRQn,
- CORTEX_PRIORITY_MASK(STM32_PWM_PWM1_IRQ_PRIORITY));
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
NVICEnableVector(TIM1_CC_IRQn,
- CORTEX_PRIORITY_MASK(STM32_PWM_PWM1_IRQ_PRIORITY));
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM1_IRQ_PRIORITY));
}
#endif
#if STM32_PWM_USE_TIM2
@@ -300,7 +337,7 @@ void pwm_lld_start(PWMDriver *pwmp) { RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;
RCC->APB1RSTR = 0;
NVICEnableVector(TIM2_IRQn,
- CORTEX_PRIORITY_MASK(STM32_PWM_PWM2_IRQ_PRIORITY));
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM2_IRQ_PRIORITY));
}
#endif
#if STM32_PWM_USE_TIM3
@@ -309,7 +346,7 @@ void pwm_lld_start(PWMDriver *pwmp) { RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;
RCC->APB1RSTR = 0;
NVICEnableVector(TIM3_IRQn,
- CORTEX_PRIORITY_MASK(STM32_PWM_PWM3_IRQ_PRIORITY));
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM3_IRQ_PRIORITY));
}
#endif
#if STM32_PWM_USE_TIM4
@@ -318,9 +355,21 @@ void pwm_lld_start(PWMDriver *pwmp) { RCC->APB1RSTR = RCC_APB1RSTR_TIM4RST;
RCC->APB1RSTR = 0;
NVICEnableVector(TIM4_IRQn,
- CORTEX_PRIORITY_MASK(STM32_PWM_PWM4_IRQ_PRIORITY));
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM4_IRQ_PRIORITY));
}
#endif
+
+#if STM32_PWM_USE_TIM5
+ if (&PWMD5 == pwmp) {
+ RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;
+ RCC->APB1RSTR = RCC_APB1RSTR_TIM5RST;
+ RCC->APB1RSTR = 0;
+ NVICEnableVector(TIM5_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM_TIM5_IRQ_PRIORITY));
+ }
+#endif
+
+
/* All channels configured in PWM1 mode with preload enabled and will
stay that way until the driver is stopped.*/
pwmp->pd_tim->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 |
@@ -440,6 +489,12 @@ void pwm_lld_stop(PWMDriver *pwmp) { RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;
}
#endif
+#if STM32_PWM_USE_TIM5
+ if (&PWMD5 == pwmp) {
+ NVICDisableVector(TIM5_IRQn);
+ RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
+ }
+#endif
}
}
@@ -462,7 +517,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmp->pd_enabled_channels |= (1 << channel);
/* If there is a callback associated to the channel then the proper
interrupt is cleared and enabled.*/
- if (pwmp->pd_config->pc_channels[0].pcc_callback) {
+ if (pwmp->pd_config->pc_channels[channel].pcc_callback) {
pwmp->pd_tim->SR = ~(2 << channel);
pwmp->pd_tim->DIER |= (2 << channel);
}
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index 6da57f5e1..b716d77c2 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -80,31 +80,47 @@ #endif
/**
+ * @brief PWM5 driver enable switch.
+ * @details If set to @p TRUE the support for PWM5 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_PWM_USE_TIM5) || defined(__DOXYGEN__)
+#define STM32_PWM_USE_TIM5 TRUE
+#endif
+
+/**
* @brief PWM1 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM1_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#endif
/**
* @brief PWM2 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM2_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#endif
/**
* @brief PWM3 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM3_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#endif
/**
* @brief PWM4 interrupt priority level setting.
*/
-#if !defined(STM32_PWM_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM_PWM4_IRQ_PRIORITY 7
+#if !defined(STM32_PWM_TIM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#endif
+
+/**
+ * @brief PWM5 interrupt priority level setting.
+ */
+#if !defined(STM32_PWM_TIM5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#endif
/*===========================================================================*/
@@ -127,8 +143,13 @@ #error "TIM4 not present in the selected device"
#endif
+#if STM32_PWM_USE_TIM5 && !STM32_HAS_TIM5
+#error "TIM5 not present in the selected device"
+#endif
+
#if !STM32_PWM_USE_TIM1 && !STM32_PWM_USE_TIM2 && \
- !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4
+ !STM32_PWM_USE_TIM3 && !STM32_PWM_USE_TIM4 && \
+ !STM32_PWM_USE_TIM5
#error "PWM driver activated but no TIM peripheral assigned"
#endif
@@ -338,6 +359,10 @@ extern PWMDriver PWMD3; extern PWMDriver PWMD4;
#endif
+#if defined(STM32_PWM_USE_TIM5) && !defined(__DOXYGEN__)
+extern PWMDriver PWMD5;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
|