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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-14 13:29:09 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-11-14 13:29:09 +0000 |
| commit | 7ab0cff418bf49fcf1671dd72667b81a85c1ac37 (patch) | |
| tree | 9527dc092b8fc59f733b2a0353d579ceec8a72ff /os/hal/platforms/STM32/pal_lld.c | |
| parent | bf8592688860a61181b3f5a4c9b6d4d8856b8abb (diff) | |
| download | ChibiOS-7ab0cff418bf49fcf1671dd72667b81a85c1ac37.tar.gz ChibiOS-7ab0cff418bf49fcf1671dd72667b81a85c1ac37.tar.bz2 ChibiOS-7ab0cff418bf49fcf1671dd72667b81a85c1ac37.zip | |
Improved STM32 HAL support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2363 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/STM32/pal_lld.c')
| -rw-r--r-- | os/hal/platforms/STM32/pal_lld.c | 87 |
1 files changed, 44 insertions, 43 deletions
diff --git a/os/hal/platforms/STM32/pal_lld.c b/os/hal/platforms/STM32/pal_lld.c index 6e2346000..ac90883f7 100644 --- a/os/hal/platforms/STM32/pal_lld.c +++ b/os/hal/platforms/STM32/pal_lld.c @@ -30,30 +30,29 @@ #if HAL_USE_PAL || defined(__DOXYGEN__)
-#if defined(STM32F10X_LD)
-#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
- RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
- RCC_APB2RSTR_AFIORST)
-#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
- RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
- RCC_APB2ENR_AFIOEN)
-#elif defined(STM32F10X_HD)
-#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
- RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
- RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_IOPFRST | \
+#if STM32_HAS_GPIOG
+#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
+ RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
+ RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_IOPFRST | \
RCC_APB2RSTR_IOPGRST | RCC_APB2RSTR_AFIORST);
-#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
- RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
- RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
+#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
+ RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
+ RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
-#else
- /* Defaults on Medium Density and Connection Line devices.*/
-#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
- RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
+#elif STM32_HAS_GPIOE
+#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
+ RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST);
-#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
- RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
+#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
+ RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
+#else
+#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
+ RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
+ RCC_APB2RSTR_AFIORST)
+#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
+ RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
+ RCC_APB2ENR_AFIOEN)
#endif
/*===========================================================================*/
@@ -97,30 +96,32 @@ void _pal_lld_init(const PALConfig *config) { RCC->APB2RSTR = APB2_RST_MASK;
RCC->APB2RSTR = 0;
- IOPORT1->ODR = config->PAData.odr;
- IOPORT1->CRH = config->PAData.crh;
- IOPORT1->CRL = config->PAData.crl;
- IOPORT2->ODR = config->PBData.odr;
- IOPORT2->CRH = config->PBData.crh;
- IOPORT2->CRL = config->PBData.crl;
- IOPORT3->ODR = config->PCData.odr;
- IOPORT3->CRH = config->PCData.crh;
- IOPORT3->CRL = config->PCData.crl;
- IOPORT4->ODR = config->PDData.odr;
- IOPORT4->CRH = config->PDData.crh;
- IOPORT4->CRL = config->PDData.crl;
-#if !defined(STM32F10X_LD) || defined(__DOXYGEN__)
- IOPORT5->ODR = config->PEData.odr;
- IOPORT5->CRH = config->PEData.crh;
- IOPORT5->CRL = config->PEData.crl;
+ GPIOA->ODR = config->PAData.odr;
+ GPIOA->CRH = config->PAData.crh;
+ GPIOA->CRL = config->PAData.crl;
+ GPIOB->ODR = config->PBData.odr;
+ GPIOB->CRH = config->PBData.crh;
+ GPIOB->CRL = config->PBData.crl;
+ GPIOC->ODR = config->PCData.odr;
+ GPIOC->CRH = config->PCData.crh;
+ GPIOC->CRL = config->PCData.crl;
+ GPIOD->ODR = config->PDData.odr;
+ GPIOD->CRH = config->PDData.crh;
+ GPIOD->CRL = config->PDData.crl;
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ GPIOE->ODR = config->PEData.odr;
+ GPIOE->CRH = config->PEData.crh;
+ GPIOE->CRL = config->PEData.crl;
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ GPIOF->ODR = config->PFData.odr;
+ GPIOF->CRH = config->PFData.crh;
+ GPIOF->CRL = config->PFData.crl;
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ GPIOG->ODR = config->PGData.odr;
+ GPIOG->CRH = config->PGData.crh;
+ GPIOG->CRL = config->PGData.crl;
+#endif
#endif
-#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
- IOPORT6->ODR = config->PFData.odr;
- IOPORT6->CRH = config->PFData.crh;
- IOPORT6->CRL = config->PFData.crl;
- IOPORT7->ODR = config->PGData.odr;
- IOPORT7->CRH = config->PGData.crh;
- IOPORT7->CRL = config->PGData.crl;
#endif
}
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