diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-13 13:35:10 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-13 13:35:10 +0000 |
| commit | f0e62eb4b588d8b2fbf858efb7b41226a2424d81 (patch) | |
| tree | c785d8ad55aa7b711167b38aefd5194daba7afbc /os/hal/platforms/SPC5xx/LINFlex_v1 | |
| parent | 02b1b936d96443958c3cd6dc8b2b0eedec3a6a46 (diff) | |
| download | ChibiOS-f0e62eb4b588d8b2fbf858efb7b41226a2424d81.tar.gz ChibiOS-f0e62eb4b588d8b2fbf858efb7b41226a2424d81.tar.bz2 ChibiOS-f0e62eb4b588d8b2fbf858efb7b41226a2424d81.zip | |
SPC560Dxx support added.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5847 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx/LINFlex_v1')
| -rw-r--r-- | os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c | 184 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h | 134 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h | 510 |
3 files changed, 769 insertions, 59 deletions
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c index b31bd2387..71247b236 100644 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c @@ -84,7 +84,7 @@ static const SerialConfig default_config = { */
static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
uint32_t div;
- volatile struct LINFLEX_tag *linflexp = sdp->linflexp;
+ volatile struct spc5_linflex *linflexp = sdp->linflexp;
/* Enters the configuration mode.*/
linflexp->LINCR1.R = 1; /* INIT bit. */
@@ -111,7 +111,7 @@ static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) { *
* @param[in] linflexp pointer to a LINFlex I/O block
*/
-static void spc5_linflex_deinit(volatile struct LINFLEX_tag *linflexp) {
+static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) {
/* Enters the configuration mode.*/
linflexp->LINCR1.R = 1; /* INIT bit. */
@@ -222,6 +222,34 @@ static void notify2(GenericQueue *qp) { }
#endif
+#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
+static void notify3(GenericQueue *qp) {
+
+ (void)qp;
+ if (!SD3.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD3);
+ if (b != Q_EMPTY) {
+ SD3.linflexp->UARTCR.B.TXEN = 1;
+ SD3.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
+static void notify4(GenericQueue *qp) {
+
+ (void)qp;
+ if (!SD4.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD4);
+ if (b != Q_EMPTY) {
+ SD4.linflexp->UARTCR.B.TXEN = 1;
+ SD4.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
@@ -332,6 +360,112 @@ CH_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) { }
#endif
+#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX2_RXI_HANDLER)
+#error "SPC5_LINFLEX2_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 RXI interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX2_TXI_HANDLER)
+#error "SPC5_LINFLEX2_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 TXI interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX2_ERR_HANDLER)
+#error "SPC5_LINFLEX2_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 ERR interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD3);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX3_RXI_HANDLER)
+#error "SPC5_LINFLEX3_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 RXI interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX3_TXI_HANDLER)
+#error "SPC5_LINFLEX3_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 TXI interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX3_ERR_HANDLER)
+#error "SPC5_LINFLEX3_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 ERR interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD4);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
@@ -345,7 +479,7 @@ void sd_lld_init(void) { #if SPC5_SERIAL_USE_LINFLEX0
sdObjectInit(&SD1, NULL, notify1);
- SD1.linflexp = &LINFLEX_0;
+ SD1.linflexp = &SPC5_LINFLEX0;
INTC.PSR[SPC5_LINFLEX0_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
INTC.PSR[SPC5_LINFLEX0_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
INTC.PSR[SPC5_LINFLEX0_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX0_PRIORITY;
@@ -353,11 +487,27 @@ void sd_lld_init(void) { #if SPC5_SERIAL_USE_LINFLEX1
sdObjectInit(&SD2, NULL, notify2);
- SD2.linflexp = &LINFLEX_1;
+ SD2.linflexp = &SPC5_LINFLEX1;
INTC.PSR[SPC5_LINFLEX1_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
INTC.PSR[SPC5_LINFLEX1_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
INTC.PSR[SPC5_LINFLEX1_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX1_PRIORITY;
#endif
+
+#if SPC5_SERIAL_USE_LINFLEX2
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.linflexp = &SPC5_LINFLEX2;
+ INTC.PSR[SPC5_LINFLEX2_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
+ INTC.PSR[SPC5_LINFLEX2_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
+ INTC.PSR[SPC5_LINFLEX2_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX2_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3
+ sdObjectInit(&SD4, NULL, notify4);
+ SD4.linflexp = &SPC5_LINFLEX3;
+ INTC.PSR[SPC5_LINFLEX3_RXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
+ INTC.PSR[SPC5_LINFLEX3_TXI_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
+ INTC.PSR[SPC5_LINFLEX3_ERR_NUMBER].R = SPC5_SERIAL_LINFLEX3_PRIORITY;
+#endif
}
/**
@@ -388,6 +538,18 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { SPC5_SERIAL_LINFLEX1_START_PCTL);
}
#endif
+#if SPC5_SERIAL_USE_LINFLEX2
+ if (&SD3 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
+ SPC5_SERIAL_LINFLEX2_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX3
+ if (&SD4 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
+ SPC5_SERIAL_LINFLEX3_START_PCTL);
+ }
+#endif
}
spc5_linflex_init(sdp, config);
}
@@ -418,6 +580,20 @@ void sd_lld_stop(SerialDriver *sdp) { return;
}
#endif
+#if SPC5_SERIAL_USE_LINFLEX2
+ if (&SD3 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
+ SPC5_SERIAL_LINFLEX2_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX3
+ if (&SD4 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
+ SPC5_SERIAL_LINFLEX3_STOP_PCTL);
+ return;
+ }
+#endif
}
}
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h index 3e34014a5..cbd446b86 100644 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h @@ -27,63 +27,13 @@ #if HAL_USE_SERIAL || defined(__DOXYGEN__)
+#include "spc5_linflex.h"
+
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
- * @name LINIER register bits definitions
- * @{
- */
-#define SPC5_LINIER_HRIE (1U << 0)
-#define SPC5_LINIER_DTIE (1U << 1)
-#define SPC5_LINIER_DRIE (1U << 2)
-#define SPC5_LINIER_DBEIE (1U << 3)
-#define SPC5_LINIER_DBFIE (1U << 4)
-#define SPC5_LINIER_WUIE (1U << 5)
-#define SPC5_LINIER_LSIE (1U << 6)
-#define SPC5_LINIER_BOIE (1U << 7)
-#define SPC5_LINIER_FEIE (1U << 8)
-#define SPC5_LINIER_HEIE (1U << 11)
-#define SPC5_LINIER_CEIE (1U << 12)
-#define SPC5_LINIER_BEIE (1U << 13)
-#define SPC5_LINIER_OCIE (1U << 14)
-#define SPC5_LINIER_SZIE (1U << 15)
-/** @} */
-
-/**
- * @name UARTSR register bits definitions
- * @{
- */
-#define SPC5_UARTSR_NF (1U << 0)
-#define SPC5_UARTSR_DTF (1U << 1)
-#define SPC5_UARTSR_DRF (1U << 2)
-#define SPC5_UARTSR_WUF (1U << 5)
-#define SPC5_UARTSR_RPS (1U << 6)
-#define SPC5_UARTSR_BOF (1U << 7)
-#define SPC5_UARTSR_FEF (1U << 8)
-#define SPC5_UARTSR_RMB (1U << 9)
-#define SPC5_UARTSR_PE0 (1U << 10)
-#define SPC5_UARTSR_PE1 (1U << 11)
-#define SPC5_UARTSR_PE2 (1U << 12)
-#define SPC5_UARTSR_PE3 (1U << 13)
-#define SPC5_UARTSR_OCF (1U << 14)
-#define SPC5_UARTSR_SZF (1U << 15)
-/** @} */
-
-/**
- * @name UARTCR register bits definitions
- * @{
- */
-#define SPC5_UARTCR_UART (1U << 0)
-#define SPC5_UARTCR_WL (1U << 1)
-#define SPC5_UARTCR_PCE (1U << 2)
-#define SPC5_UARTCR_OP (1U << 3)
-#define SPC5_UARTCR_TXEN (1U << 4)
-#define SPC5_UARTCR_RXEN (1U << 5)
-/** @} */
-
-/**
* @name Serial driver allowable modes
* @{
*/
@@ -104,7 +54,7 @@ * @details If set to @p TRUE the support for LINFlex-0 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX0 TRUE
+#define SPC5_SERIAL_USE_LINFLEX0 FALSE
#endif
/**
@@ -112,7 +62,23 @@ * @details If set to @p TRUE the support for LINFlex-1 is included.
*/
#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__)
-#define SPC5_SERIAL_USE_LINFLEX1 TRUE
+#define SPC5_SERIAL_USE_LINFLEX1 FALSE
+#endif
+
+/**
+ * @brief LINFlex-2 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-2 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX2 FALSE
+#endif
+
+/**
+ * @brief LINFlex-3 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-3 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX3 FALSE
#endif
/**
@@ -130,6 +96,20 @@ #endif
/**
+ * @brief LINFlex-2 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-3 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_PRIORITY 8
+#endif
+
+/**
* @brief LINFlex-0 peripheral configuration when started.
* @note The default configuration is 1 (always run) in run mode and
* 2 (only halt) in low power mode. The defaults of the run modes
@@ -173,6 +153,50 @@ SPC5_ME_PCTL_LP(0))
#endif
+/**
+ * @brief LINFlex-2 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-2 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-3 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-3 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -238,7 +262,7 @@ typedef struct { uint8_t ob[SERIAL_BUFFERS_SIZE]; \
/* End of the mandatory fields.*/ \
/* Pointer to the volatile LINFlex registers block.*/ \
- volatile struct LINFLEX_tag *linflexp;
+ volatile struct spc5_linflex *linflexp;
/*===========================================================================*/
/* Driver macros. */
diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h new file mode 100644 index 000000000..28e7575c4 --- /dev/null +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/spc5_linflex.h @@ -0,0 +1,510 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_linflex.h
+ * @brief LINFlex helper driver header.
+ *
+ * @addtogroup SPC5xx_LINFLEX
+ * @{
+ */
+
+#ifndef _SPC5_LINFLEX_H_
+#define _SPC5_LINFLEX_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name LINIER register bits definitions
+ * @{
+ */
+#define SPC5_LINIER_HRIE (1U << 0)
+#define SPC5_LINIER_DTIE (1U << 1)
+#define SPC5_LINIER_DRIE (1U << 2)
+#define SPC5_LINIER_DBEIE (1U << 3)
+#define SPC5_LINIER_DBFIE (1U << 4)
+#define SPC5_LINIER_WUIE (1U << 5)
+#define SPC5_LINIER_LSIE (1U << 6)
+#define SPC5_LINIER_BOIE (1U << 7)
+#define SPC5_LINIER_FEIE (1U << 8)
+#define SPC5_LINIER_HEIE (1U << 11)
+#define SPC5_LINIER_CEIE (1U << 12)
+#define SPC5_LINIER_BEIE (1U << 13)
+#define SPC5_LINIER_OCIE (1U << 14)
+#define SPC5_LINIER_SZIE (1U << 15)
+/** @} */
+
+/**
+ * @name UARTSR register bits definitions
+ * @{
+ */
+#define SPC5_UARTSR_NF (1U << 0)
+#define SPC5_UARTSR_DTF (1U << 1)
+#define SPC5_UARTSR_DRF (1U << 2)
+#define SPC5_UARTSR_WUF (1U << 5)
+#define SPC5_UARTSR_RPS (1U << 6)
+#define SPC5_UARTSR_BOF (1U << 7)
+#define SPC5_UARTSR_FEF (1U << 8)
+#define SPC5_UARTSR_RMB (1U << 9)
+#define SPC5_UARTSR_PE0 (1U << 10)
+#define SPC5_UARTSR_PE1 (1U << 11)
+#define SPC5_UARTSR_PE2 (1U << 12)
+#define SPC5_UARTSR_PE3 (1U << 13)
+#define SPC5_UARTSR_OCF (1U << 14)
+#define SPC5_UARTSR_SZF (1U << 15)
+/** @} */
+
+/**
+ * @name UARTCR register bits definitions
+ * @{
+ */
+#define SPC5_UARTCR_UART (1U << 0)
+#define SPC5_UARTCR_WL (1U << 1)
+#define SPC5_UARTCR_PCE (1U << 2)
+#define SPC5_UARTCR_OP (1U << 3)
+#define SPC5_UARTCR_TXEN (1U << 4)
+#define SPC5_UARTCR_RXEN (1U << 5)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+
+struct spc5_linflex {
+
+ int16_t LINFLEX_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CCD :1;
+ vuint16_t CFD :1;
+ vuint16_t LASE :1;
+ vuint16_t AWUM :1;
+ vuint16_t MBL :4;
+ vuint16_t BF :1;
+ vuint16_t SFTM :1;
+ vuint16_t LBKM :1;
+ vuint16_t MME :1;
+ vuint16_t SBDT :1;
+ vuint16_t RBLM :1;
+ vuint16_t SLEEP :1;
+ vuint16_t INIT :1;
+ } B;
+ } LINCR1;
+
+ int16_t LINFLEX_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZIE :1;
+ vuint16_t OCIE :1;
+ vuint16_t BEIE :1;
+ vuint16_t CEIE :1;
+ vuint16_t HEIE :1;
+ vuint16_t :2;
+ vuint16_t FEIE :1;
+ vuint16_t BOIE :1;
+ vuint16_t LSIE :1;
+ vuint16_t WUIE :1;
+ vuint16_t DBFIE :1;
+ vuint16_t DBEIE :1;
+ vuint16_t DRIE :1;
+ vuint16_t DTIE :1;
+ vuint16_t HRIE :1;
+ } B;
+ } LINIER;
+
+ int16_t LINFLEX_reserved3;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LINS :4;
+ vuint16_t :2;
+ vuint16_t RMB :1;
+ vuint16_t :1;
+ vuint16_t RBSY :1;
+ vuint16_t RPS :1;
+ vuint16_t WUF :1;
+ vuint16_t DBFF :1;
+ vuint16_t DBEF :1;
+ vuint16_t DRF :1;
+ vuint16_t DTF :1;
+ vuint16_t HRF :1;
+ } B;
+ } LINSR;
+
+ int16_t LINFLEX_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF :1;
+ vuint16_t OCF :1;
+ vuint16_t BEF :1;
+ vuint16_t CEF :1;
+ vuint16_t SFEF :1;
+ vuint16_t BDEF :1;
+ vuint16_t IDPEF :1;
+ vuint16_t FEF :1;
+ vuint16_t BOF :1;
+ vuint16_t :6;
+ vuint16_t NF :1;
+ } B;
+ } LINESR;
+
+ int16_t LINFLEX_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t TDFL :2;
+ vuint16_t :1;
+ vuint16_t RDFL :2;
+ vuint16_t :4;
+ vuint16_t RXEN :1;
+ vuint16_t TXEN :1;
+ vuint16_t OP :1;
+ vuint16_t PCE :1;
+ vuint16_t WL :1;
+ vuint16_t UART :1;
+ } B;
+ } UARTCR;
+
+ int16_t LINFLEX_reserved6;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF :1;
+ vuint16_t OCF :1;
+ vuint16_t PE :4;
+ vuint16_t RMB :1;
+ vuint16_t FEF :1;
+ vuint16_t BOF :1;
+ vuint16_t RPS :1;
+ vuint16_t WUF :1;
+ vuint16_t :2;
+ vuint16_t DRF :1;
+ vuint16_t DTF :1;
+ vuint16_t NF :1;
+ } B;
+ } UARTSR;
+
+ int16_t LINFLEX_reserved7;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t LTOM :1;
+ vuint16_t IOT :1;
+ vuint16_t TOCE :1;
+ vuint16_t CNT :8;
+ } B;
+ } LINTCSR;
+
+ int16_t LINFLEX_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OC2 :8;
+ vuint16_t OC1 :8;
+ } B;
+ } LINOCR;
+
+ int16_t LINFLEX_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t RTO :4;
+ vuint16_t :1;
+ vuint16_t HTO :7;
+ } B;
+ } LINTOCR;
+
+ int16_t LINFLEX_reserved10;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t DIV_F :4;
+ } B;
+ } LINFBRR;
+
+ int16_t LINFLEX_reserved11;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DIV_M :13;
+ } B;
+ } LINIBRR;
+
+ int16_t LINFLEX_reserved12;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t CF :8;
+ } B;
+ } LINCFR;
+
+ int16_t LINFLEX_reserved13;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t IOBE :1;
+ vuint16_t IOPE :1;
+ vuint16_t WURQ :1;
+ vuint16_t DDRQ :1;
+ vuint16_t DTRQ :1;
+ vuint16_t ABRQ :1;
+ vuint16_t HTRQ :1;
+ vuint16_t :8;
+ } B;
+ } LINCR2;
+
+ int16_t LINFLEX_reserved14;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DFL :6;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } BIDR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3 :8;
+ vuint32_t DATA2 :8;
+ vuint32_t DATA1 :8;
+ vuint32_t DATA0 :8;
+ } B;
+ } BDRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7 :8;
+ vuint32_t DATA6 :8;
+ vuint32_t DATA5 :8;
+ vuint32_t DATA4 :8;
+ } B;
+ } BDRM;
+
+ int16_t LINFLEX_reserved15;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t FACT :8;
+ } B;
+ } IFER;
+
+ int16_t LINFLEX_reserved16;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t IFMI :4;
+ } B;
+ } IFMI;
+
+ int16_t LINFLEX_reserved17;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t IFM :4;
+ } B;
+ } IFMR;
+
+ int16_t LINFLEX_reserved18;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR0;
+
+ int16_t LINFLEX_reserved19;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR1;
+
+ int16_t LINFLEX_reserved20;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR2;
+
+ int16_t LINFLEX_reserved21;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR3;
+
+ int16_t LINFLEX_reserved22;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR4;
+
+ int16_t LINFLEX_reserved23;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR5;
+
+ int16_t LINFLEX_reserved24;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR6;
+
+ int16_t LINFLEX_reserved25;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR7;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/**
+ * @name LINFlex units references
+ * @{
+ */
+#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE40000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE44000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFFE48000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFFE4C000UL)
+#endif
+/** @} */
+
+#endif /* _SPC5_LINFLEX_H_ */
+
+/** @} */
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