diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
| commit | 8ca210a4af9fd039e290cfcc309adde543999c1f (patch) | |
| tree | 1aa594d5e65d5ebabdd358acbe8d3a9ac29f2070 /os/hal/platforms/SPC5xx/DSPI_v1 | |
| parent | cb453a3a12464dd71856b1354d083b5b02260870 (diff) | |
| download | ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.gz ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.bz2 ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx/DSPI_v1')
| -rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h | 448 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c | 1218 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h | 532 |
3 files changed, 0 insertions, 2198 deletions
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h b/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h deleted file mode 100644 index 4c6105e15..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spc5_dspi.h +++ /dev/null @@ -1,448 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file DSPI_v1/spc5_dspi.h
- * @brief SPC5xx DSPI header file.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPC5_DSPI_H_
-#define _SPC5_DSPI_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name MCR register definitions
- * @{
- */
-#define SPC5_MCR_MSTR (1U << 31)
-#define SPC5_MCR_CONT_SCKE (1U << 30)
-#define SPC5_MCR_DCONF_MASK (3U << 28)
-#define SPC5_MCR_FRZ (1U << 27)
-#define SPC5_MCR_MTFE (1U << 26)
-#define SPC5_MCR_PCSSE (1U << 25)
-#define SPC5_MCR_ROOE (1U << 24)
-#define SPC5_MCR_PCSIS7 (1U << 23)
-#define SPC5_MCR_PCSIS6 (1U << 22)
-#define SPC5_MCR_PCSIS5 (1U << 21)
-#define SPC5_MCR_PCSIS4 (1U << 20)
-#define SPC5_MCR_PCSIS3 (1U << 19)
-#define SPC5_MCR_PCSIS2 (1U << 18)
-#define SPC5_MCR_PCSIS1 (1U << 17)
-#define SPC5_MCR_PCSIS0 (1U << 16)
-#define SPC5_MCR_DOZE (1U << 15)
-#define SPC5_MCR_MDIS (1U << 14)
-#define SPC5_MCR_DIS_TXF (1U << 13)
-#define SPC5_MCR_DIS_RXF (1U << 12)
-#define SPC5_MCR_CLR_TXF (1U << 11)
-#define SPC5_MCR_CLR_RXF (1U << 10)
-#define SPC5_MCR_SMPL_PT_MASK (3U << 8)
-#define SPC5_MCR_SMPL_PT(n) ((n) << 8)
-#define SPC5_MCR_FCPCS (1U << 2)
-#define SPC5_MCR_PES (1U << 1)
-#define SPC5_MCR_HALT (1U << 0)
-/** @} */
-
-/**
- * @name RSER register definitions
- * @{
- */
-#define SPC5_RSER_TCF_RE (1U << 31)
-#define SPC5_RSER_DSITCF_RE (1U << 29)
-#define SPC5_RSER_EOQF_RE (1U << 28)
-#define SPC5_RSER_TFUF_RE (1U << 27)
-#define SPC5_RSER_SPITCF_RE (1U << 26)
-#define SPC5_RSER_TFFF_RE (1U << 25)
-#define SPC5_RSER_TFFF_DIRS (1U << 24)
-#define SPC5_RSER_DPEF_RE (1U << 22)
-#define SPC5_RSER_SPEF_RE (1U << 21)
-#define SPC5_RSER_DDIF_RE (1U << 20)
-#define SPC5_RSER_RFOF_RE (1U << 19)
-#define SPC5_RSER_RFDF_RE (1U << 17)
-#define SPC5_RSER_RFDF_DIRS (1U << 16)
-/** @} */
-
-/**
- * @name CTAR registers definitions
- * @{
- */
-#define SPC5_CTAR_DBR (1U << 31)
-#define SPC5_CTAR_FMSZ_MASK (15U << 27)
-#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27)
-#define SPC5_CTAR_CPOL (1U << 26)
-#define SPC5_CTAR_CPHA (1U << 25)
-#define SPC5_CTAR_LSBFE (1U << 24)
-#define SPC5_CTAR_PCSSCK_MASK (3U << 22)
-#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22)
-#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22)
-#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22)
-#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22)
-#define SPC5_CTAR_PASC_MASK (3U << 20)
-#define SPC5_CTAR_PASC_PRE1 (0U << 20)
-#define SPC5_CTAR_PASC_PRE3 (1U << 20)
-#define SPC5_CTAR_PASC_PRE5 (2U << 20)
-#define SPC5_CTAR_PASC_PRE7 (3U << 20)
-#define SPC5_CTAR_PDT_MASK (3U << 18)
-#define SPC5_CTAR_PDT_PRE1 (0U << 18)
-#define SPC5_CTAR_PDT_PRE3 (1U << 18)
-#define SPC5_CTAR_PDT_PRE5 (2U << 18)
-#define SPC5_CTAR_PDT_PRE7 (3U << 18)
-#define SPC5_CTAR_PBR_MASK (3U << 16)
-#define SPC5_CTAR_PBR_PRE2 (0U << 16)
-#define SPC5_CTAR_PBR_PRE3 (1U << 16)
-#define SPC5_CTAR_PBR_PRE5 (2U << 16)
-#define SPC5_CTAR_PBR_PRE7 (3U << 16)
-#define SPC5_CTAR_CSSCK_MASK (15U << 12)
-#define SPC5_CTAR_CSSCK_DIV2 (0U << 12)
-#define SPC5_CTAR_CSSCK_DIV4 (1U << 12)
-#define SPC5_CTAR_CSSCK_DIV6 (2U << 12)
-#define SPC5_CTAR_CSSCK_DIV8 (3U << 12)
-#define SPC5_CTAR_CSSCK_DIV16 (4U << 12)
-#define SPC5_CTAR_CSSCK_DIV32 (5U << 12)
-#define SPC5_CTAR_CSSCK_DIV64 (6U << 12)
-#define SPC5_CTAR_CSSCK_DIV128 (7U << 12)
-#define SPC5_CTAR_CSSCK_DIV256 (8U << 12)
-#define SPC5_CTAR_CSSCK_DIV512 (9U << 12)
-#define SPC5_CTAR_CSSCK_DIV1024 (10U << 12)
-#define SPC5_CTAR_CSSCK_DIV2048 (11U << 12)
-#define SPC5_CTAR_CSSCK_DIV4096 (12U << 12)
-#define SPC5_CTAR_CSSCK_DIV8192 (13U << 12)
-#define SPC5_CTAR_CSSCK_DIV16384 (14U << 12)
-#define SPC5_CTAR_CSSCK_DIV32768 (15U << 12)
-#define SPC5_CTAR_ASC_MASK (15U << 8)
-#define SPC5_CTAR_ASC_DIV2 (0U << 8)
-#define SPC5_CTAR_ASC_DIV4 (1U << 8)
-#define SPC5_CTAR_ASC_DIV6 (2U << 8)
-#define SPC5_CTAR_ASC_DIV8 (3U << 8)
-#define SPC5_CTAR_ASC_DIV16 (4U << 8)
-#define SPC5_CTAR_ASC_DIV32 (5U << 8)
-#define SPC5_CTAR_ASC_DIV64 (6U << 8)
-#define SPC5_CTAR_ASC_DIV128 (7U << 8)
-#define SPC5_CTAR_ASC_DIV256 (8U << 8)
-#define SPC5_CTAR_ASC_DIV512 (9U << 8)
-#define SPC5_CTAR_ASC_DIV1024 (10U << 8)
-#define SPC5_CTAR_ASC_DIV2048 (11U << 8)
-#define SPC5_CTAR_ASC_DIV4096 (12U << 8)
-#define SPC5_CTAR_ASC_DIV8192 (13U << 8)
-#define SPC5_CTAR_ASC_DIV16384 (14U << 8)
-#define SPC5_CTAR_ASC_DIV32768 (15U << 8)
-#define SPC5_CTAR_DT_MASK (15U << 4)
-#define SPC5_CTAR_DT_DIV2 (0U << 4)
-#define SPC5_CTAR_DT_DIV4 (1U << 4)
-#define SPC5_CTAR_DT_DIV6 (2U << 4)
-#define SPC5_CTAR_DT_DIV8 (3U << 4)
-#define SPC5_CTAR_DT_DIV16 (4U << 4)
-#define SPC5_CTAR_DT_DIV32 (5U << 4)
-#define SPC5_CTAR_DT_DIV64 (6U << 4)
-#define SPC5_CTAR_DT_DIV128 (7U << 4)
-#define SPC5_CTAR_DT_DIV256 (8U << 4)
-#define SPC5_CTAR_DT_DIV512 (9U << 4)
-#define SPC5_CTAR_DT_DIV1024 (10U << 4)
-#define SPC5_CTAR_DT_DIV2048 (11U << 4)
-#define SPC5_CTAR_DT_DIV4096 (12U << 4)
-#define SPC5_CTAR_DT_DIV8192 (13U << 4)
-#define SPC5_CTAR_DT_DIV16384 (14U << 4)
-#define SPC5_CTAR_DT_DIV32768 (15U << 4)
-#define SPC5_CTAR_BR_MASK (15U << 0)
-#define SPC5_CTAR_BR_DIV2 (0U << 0)
-#define SPC5_CTAR_BR_DIV4 (1U << 0)
-#define SPC5_CTAR_BR_DIV6 (2U << 0)
-#define SPC5_CTAR_BR_DIV8 (3U << 0)
-#define SPC5_CTAR_BR_DIV16 (4U << 0)
-#define SPC5_CTAR_BR_DIV32 (5U << 0)
-#define SPC5_CTAR_BR_DIV64 (6U << 0)
-#define SPC5_CTAR_BR_DIV128 (7U << 0)
-#define SPC5_CTAR_BR_DIV256 (8U << 0)
-#define SPC5_CTAR_BR_DIV512 (9U << 0)
-#define SPC5_CTAR_BR_DIV1024 (10U << 0)
-#define SPC5_CTAR_BR_DIV2048 (11U << 0)
-#define SPC5_CTAR_BR_DIV4096 (12U << 0)
-#define SPC5_CTAR_BR_DIV8192 (13U << 0)
-#define SPC5_CTAR_BR_DIV16384 (14U << 0)
-#define SPC5_CTAR_BR_DIV32768 (15U << 0)
-/** @} */
-
-/**
- * @name PUSHR register definitions
- * @{
- */
-#define SPC5_PUSHR_CONT (1U << 31)
-#define SPC5_PUSHR_CTAS_MASK (3U << 28)
-#define SPC5_PUSHR_CTAS(n) ((n) << 29)
-#define SPC5_PUSHR_EOQ (1U << 27)
-#define SPC5_PUSHR_CTCNT (1U << 26)
-#define SPC5_PUSHR_MASC (1U << 25)
-#define SPC5_PUSHR_MCSC (1U << 24)
-#define SPC5_PUSHR_PCS_MASK (255U << 16)
-#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16)
-#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-struct spc5_dspi {
- union {
- vuint32_t R;
- struct {
- vuint32_t MSTR :1;
- vuint32_t CONT_SCKE :1;
- vuint32_t DCONF :2;
- vuint32_t FRZ :1;
- vuint32_t MTFE :1;
- vuint32_t PCSSE :1;
- vuint32_t ROOE :1;
- vuint32_t PCSIS7 :1;
- vuint32_t PCSIS6 :1;
- vuint32_t PCSIS5 :1;
- vuint32_t PCSIS4 :1;
- vuint32_t PCSIS3 :1;
- vuint32_t PCSIS2 :1;
- vuint32_t PCSIS1 :1;
- vuint32_t PCSIS0 :1;
- vuint32_t :1;
- vuint32_t MDIS :1;
- vuint32_t DIS_TXF :1;
- vuint32_t DIS_RXF :1;
- vuint32_t CLR_TXF :1;
- vuint32_t CLR_RXF :1;
- vuint32_t SMPL_PT :2;
- vuint32_t :7;
- vuint32_t HALT :1;
- } B;
- } MCR; /* Module Configuration Register */
-
- uint32_t dspi_reserved1;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCNT :16;
- vuint32_t :16;
- } B;
- } TCR;
-
- union {
- vuint32_t R;
- struct {
- vuint32_t DBR :1;
- vuint32_t FMSZ :4;
- vuint32_t CPOL :1;
- vuint32_t CPHA :1;
- vuint32_t LSBFE :1;
- vuint32_t PCSSCK :2;
- vuint32_t PASC :2;
- vuint32_t PDT :2;
- vuint32_t PBR :2;
- vuint32_t CSSCK :4;
- vuint32_t ASC :4;
- vuint32_t DT :4;
- vuint32_t BR :4;
- } B;
- } CTAR[8]; /* Clock and Transfer Attributes Registers */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCF :1;
- vuint32_t TXRXS :1;
- vuint32_t :1;
- vuint32_t EOQF :1;
- vuint32_t TFUF :1;
- vuint32_t :1;
- vuint32_t TFFF :1;
- vuint32_t :5;
- vuint32_t RFOF :1;
- vuint32_t :1;
- vuint32_t RFDF :1;
- vuint32_t :1;
- vuint32_t TXCTR :4;
- vuint32_t TXNXTPTR :4;
- vuint32_t RXCTR :4;
- vuint32_t POPNXTPTR :4;
- } B;
- } SR; /* Status Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TCFRE :1;
- vuint32_t :2;
- vuint32_t EOQFRE :1;
- vuint32_t TFUFRE :1;
- vuint32_t :1;
- vuint32_t TFFFRE :1;
- vuint32_t TFFFDIRS :1;
- vuint32_t :4;
- vuint32_t RFOFRE :1;
- vuint32_t :1;
- vuint32_t RFDFRE :1;
- vuint32_t RFDFDIRS :1;
- vuint32_t :16;
- } B;
- } RSER; /* DMA/Interrupt Request Select and Enable Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t CONT :1;
- vuint32_t CTAS :3;
- vuint32_t EOQ :1;
- vuint32_t CTCNT :1;
- vuint32_t :2;
- vuint32_t PCS7 :1;
- vuint32_t PCS6 :1;
- vuint32_t PCS5 :1;
- vuint32_t PCS4 :1;
- vuint32_t PCS3 :1;
- vuint32_t PCS2 :1;
- vuint32_t PCS1 :1;
- vuint32_t PCS0 :1;
- vuint32_t TXDATA :16;
- } B;
- } PUSHR; /* PUSH TX FIFO Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t RXDATA :16;
- } B;
- } POPR; /* POP RX FIFO Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t TXCMD :16;
- vuint32_t TXDATA :16;
- } B;
- } TXFR[5]; /* Transmit FIFO Registers */
-
- vuint32_t DSPI_reserved_txf[11];
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t RXDATA :16;
- } B;
- } RXFR[5]; /* Receive FIFO Registers */
-
- vuint32_t DSPI_reserved_rxf[12];
-
- union {
- vuint32_t R;
- struct {
- vuint32_t MTOE :1;
- vuint32_t :1;
- vuint32_t MTOCNT :6;
- vuint32_t :4;
- vuint32_t TXSS :1;
- vuint32_t TPOL :1;
- vuint32_t TRRE :1;
- vuint32_t CID :1;
- vuint32_t DCONT :1;
- vuint32_t DSICTAS :3;
- vuint32_t :6;
- vuint32_t DPCS5 :1;
- vuint32_t DPCS4 :1;
- vuint32_t DPCS3 :1;
- vuint32_t DPCS2 :1;
- vuint32_t DPCS1 :1;
- vuint32_t DPCS0 :1;
- } B;
- } DSICR; /* DSI Configuration Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t SER_DATA :16;
- } B;
- } SDR; /* DSI Serialization Data Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t ASER_DATA :16;
- } B;
- } ASDR; /* DSI Alternate Serialization Data Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t COMP_DATA :16;
- } B;
- } COMPR; /* DSI Transmit Comparison Register */
-
- union {
- vuint32_t R;
- struct {
- vuint32_t :16;
- vuint32_t DESER_DATA :16;
- } B;
- } DDR; /* DSI deserialization Data Register */
-
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name DSPI units references
- * @{
- */
-#if SPC5_HAS_DSPI0 || defined(__DOXYGEN__)
-#define SPC5_DSPI0 (*(struct spc5_dspi *)0xFFF90000U)
-#endif
-
-#if SPC5_HAS_DSPI1 || defined(__DOXYGEN__)
-#define SPC5_DSPI1 (*(struct spc5_dspi *)0xFFF94000U)
-#endif
-
-#if SPC5_HAS_DSPI2 || defined(__DOXYGEN__)
-#define SPC5_DSPI2 (*(struct spc5_dspi *)0xFFF98000U)
-#endif
-
-#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
-#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U)
-#endif
-
-#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
-#define SPC5_DSPI4 (*(struct spc5_dspi *)0x8FFA0000U)
-#endif
-/** @} */
-
-#endif /* _SPC5_DSPI_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c deleted file mode 100644 index f5db08a75..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c +++ /dev/null @@ -1,1218 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/DSPI_v1/spi_lld.c
- * @brief SPC5xx SPI subsystem low level driver source.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/* Some forward declarations.*/
-static void spi_serve_rx_irq(edma_channel_t channel, void *p);
-static void spi_serve_tx_irq(edma_channel_t channel, void *p);
-static void spi_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr);
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/* Excluded PUSHR bits.*/
-#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \
- SPC5_PUSHR_EOQ | \
- SPC5_PUSHR_TXDATA_MASK)
-
-#define DSPI_POPR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 3)
-#define DSPI_POPR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 2)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief SPID1 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-SPIDriver SPID1;
-#endif
-
-/**
- * @brief SPID2 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-SPIDriver SPID2;
-#endif
-
-/**
- * @brief SPID3 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-SPIDriver SPID3;
-#endif
-
-/**
- * @brief SPID4 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-SPIDriver SPID4;
-#endif
-
-/**
- * @brief SPID5 driver identifier.
- */
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-SPIDriver SPID5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI0 TX1.
- */
-static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
- SPC5_DSPI0_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI0_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief DMA configuration for DSPI0 TX2.
- */
-static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
- SPC5_DSPI0_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1
-};
-
-/**
- * @brief DMA configuration for DSPI0 RX.
- */
-static const edma_channel_config_t spi_dspi0_rx_dma_config = {
- SPC5_DSPI0_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI0_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1
-};
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI1 TX1.
- */
-static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
- SPC5_DSPI1_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI1_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief DMA configuration for DSPI1 TX2.
- */
-static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
- SPC5_DSPI1_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2
-};
-
-/**
- * @brief DMA configuration for DSPI1 RX.
- */
-static const edma_channel_config_t spi_dspi1_rx_dma_config = {
- SPC5_DSPI1_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI1_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2
-};
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI2 TX1.
- */
-static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
- SPC5_DSPI2_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI2_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief DMA configuration for DSPI2 TX2.
- */
-static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
- SPC5_DSPI2_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3
-};
-
-/**
- * @brief DMA configuration for DSPI2 RX.
- */
-static const edma_channel_config_t spi_dspi2_rx_dma_config = {
- SPC5_DSPI2_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI2_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3
-};
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI3 TX1.
- */
-static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
- SPC5_DSPI3_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI3_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief DMA configuration for DSPI3 TX2.
- */
-static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
- SPC5_DSPI3_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4
-};
-
-/**
- * @brief DMA configuration for DSPI3 RX.
- */
-static const edma_channel_config_t spi_dspi3_rx_dma_config = {
- SPC5_DSPI3_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI3_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4
-};
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-/**
- * @brief DMA configuration for DSPI4 TX1.
- */
-static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
- SPC5_DSPI4_TX1_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI4_TX1_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief DMA configuration for DSPI4 TX2.
- */
-static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
- SPC5_DSPI4_TX2_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- 0,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5
-};
-
-/**
- * @brief DMA configuration for DSPI4 RX.
- */
-static const edma_channel_config_t spi_dspi4_rx_dma_config = {
- SPC5_DSPI4_RX_DMA_CH_ID,
-#if SPC5_EDMA_HAS_MUX
- SPC5_DSPI4_RX_DMA_DEV_ID,
-#endif
- SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
- spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5
-};
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Starts reception using DMA ignoring the received data.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_rx_ignore(SPIDriver *spip, size_t n) {
- static uint32_t datasink;
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR8_ADDRESS(spip), /* src. */
- &datasink, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 0, /* ssize, 16 bits transfers.*/
- 0, /* dsize, 16 bits transfers.*/
- 1, /* nbytes, always one. */
- n, /* iter. */
- 0, /* slast. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts reception using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx8(SPIDriver *spip,
- size_t n,
- uint8_t *rxbuf) {
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR8_ADDRESS(spip), /* src. */
- rxbuf, /* dst. */
- 0, /* soff, do not advance. */
- 1, /* doff, advance by one. */
- 0, /* ssize, 8 bits transfers. */
- 0, /* dsize, 8 bits transfers. */
- 1, /* nbytes, always one. */
- n, /* iter. */
- 0, /* slast. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts reception using DMA for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-static void spi_start_dma_rx16(SPIDriver *spip,
- size_t n,
- uint16_t *rxbuf) {
-
- edmaChannelSetup(spip->rx_channel, /* channel. */
- DSPI_POPR16_ADDRESS(spip), /* src. */
- rxbuf, /* dst. */
- 0, /* soff, do not advance. */
- 2, /* doff, advance by two. */
- 1, /* ssize, 16 bits transfers.*/
- 1, /* dsize, 16 bits transfers.*/
- 2, /* nbytes, always two. */
- n, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- edmaChannelStart(spip->rx_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_start_dma_tx_ignore(SPIDriver *spip, size_t n) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr | (uint32_t)0xFFFF;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_last = spip->tx_intbuf;
-
- /* Setting up TX1 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx1_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* Starting TX1 DMA channel.*/
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx8(SPIDriver *spip,
- size_t n,
- const uint8_t *txbuf) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
- /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
- edmaChannelSetupLinked(
- spip->tx1_channel, /* channel. */
- spip->tx2_channel, /* linkch. */
- txbuf + 1, /* src. */
- ((const uint8_t *)&spip->tx_intbuf) + 3, /* dst. */
- 1, /* soff, advance by 1. */
- 0, /* doff, do not advance. */
- 0, /* ssize, 8 bits transfers. */
- 0, /* dsize, 8 bits transfers. */
- 1, /* nbytes, always one. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ); /* mode. */
-
- /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx2_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* The last frame will be pushed by the TX DMA operation completion
- callback.*/
- spip->tx_last = txbuf[n - 1];
-
- /* Starting TX DMA channels.*/
- edmaChannelStart(spip->tx2_channel);
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts transmission using DMA for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_start_dma_tx16(SPIDriver *spip,
- size_t n,
- const uint16_t *txbuf) {
-
- /* Preparing the TX intermediate buffer with the fixed part.*/
- spip->tx_intbuf = spip->config->pushr;
-
- /* The first frame is pushed by the CPU, then the DMA is activated to
- send the following frames. This should reduce latency on the operation
- start.*/
- spip->dspi->PUSHR.R = spip->tx_intbuf | (uint32_t)*txbuf;
-
- /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
- edmaChannelSetupLinked(
- spip->tx1_channel, /* channel. */
- spip->tx2_channel, /* linkch. */
- txbuf + 1, /* src. */
- ((const uint8_t *)&spip->tx_intbuf) + 2, /* dst. */
- 1, /* soff, advance by 1. */
- 0, /* doff, do not advance. */
- 1, /* ssize, 16 bits transfers.*/
- 1, /* dsize, 16 bits transfers.*/
- 1, /* nbytes, always one. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ); /* mode. */
-
- /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
- edmaChannelSetup(spip->tx2_channel, /* channel. */
- &spip->tx_intbuf, /* src. */
- &spip->dspi->PUSHR.R, /* dst. */
- 0, /* soff, do not advance. */
- 0, /* doff, do not advance. */
- 2, /* ssize, 32 bits transfers.*/
- 2, /* dsize, 32 bits transfers.*/
- 4, /* nbytes, always four. */
- n - 2, /* iter. */
- 0, /* slast, no source adjust. */
- 0, /* dlast, no dest.adjust. */
- EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
-
- /* The last frame will be pushed by the TX DMA operation completion
- callback.*/
- spip->tx_last = txbuf[n - 1];
-
- /* Starting TX DMA channels.*/
- edmaChannelStart(spip->tx2_channel);
- edmaChannelStart(spip->tx1_channel);
-}
-
-/**
- * @brief Starts idle bits using FIFO pre-filling.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- *
- * @notapi
- */
-static void spi_tx_prefill_ignore(SPIDriver *spip, size_t n) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)0xFFFF) &
- ~SPC5_PUSHR_CONT;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)0xFFFF;
- } while (TRUE);
-}
-
-/**
- * @brief Starts transmission using FIFO pre-filling for frames up to 8 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill8(SPIDriver *spip,
- size_t n,
- const uint8_t *txbuf) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf) &
- ~SPC5_PUSHR_CONT;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
- txbuf++;
- } while (TRUE);
-}
-
-/**
- * @brief Starts transmission using FIFO pre-filling for frames up to 16 bits.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-static void spi_tx_prefill16(SPIDriver *spip,
- size_t n,
- const uint16_t *txbuf) {
- uint32_t cmd = spip->config->pushr;
-
- do {
- if (--n == 0) {
- spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
- break;
- }
- spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
- txbuf++;
- } while (TRUE);
-}
-
-/**
- * @brief Shared RX DMA events service routine.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
- SPIDriver *spip = (SPIDriver *)p;
-
- /* Clearing RX channel state.*/
- edmaChannelStop(channel);
-
- /* Stops the DSPI and clears the queues.*/
- spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
- /* Portable SPI ISR code defined in the high level driver, note, it is
- a macro.*/
- _spi_isr_code(spip);
-}
-
-/**
- * @brief Shared TX1/TX2 DMA events service routine.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- *
- * @notapi
- */
-static void spi_serve_tx_irq(edma_channel_t channel, void *p) {
- SPIDriver *spip = (SPIDriver *)p;
-
- (void)channel;
-
- /* Clearing TX channels state.*/
- edmaChannelStop(spip->tx1_channel);
- edmaChannelStop(spip->tx2_channel);
-
- /* If the TX FIFO is full then the push of the last frame is delagated to
- an interrupt handler else it is performed immediately. Both conditions
- can be true depending on the SPI speed and ISR latency.*/
- if (spip->dspi->SR.B.TFFF) {
- spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
- }
- else {
- spip->dspi->RSER.B.TFFFDIRS = 0;
- }
-}
-
-/**
- * @brief Shared ISR for DMA error events.
- *
- * @param[in] channel the channel number
- * @param[in] p parameter for the registered function
- * @param[in] esr content of the ESR register
- *
- * @notapi
- */
-static void spi_serve_dma_error_irq(edma_channel_t channel,
- void *p,
- uint32_t esr) {
- SPIDriver *spip = (SPIDriver *)p;
-
- (void)channel;
- (void)esr;
-
- /* Stops the DSPI and clears the queues.*/
- spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
-
- edmaChannelStop(spip->tx1_channel);
- edmaChannelStop(spip->tx2_channel);
- edmaChannelStop(spip->rx_channel);
-
- SPC5_SPI_DMA_ERROR_HOOK(spip);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI0_TFFF_HANDLER)
-#error "SPC5_DSPI0_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI0 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI0.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI0.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI0.PUSHR.R = (SPID1.config->pushr | SPID1.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI1_TFFF_HANDLER)
-#error "SPC5_DSPI1_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI1 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI1.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI1.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI1.PUSHR.R = (SPID2.config->pushr | SPID2.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI2_TFFF_HANDLER)
-#error "SPC5_DSPI2_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI2 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI2.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI2.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI2.PUSHR.R = (SPID3.config->pushr | SPID3.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI3_TFFF_HANDLER)
-#error "SPC5_DSPI3_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI3 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI3.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI3.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI3.PUSHR.R = (SPID4.config->pushr | SPID4.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
-#if !defined(SPC5_DSPI4_TFFF_HANDLER)
-#error "SPC5_DSPI4_TFFF_HANDLER not defined"
-#endif
-/**
- * @brief DSPI4 TFFF interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_DSPI4_TFFF_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- chSysLockFromIsr();
-
- /* Interrupt served and back to DMA mode.*/
- SPC5_DSPI4.RSER.B.TFFFDIRS = 1;
- SPC5_DSPI4.SR.B.TFFF = 1;
-
- /* Pushing last frame.*/
- SPC5_DSPI4.PUSHR.R = (SPID5.config->pushr | SPID5.tx_last | SPC5_PUSHR_EOQ) &
- ~SPC5_PUSHR_CONT;
-
- chSysUnlockFromIsr();
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_SPI_USE_DSPI4 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if SPC5_SPI_USE_DSPI0
- /* Driver initialization.*/
- spiObjectInit(&SPID1);
- SPC5_DSPI0_ENABLE_CLOCK();
- SPID1.dspi = &SPC5_DSPI0;
- SPID1.tx1_channel = EDMA_ERROR;
- SPID1.tx2_channel = EDMA_ERROR;
- SPID1.rx_channel = EDMA_ERROR;
- SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI0_MCR;
- INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
- /* Driver initialization.*/
- SPC5_DSPI1_ENABLE_CLOCK();
- spiObjectInit(&SPID2);
- SPID2.dspi = &SPC5_DSPI1;
- SPID2.tx1_channel = EDMA_ERROR;
- SPID2.tx2_channel = EDMA_ERROR;
- SPID2.rx_channel = EDMA_ERROR;
- SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI1_MCR;
- INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
- /* Driver initialization.*/
- spiObjectInit(&SPID3);
- SPC5_DSPI2_ENABLE_CLOCK();
- SPID3.dspi = &SPC5_DSPI2;
- SPID3.tx1_channel = EDMA_ERROR;
- SPID3.tx2_channel = EDMA_ERROR;
- SPID3.rx_channel = EDMA_ERROR;
- SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI2_MCR;
- INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
- /* Driver initialization.*/
- spiObjectInit(&SPID4);
- SPC5_DSPI3_ENABLE_CLOCK();
- SPID4.dspi = &SPC5_DSPI3;
- SPID4.tx1_channel = EDMA_ERROR;
- SPID4.tx2_channel = EDMA_ERROR;
- SPID4.rx_channel = EDMA_ERROR;
- SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI3_MCR;
- INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
- /* Driver initialization.*/
- spiObjectInit(&SPID5);
- SPC5_DSPI4_ENABLE_CLOCK();
- SPID5.dspi = &SPC5_DSPI4;
- SPID5.tx1_channel = EDMA_ERROR;
- SPID5.tx2_channel = EDMA_ERROR;
- SPID5.rx_channel = EDMA_ERROR;
- SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI4_MCR;
- INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
-#endif /* SPC5_SPI_USE_DSPI4 */
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- chDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
- "spi_lld_start(), #1", "invalid PUSHR bits specified");
-
- if (spip->state == SPI_STOP) {
- /* Enables the peripheral.*/
-
-#if SPC5_SPI_USE_DSPI0
- if (&SPID1 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi0_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi0_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI0 */
-
-#if SPC5_SPI_USE_DSPI1
- if (&SPID2 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi1_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi1_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI1 */
-
-#if SPC5_SPI_USE_DSPI2
- if (&SPID3 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi2_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi2_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI2 */
-
-#if SPC5_SPI_USE_DSPI3
- if (&SPID4 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi3_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi3_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI3 */
-
-#if SPC5_SPI_USE_DSPI4
- if (&SPID5 == spip) {
- spip->tx1_channel = edmaChannelAllocate(&spi_dspi4_tx1_dma_config);
- spip->tx2_channel = edmaChannelAllocate(&spi_dspi4_tx2_dma_config);
- spip->rx_channel = edmaChannelAllocate(&spi_dspi4_rx_dma_config);
- }
-#endif /* SPC5_SPI_USE_DSPI5 */
-
- chDbgAssert((spip->tx1_channel != EDMA_ERROR) &&
- (spip->tx2_channel != EDMA_ERROR) &&
- (spip->rx_channel != EDMA_ERROR),
- "spi_lld_start(), #2", "channel cannot be allocated");
- }
-
- /* Configures the peripheral.*/
- spip->dspi->MCR.B.MDIS = 0;
- spip->dspi->CTAR[0].R = spip->config->ctar0;
- spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
- SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
- spip->dspi->SR.R = spip->dspi->SR.R;
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- if (spip->state == SPI_READY) {
- /* Releases the allocated EDMA channels.*/
- edmaChannelRelease(spip->tx1_channel);
- edmaChannelRelease(spip->tx2_channel);
- edmaChannelRelease(spip->rx_channel);
-
- /* Resets the peripheral.*/
- spip->dspi->CTAR[0].R = 0;
- spip->dspi->RSER.R = 0;
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.R |= SPC5_MCR_HALT |
- SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
- spip->dspi->MCR.B.MDIS = 1;
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This asynchronous function starts the transmission of a series of
- * idle words on the SPI bus and ignores the received data.
- * @post At the end of the operation the configured callback is invoked.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx_ignore(spip, n);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill_ignore(spip, n);
- }
- else {
- spi_start_dma_tx_ignore(spip, n);
- }
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This asynchronous function starts a simultaneous transmit/receive
- * operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx8(spip, n, rxbuf);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill8(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx8(spip, n, txbuf);
- }
- }
- else {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx16(spip, n, rxbuf);
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill16(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx16(spip, n, txbuf);
- }
- }
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @details This asynchronous function starts a transmit operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx_ignore(spip, n);
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill8(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx8(spip, n, txbuf);
- }
- }
- else {
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill16(spip, n, txbuf);
- }
- else {
- spi_start_dma_tx16(spip, n, txbuf);
- }
- }
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @details This asynchronous function starts a receive operation.
- * @post At the end of the operation the configured callback is invoked.
- * @note The buffers are organized as uint8_t arrays for data sizes below or
- * equal to 8 bits else it is organized as uint16_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- /* Starting transfer.*/
- spip->dspi->SR.R = spip->dspi->SR.R;
- spip->dspi->MCR.B.HALT = 0;
-
- /* DMAs require a different setup depending on the frame size.*/
- if (spip->dspi->CTAR[0].B.FMSZ < 8) {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx8(spip, n, rxbuf);
- }
- else {
- /* Setting up the RX DMA channel.*/
- spi_start_dma_rx16(spip, n, rxbuf);
- }
-
- if (n <= SPC5_DSPI_FIFO_DEPTH) {
- /* If the total transfer size is smaller than the TX FIFO size then
- the whole transmitted data is pushed here and the TX DMA is not
- activated.*/
- spi_tx_prefill_ignore(spip, n);
- }
- else {
- spi_start_dma_tx_ignore(spip, n);
- }
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
- uint32_t popr;
-
- spip->dspi->MCR.B.HALT = 0;
- spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr |
- (uint32_t)frame) & ~SPC5_PUSHR_CONT;
- while (!spip->dspi->SR.B.RFDF)
- ;
- popr = spip->dspi->POPR.R;
- spip->dspi->MCR.B.HALT = 1;
- return (uint16_t)popr;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h deleted file mode 100644 index 1e2e9fd1c..000000000 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h +++ /dev/null @@ -1,532 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file SPC5xx/DSPI_v1/spi_lld.h
- * @brief SPC5xx SPI subsystem low level driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-#include "spc5_dspi.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief SPID1 driver enable switch.
- * @details If set to @p TRUE the support for DSPI0 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI0) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI0 FALSE
-#endif
-
-/**
- * @brief SPID2 driver enable switch.
- * @details If set to @p TRUE the support for DSPI1 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI1 FALSE
-#endif
-
-/**
- * @brief SPID3 driver enable switch.
- * @details If set to @p TRUE the support for DSPI2 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI2) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI2 FALSE
-#endif
-
-/**
- * @brief SPID4 driver enable switch.
- * @details If set to @p TRUE the support for DSPI3 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI3) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI3 FALSE
-#endif
-
-/**
- * @brief SPID5 driver enable switch.
- * @details If set to @p TRUE the support for DSPI4 is included.
- */
-#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__)
-#define SPC5_SPI_USE_DSPI4 FALSE
-#endif
-
-/**
- * @brief DSPI0 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI1 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSP2 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI3 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI4 MCR PCS defaults.
- */
-#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
- SPC5_MCR_PCSIS1 | \
- SPC5_MCR_PCSIS2 | \
- SPC5_MCR_PCSIS3 | \
- SPC5_MCR_PCSIS4 | \
- SPC5_MCR_PCSIS5 | \
- SPC5_MCR_PCSIS6 | \
- SPC5_MCR_PCSIS7)
-#endif
-
-/**
- * @brief DSPI0 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI1 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI2 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI3 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI4 DMA IRQ priority.
- */
-#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
-#endif
-
-/**
- * @brief SPI DMA error hook.
- */
-#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
-#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
-#endif
-
-/**
- * @brief DSPI0 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI1 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI2 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI3 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI4 DMA priority.
- */
-#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_IRQ_PRIO 10
-#endif
-
-/**
- * @brief DSPI0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI2 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI2 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI2_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI3 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI3 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI3_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-
-/**
- * @brief DSPI4 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief DSPI4 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_SPI_DSPI4_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !SPC5_HAS_DSPI0
-#error "DSPI0 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !SPC5_HAS_DSPI1
-#error "DSPI1 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !SPC5_HAS_DSPI2
-#error "DSPI2 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !SPC5_HAS_DSPI3
-#error "DSPI3 not present in the selected device"
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !SPC5_HAS_DSPI4
-#error "DSPI4 not present in the selected device"
-#endif
-
-#if !SPC5_SPI_USE_DSPI0 && !SPC5_SPI_USE_DSPI1 && \
- !SPC5_SPI_USE_DSPI2 && !SPC5_SPI_USE_DSPI3 && \
- !SPC5_SPI_USE_DSPI4
-#error "SPI driver activated but no DSPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Operation complete callback.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number.
- */
- uint16_t sspad;
- /**
- * @brief DSPI CTAR0 value for this session.
- */
- uint32_t ctar0;
- /**
- * @brief DSPI PUSHR command for this session.
- * @note Only CTAR0 can be referenced, the other CTARs are not
- * initialized. The data part must be left to zero.
- */
- uint32_t pushr;
-} SPIConfig;
-
-/**
- * @brief Structure representing an SPI driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- Thread *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the DSPI registers block.
- */
- struct spc5_dspi *dspi;
- /**
- * @brief EDMA channel used for data memory to memory copy.
- */
- edma_channel_t tx1_channel;
- /**
- * @brief EDMA channel used for transmit.
- */
- edma_channel_t tx2_channel;
- /**
- * @brief EDMA channel used for receive.
- */
- edma_channel_t rx_channel;
- /**
- * @brief Last frame of a transmission sequence.
- */
- uint32_t tx_last;
- /**
- * @brief TX intermediate buffer.
- * @note This field is written by the TX1 DMA channel and read by the
- * TX2 DMA channel.
- */
- uint32_t tx_intbuf;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_SPI_USE_DSPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if SPC5_SPI_USE_DSPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#if SPC5_SPI_USE_DSPI2 && !defined(__DOXYGEN__)
-extern SPIDriver SPID3;
-#endif
-
-#if SPC5_SPI_USE_DSPI3 && !defined(__DOXYGEN__)
-extern SPIDriver SPID4;
-#endif
-
-#if SPC5_SPI_USE_DSPI4 && !defined(__DOXYGEN__)
-extern SPIDriver SPID5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
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