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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-11 14:17:39 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-11 14:17:39 +0000 |
| commit | a6962b212d32bbf1e0bb7154e10184527470cd9a (patch) | |
| tree | b330e89b4c3641358c5546cd7b5f9bb02cb94572 /os/hal/platforms/SPC563Mxx/hal_lld.c | |
| parent | bc2bcd741781f51daa56af86c7e67f0f91eb50a2 (diff) | |
| download | ChibiOS-a6962b212d32bbf1e0bb7154e10184527470cd9a.tar.gz ChibiOS-a6962b212d32bbf1e0bb7154e10184527470cd9a.tar.bz2 ChibiOS-a6962b212d32bbf1e0bb7154e10184527470cd9a.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4903 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC563Mxx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/SPC563Mxx/hal_lld.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c index 89a5d9e45..a140536e3 100644 --- a/os/hal/platforms/SPC563Mxx/hal_lld.c +++ b/os/hal/platforms/SPC563Mxx/hal_lld.c @@ -58,7 +58,7 @@ void hal_lld_init(void) { "mtspr 1013, %%r3": : : "r3");
/* FLASH wait states and prefetching setup.*/
- CFLASH0.BIUCR.R = SPC_FLASH_BIUCR | SPC_FLASH_WS;
+ CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
CFLASH0.BIUCR2.R = 0;
CFLASH0.PFCR3.R = 0;
@@ -81,7 +81,7 @@ void hal_lld_init(void) { /* Downcounter timer initialized for system tick use, TB enabled for debug
and measurements.*/
- n = SPC_SYSCLK / CH_FREQUENCY;
+ n = SPC5_SYSCLK / CH_FREQUENCY;
asm volatile ("li %%r3, 0 \t\n"
"mtspr 284, %%r3 \t\n" /* Clear TBL register. */
"mtspr 285, %%r3 \t\n" /* Clear TBU register. */
@@ -110,18 +110,18 @@ void hal_lld_init(void) { */
void spc_clock_init(void) {
-#if !SPC_NO_INIT
+#if !SPC5_NO_INIT
/* PLL activation.*/
FMPLL.ESYNCR1.B.EMODE = 1;
FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
- FMPLL.ESYNCR1.B.EPREDIV = SPC_CLK_PREDIV;
- FMPLL.ESYNCR1.B.EMFD = SPC_CLK_MFD;
- FMPLL.ESYNCR2.B.ERFD = SPC_CLK_RFD;
+ FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
+ FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
+ FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
while (!FMPLL.SYNSR.B.LOCK)
;
FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
-#endif /* !SPC_NO_INIT */
+#endif /* !SPC5_NO_INIT */
}
/** @} */
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