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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-11 10:27:10 +0000 |
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| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-12-11 10:27:10 +0000 |
| commit | 456ddf784d7bc6fe7c88446faa8bac759078d019 (patch) | |
| tree | 6aec83a3f121bc25cf14c3b7794941048aad00ac /os/hal/platforms/SPC563Mxx/hal_lld.c | |
| parent | beb5f4e03ebaaa196009c41fbb4d9e2c7bc3a14d (diff) | |
| download | ChibiOS-456ddf784d7bc6fe7c88446faa8bac759078d019.tar.gz ChibiOS-456ddf784d7bc6fe7c88446faa8bac759078d019.tar.bz2 ChibiOS-456ddf784d7bc6fe7c88446faa8bac759078d019.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4900 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC563Mxx/hal_lld.c')
| -rw-r--r-- | os/hal/platforms/SPC563Mxx/hal_lld.c | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c new file mode 100644 index 000000000..89a5d9e45 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/hal_lld.c @@ -0,0 +1,127 @@ +/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file SPC563Mxx/hal_lld.c
+ * @brief SPC563Mxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ extern void _vectors(void);
+ uint32_t n;
+
+ /* Enables the branch prediction, clears and enables the BTB into the
+ BUCSR special register (1013).*/
+ asm volatile ("li %%r3, 0x0201 \t\n"
+ "mtspr 1013, %%r3": : : "r3");
+
+ /* FLASH wait states and prefetching setup.*/
+ CFLASH0.BIUCR.R = SPC_FLASH_BIUCR | SPC_FLASH_WS;
+ CFLASH0.BIUCR2.R = 0;
+ CFLASH0.PFCR3.R = 0;
+
+ /* Optimal crossbar settings. The DMA priority is placed above the CPU
+ priority in order to not starve I/O activities while the CPU is
+ executing tight loops (FLASH and SRAM slave ports only).
+ The SRAM is parked on the load/store port, for some unknown reason it
+ is defaulted on the instructions port and this kills performance.*/
+ XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
+ XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
+ eDMA (1): 0 (highest)
+ Core Instructions (0): 1
+ Undocumented (2): 2
+ Core Data (4): 3 */
+ XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
+ eDMA (1): 0 (highest)
+ Core Instructions (0): 1
+ Undocumented (2): 2
+ Core Data (4): 3 */
+
+ /* Downcounter timer initialized for system tick use, TB enabled for debug
+ and measurements.*/
+ n = SPC_SYSCLK / CH_FREQUENCY;
+ asm volatile ("li %%r3, 0 \t\n"
+ "mtspr 284, %%r3 \t\n" /* Clear TBL register. */
+ "mtspr 285, %%r3 \t\n" /* Clear TBU register. */
+ "mtspr 22, %[n] \t\n" /* Init. DEC register. */
+ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
+ "li %%r3, 0x4000 \t\n" /* TBEN bit. */
+ "mtspr 1008, %%r3 \t\n" /* HID0 register. */
+ "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
+ "mtspr 340, %%r3" /* TCR register. */
+ : : [n] "r" (n) : "r3");
+
+ /* INTC initialization, software vector mode, 4 bytes vectors, starting
+ at priority 0.*/
+ INTC.MCR.R = 0;
+ INTC.CPR.R = 0;
+ INTC.IACKR.R = (uint32_t)_vectors;
+}
+
+/**
+ * @brief SPC563 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+#if !SPC_NO_INIT
+ /* PLL activation.*/
+ FMPLL.ESYNCR1.B.EMODE = 1;
+ FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
+ FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
+ FMPLL.ESYNCR1.B.EPREDIV = SPC_CLK_PREDIV;
+ FMPLL.ESYNCR1.B.EMFD = SPC_CLK_MFD;
+ FMPLL.ESYNCR2.B.ERFD = SPC_CLK_RFD;
+ while (!FMPLL.SYNSR.B.LOCK)
+ ;
+ FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
+#endif /* !SPC_NO_INIT */
+}
+
+/** @} */
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