diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
| commit | 8ca210a4af9fd039e290cfcc309adde543999c1f (patch) | |
| tree | 1aa594d5e65d5ebabdd358acbe8d3a9ac29f2070 /os/hal/platforms/AT91SAM7 | |
| parent | cb453a3a12464dd71856b1354d083b5b02260870 (diff) | |
| download | ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.gz ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.bz2 ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/AT91SAM7')
33 files changed, 0 insertions, 27025 deletions
diff --git a/os/hal/platforms/AT91SAM7/adc_lld.c b/os/hal/platforms/AT91SAM7/adc_lld.c deleted file mode 100644 index 066e3c542..000000000 --- a/os/hal/platforms/AT91SAM7/adc_lld.c +++ /dev/null @@ -1,382 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- This file has been contributed by:
- Andrew Hannam aka inmarket.
-*/
-/**
- * @file AT91SAM7/adc_lld.c
- * @brief AT91SAM7 ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/**
- * @brief ADC1 Prescaler
- * @detail Prescale = RoundUp(MCK / 2 / ADCClock - 1)
- */
-#if ((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1) > 255
- #define AT91_ADC1_PRESCALE 255
-#else
- #define AT91_ADC1_PRESCALE ((((MCK/2)+(AT91_ADC1_CLOCK-1))/AT91_ADC1_CLOCK)-1)
-#endif
-
-/**
- * @brief ADC1 Startup Time
- * @details Startup = RoundUp(ADCClock / 400,000 - 1)
- * @note Corresponds to a startup delay > 20uS (as required from the datasheet)
- */
-#if (((AT91_ADC1_CLOCK+399999)/400000)-1) > 127
- #define AT91_ADC1_STARTUP 127
-#else
- #define AT91_ADC1_STARTUP (((AT91_ADC1_CLOCK+399999)/400000)-1)
-#endif
-
-#if AT91_ADC1_RESOLUTION == 8
- #define AT91_ADC1_MAINMODE (((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_8_BIT)
-#else
- #define AT91_ADC1_MAINMODE (((AT91_ADC1_SHTM & 0x0F) << 24) | ((AT91_ADC1_STARTUP & 0x7F) << 16) | ((AT91_ADC1_PRESCALE & 0xFF) << 8) | AT91C_ADC_LOWRES_10_BIT)
-#endif
-
-#if AT91_ADC1_TIMER < 0 || AT91_ADC1_TIMER > 2
- #error "Unknown Timer specified for ADC1"
-#endif
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-#if !ADC_USE_ADC1
- #error "You must specify ADC_USE_ADC1 if you have specified HAL_USE_ADC"
-#endif
-
-/** @brief ADC1 driver identifier.*/
-ADCDriver ADCD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#define ADCReg1 ((AT91S_ADC *)AT91C_ADC_CR)
-
-#if AT91_ADC1_MAINMODE == 2
- #define ADCTimer1 ((AT91S_TC *)AT91C_TC2_CCR)
- #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA2
- #define AT91_ADC1_TIMERID AT91C_ID_TC2
-#elif AT91_ADC1_MAINMODE == 1
- #define ADCTimer1 ((AT91S_TC *)AT91C_TC1_CCR)
- #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA1
- #define AT91_ADC1_TIMERID AT91C_ID_TC1
-#else
- #define ADCTimer1 ((AT91S_TC *)AT91C_TC0_CCR)
- #define AT91_ADC1_TIMERMODE AT91C_ADC_TRGSEL_TIOA0
- #define AT91_ADC1_TIMERID AT91C_ID_TC0
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-#define adc_sleep() ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_MODE | AT91C_ADC_TRGEN_DIS)
-#define adc_wake() ADCReg1->ADC_MR = (AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS)
-#define adc_disable() { \
- ADCReg1->ADC_IDR = 0xFFFFFFFF; \
- ADCReg1->ADC_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; \
- adc_wake(); \
- ADCReg1->ADC_CHDR = 0xFF; \
- }
-#define adc_clrint() { \
- uint32_t isr, dummy; \
- \
- isr = ADCReg1->ADC_SR; \
- if ((isr & AT91C_ADC_DRDY)) dummy = ADCReg1->ADC_LCDR; \
- if ((isr & AT91C_ADC_EOC0)) dummy = ADCReg1->ADC_CDR0; \
- if ((isr & AT91C_ADC_EOC1)) dummy = ADCReg1->ADC_CDR1; \
- if ((isr & AT91C_ADC_EOC2)) dummy = ADCReg1->ADC_CDR2; \
- if ((isr & AT91C_ADC_EOC3)) dummy = ADCReg1->ADC_CDR3; \
- if ((isr & AT91C_ADC_EOC4)) dummy = ADCReg1->ADC_CDR4; \
- if ((isr & AT91C_ADC_EOC5)) dummy = ADCReg1->ADC_CDR5; \
- if ((isr & AT91C_ADC_EOC6)) dummy = ADCReg1->ADC_CDR6; \
- if ((isr & AT91C_ADC_EOC7)) dummy = ADCReg1->ADC_CDR7; \
- }
-#define adc_stop() { \
- adc_disable(); \
- adc_clrint(); \
- }
-
-/**
- * We must keep stack usage to a minimum - the default AT91SAM7 isr stack size is very small.
- * We sacrifice some speed and code size in order to achieve this by accessing the structure
- * and registers directly rather than through the passed in pointers. This works because the
- * AT91SAM7 supports only a single ADC device (although with 8 channels).
- */
-static void handleint(void) {
- uint32_t isr;
-
- isr = ADCReg1->ADC_SR;
-
- if (ADCD1.grpp) {
-
- /* ADC overflow condition, this could happen only if the DMA is unable to read data fast enough.*/
- if ((isr & AT91C_ADC_GOVRE)) {
- _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
-
- /* Transfer complete processing.*/
- } else if ((isr & AT91C_ADC_RXBUFF)) {
- if (ADCD1.grpp->circular) {
- /* setup the DMA again */
- ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples;
- if (ADCD1.depth <= 1) {
- ADCReg1->ADC_RCR = ADCD1.grpp->num_channels;
- ADCReg1->ADC_RNPR = 0;
- ADCReg1->ADC_RNCR = 0;
- } else {
- ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels;
- ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels));
- ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels;
- }
- ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN; // DMA enabled
- }
- _adc_isr_full_code(&ADCD1);
-
- /* Half transfer processing.*/
- } else if ((isr & AT91C_ADC_ENDRX)) {
- _adc_isr_half_code(&ADCD1);
- }
-
- } else {
- /* Spurious interrupt - Make sure it doesn't happen again */
- adc_disable();
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief ADC interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(ADC_IRQHandler) {
- CH_IRQ_PROLOGUE();
-
- handleint();
-
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
- /* Turn on ADC in the power management controller */
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_ADC);
-
- /* Driver object initialization.*/
- adcObjectInit(&ADCD1);
-
- ADCReg1->ADC_CR = 0; // 0 or AT91C_ADC_SWRST if you want to do a ADC reset
- adc_stop();
- adc_sleep();
-
- /* Setup interrupt handler */
- AIC_ConfigureIT(AT91C_ID_ADC,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91_ADC_IRQ_PRIORITY,
- ADC_IRQHandler);
- AIC_EnableIT(AT91C_ID_ADC);
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- /* If in stopped state then wake up the ADC */
- if (adcp->state == ADC_STOP) {
-
- /* Take it out of sleep mode */
- /* We could stay in sleep mode provided total conversion rate < 44kHz but we can't guarantee that here */
- adc_wake();
-
- /* TODO: We really should perform a conversion here just to ensure that we are out of sleep mode */
- }
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
- if (adcp->state != ADC_READY) {
- adc_stop();
- adc_sleep();
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t i;
-
- /* Make sure everything is stopped first */
- adc_stop();
-
- /* Safety check the trigger value */
- switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) {
- case ADC_TRIGGER_TIMER:
- case ADC_TRIGGER_EXTERNAL:
- break;
- default:
- ((ADCConversionGroup *)ADCD1.grpp)->trigger = ADC_TRIGGER_SOFTWARE;
- ADCD1.depth = 1;
- ((ADCConversionGroup *)ADCD1.grpp)->circular = 0;
- break;
- }
-
- /* Count the real number of activated channels in case the user got it wrong */
- ((ADCConversionGroup *)ADCD1.grpp)->num_channels = 0;
- for(i=1; i < 0x100; i <<= 1) {
- if ((ADCD1.grpp->channelselects & i))
- ((ADCConversionGroup *)ADCD1.grpp)->num_channels++;
- }
-
- /* Set the channels */
- ADCReg1->ADC_CHER = ADCD1.grpp->channelselects;
-
- /* Set up the DMA */
- ADCReg1->ADC_RPR = (uint32_t)ADCD1.samples;
- if (adcp->depth <= 1) {
- ADCReg1->ADC_RCR = ADCD1.grpp->num_channels;
- ADCReg1->ADC_RNPR = 0;
- ADCReg1->ADC_RNCR = 0;
- } else {
- ADCReg1->ADC_RCR = ADCD1.depth/2 * ADCD1.grpp->num_channels;
- ADCReg1->ADC_RNPR = (uint32_t)(ADCD1.samples + (ADCD1.depth/2 * ADCD1.grpp->num_channels));
- ADCReg1->ADC_RNCR = (ADCD1.depth - ADCD1.depth/2) * ADCD1.grpp->num_channels;
- }
- ADCReg1->ADC_PTCR = AT91C_PDC_RXTEN;
-
- /* Set up interrupts */
- ADCReg1->ADC_IER = AT91C_ADC_GOVRE | AT91C_ADC_ENDRX | AT91C_ADC_RXBUFF;
-
- /* Set the trigger */
- switch(ADCD1.grpp->trigger & ~ADC_TRIGGER_SOFTWARE) {
- case ADC_TRIGGER_TIMER:
- // Set up the timer if ADCD1.grpp->frequency != 0
- if (ADCD1.grpp->frequency) {
- /* Turn on Timer in the power management controller */
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91_ADC1_TIMERID);
-
- /* Disable the clock and the interrupts */
- ADCTimer1->TC_CCR = AT91C_TC_CLKDIS;
- ADCTimer1->TC_IDR = 0xFFFFFFFF;
-
- /* Set the Mode of the Timer Counter and calculate the period */
- i = (MCK/2)/ADCD1.grpp->frequency;
- if (i < (0x10000<<0)) {
- ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
- AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV1_CLOCK);
- } else if (i < (0x10000<<2)) {
- i >>= 2;
- ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
- AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV2_CLOCK);
- } else if (i < (0x10000<<4)) {
- i >>= 4;
- ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
- AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV3_CLOCK);
- } else if (i < (0x10000<<6)) {
- i >>= 6;
- ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
- AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV4_CLOCK);
- } else {
- i >>= 9;
- ADCTimer1->TC_CMR = (AT91C_TC_ASWTRG_CLEAR | AT91C_TC_ACPC_CLEAR | AT91C_TC_ACPA_SET | AT91C_TC_LDRA_RISING |
- AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_CLKS_TIMER_DIV5_CLOCK);
- }
-
- /* RC is the period, RC-RA is the pulse width (in this case = 1) */
- ADCTimer1->TC_RC = i;
- ADCTimer1->TC_RA = i - 1;
-
- /* Start the timer counter */
- ADCTimer1->TC_CCR = (AT91C_TC_CLKEN |AT91C_TC_SWTRG);
- }
-
- ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91_ADC1_TIMERMODE;
- break;
-
- case ADC_TRIGGER_EXTERNAL:
- /* Make sure the ADTRG pin is set as an input - assume pull-ups etc have already been set */
- #if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
- AT91C_BASE_PIOA->PIO_ODR = AT91C_PA8_ADTRG;
- #elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || (SAM7_PLATFORM == SAM7X512)
- AT91C_BASE_PIOB->PIO_ODR = AT91C_PB18_ADTRG;
- #endif
- ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_EN | AT91C_ADC_TRGSEL_EXT;
- break;
-
- default:
- ADCReg1->ADC_MR = AT91_ADC1_MAINMODE | AT91C_ADC_SLEEP_NORMAL_MODE | AT91C_ADC_TRGEN_DIS;
- break;
- }
-
- /* Manually start a conversion if we need to */
- if (ADCD1.grpp->trigger & ADC_TRIGGER_SOFTWARE)
- ADCReg1->ADC_CR = AT91C_ADC_START;
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
- (void) adcp;
- adc_stop();
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/adc_lld.h b/os/hal/platforms/AT91SAM7/adc_lld.h deleted file mode 100644 index fcdd9ecf6..000000000 --- a/os/hal/platforms/AT91SAM7/adc_lld.h +++ /dev/null @@ -1,303 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- This file has been contributed by:
- Andrew Hannam aka inmarket.
-*/
-/**
- * @file AT91SAM7/adc_lld.h
- * @brief AT91SAM7 ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Trigger Sources
- * @{
- */
-#define ADC_TRIGGER_SOFTWARE 0x8000 /**< @brief Software Triggering - Can be combined with another value */
-#define ADC_TRIGGER_TIMER 0x0001 /**< @brief TIO Timer Counter Channel */
-#define ADC_TRIGGER_EXTERNAL 0x0002 /**< @brief External Trigger */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define ADC_USE_ADC1 TRUE
-#endif
-
-/**
- * @brief ADC1 Timer to use when a periodic conversion is requested.
- * @details Should be set to 0..2
- * @note The default is 0
- */
-#if !defined(AT91_ADC1_TIMER) || defined(__DOXYGEN__)
-#define AT91_ADC1_TIMER 0
-#endif
-
-/**
- * @brief ADC1 Resolution.
- * @details Either 8 or 10 bits
- * @note The default is 10 bits.
- */
-#if !defined(AT91_ADC1_RESOLUTION) || defined(__DOXYGEN__)
-#define AT91_ADC1_RESOLUTION 10
-#endif
-
-/**
- * @brief ADC1 Clock
- * @details Maximum is 5MHz for 10bit or 8MHz for 8bit
- * @note The default is calculated from AT91_ADC1_RESOLUTION to give the fastest possible ADCClock
- */
-#if !defined(AT91_ADC1_CLOCK) || defined(__DOXYGEN__)
- #if AT91_ADC1_RESOLUTION == 8
- #define AT91_ADC1_CLOCK 8000000
- #else
- #define AT91_ADC1_CLOCK 5000000
- #endif
-#endif
-
-/**
- * @brief ADC1 Sample and Hold Time
- * @details SHTM = RoundUp(ADCClock * SampleHoldTime). Range = RoundUp(ADCClock / 1,666,666) to 15
- * @note Default corresponds to the minimum sample and hold time (600nS from the datasheet)
- * @note Increasing the Sample Hold Time increases the ADC input impedance
- */
-#if !defined(AT91_ADC1_SHTM) || defined(__DOXYGEN__)
- #define AT91_ADC1_SHTM 0
-#endif
-#if AT91_ADC1_SHTM < ((AT91_ADC1_CLOCK+1666665)/1666666)
- #undef AT91_ADC1_SHTM
- #define AT91_ADC1_SHTM ((AT91_ADC1_CLOCK+1666665)/1666666)
-#endif
-#if AT91_ADC1_SHTM > 15
- #undef AT91_ADC1_SHTM
- #define AT91_ADC1_SHTM 15
-#endif
-
-/**
- * @brief ADC interrupt priority level setting.
- */
-#if !defined(AT91_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define AT91_ADC_IRQ_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !defined(AT91_DMA_REQUIRED)
-#define AT91_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ADC sample data type.
- */
-#if AT91_ADC1_RESOLUTION == AT91C_ADC_LOWRES_8_BIT
- typedef uint8_t adcsample_t;
-#else
- typedef uint16_t adcsample_t;
-#endif
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief Possible ADC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- ADC_ERR_OVERFLOW = 0, /**< ADC overflow condition. Something is not working fast enough. */
-} adcerror_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note The use of this configuration structure requires knowledge of
- * STM32 ADC cell registers interface, please refer to the STM32
- * reference manual for details.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool_t circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief Select the ADC Channels to read.
- * @details The number of bits at logic level one in this register must
- * be equal to the number in the @p num_channels field.
- */
- uint16_t channelselects;
- /**
- * @brief Select how to trigger the conversion.
- */
- uint16_t trigger;
- /**
- * @brief When in ADC_TRIGGER_TIMER trigger mode - what frequency?
- */
- uint32_t frequency;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- Thread *thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h deleted file mode 100644 index 5d609f1cf..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7A3.h +++ /dev/null @@ -1,3352 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7A3.h
-// Object : AT91SAM7A3 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:10:41)
-//
-// CVS Reference : /AT91SAM7A3.pl/1.30/Wed Aug 30 14:08:29 2006//
-// CVS Reference : /SYS_SAM7A3.pl/1.7/Thu Feb 3 17:24:14 2005//
-// CVS Reference : /MC_SAM7A3.pl/1.3/Fri Sep 23 12:47:15 2005//
-// CVS Reference : /PMC_SAM7A3.pl/1.2/Tue Feb 8 14:00:18 2005//
-// CVS Reference : /RSTC_SAM7A3.pl/1.2/Wed Jul 13 15:25:16 2005//
-// CVS Reference : /SHDWC_SAM7A3.pl/1.1/Thu Feb 3 17:23:24 2005//
-// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference : /PWM_SAM7A3.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// CVS Reference : /AES_6149A.pl/1.12/Wed Nov 2 14:17:53 2005//
-// CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7A3_H
-#define AT91SAM7A3_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[1]; //
- AT91_REG SHDWC_SHCR; // Shut Down Control Register
- AT91_REG SHDWC_SHMR; // Shut Down Mode Register
- AT91_REG SHDWC_SHSR; // Shut Down Status Register
- AT91_REG Reserved27[1]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved28[1]; //
- AT91_REG SYS_GPBR0; // General Purpose Register 0
- AT91_REG SYS_GPBR1; // General Purpose Register 1
- AT91_REG Reserved29[106]; //
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved30[1]; //
- AT91_REG MC_PUIA[16]; // MC Protection Unit Area
- AT91_REG MC_PUP; // MC Protection Unit Peripherals
- AT91_REG MC_PUER; // MC Protection Unit Enable Register
- AT91_REG Reserved31[2]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-#define SYS_GPBR0 (AT91_CAST(AT91_REG *) 0x00000D50) // (SYS_GPBR0) General Purpose Register 0
-#define SYS_GPBR1 (AT91_CAST(AT91_REG *) 0x00000D54) // (SYS_GPBR1) General Purpose Register 1
-
-#endif
-// -------- GPBR : (SYS Offset: 0xd50) GPBR General Purpose Register --------
-// -------- GPBR : (SYS Offset: 0xd54) GPBR General Purpose Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SHDWC {
- AT91_REG SHDWC_SHCR; // Shut Down Control Register
- AT91_REG SHDWC_SHMR; // Shut Down Mode Register
- AT91_REG SHDWC_SHSR; // Shut Down Status Register
-} AT91S_SHDWC, *AT91PS_SHDWC;
-#else
-#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
-#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
-#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
-
-#endif
-// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
-#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
-#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
-// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
-#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
-#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
-#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
-#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
-#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
-#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
-#define AT91C_SHDWC_WKMODE1 (0x3 << 8) // (SHDWC) Wake Up 1 Mode Selection
-#define AT91C_SHDWC_WKMODE1_NONE (0x0 << 8) // (SHDWC) None. No detection is performed on the wake up input.
-#define AT91C_SHDWC_WKMODE1_HIGH (0x1 << 8) // (SHDWC) High Level.
-#define AT91C_SHDWC_WKMODE1_LOW (0x2 << 8) // (SHDWC) Low Level.
-#define AT91C_SHDWC_WKMODE1_ANYLEVEL (0x3 << 8) // (SHDWC) Any level change.
-#define AT91C_SHDWC_CPTWK1 (0xF << 12) // (SHDWC) Counter On Wake Up 1
-#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
-// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
-#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
-#define AT91C_SHDWC_WAKEUP1 (0x1 << 1) // (SHDWC) Wake Up 1 Status
-#define AT91C_SHDWC_FWKUP (0x1 << 2) // (SHDWC) Force Wake Up Status
-#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG MC_PUIA[16]; // MC Protection Unit Area
- AT91_REG MC_PUP; // MC Protection Unit Peripherals
- AT91_REG MC_PUER; // MC Protection Unit Enable Register
- AT91_REG Reserved1[2]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection
-#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access
-#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size
-#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte
-#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte
-#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte
-#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte
-#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte
-#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte
-#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte
-#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte
-#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte
-#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte
-#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte
-#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte
-#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte
-#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte
-#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte
-#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte
-#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_EOP (0x1 << 0) // (MC) End Of Programming Flag
-#define AT91C_MC_EOL (0x1 << 1) // (MC) End Of Lock/Unlock Flag
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error Flag
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error Flag
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Status Register --------
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
-#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Multimedia Card Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MCI {
- AT91_REG MCI_CR; // MCI Control Register
- AT91_REG MCI_MR; // MCI Mode Register
- AT91_REG MCI_DTOR; // MCI Data Timeout Register
- AT91_REG MCI_SDCR; // MCI SD Card Register
- AT91_REG MCI_ARGR; // MCI Argument Register
- AT91_REG MCI_CMDR; // MCI Command Register
- AT91_REG Reserved0[2]; //
- AT91_REG MCI_RSPR[4]; // MCI Response Register
- AT91_REG MCI_RDR; // MCI Receive Data Register
- AT91_REG MCI_TDR; // MCI Transmit Data Register
- AT91_REG Reserved1[2]; //
- AT91_REG MCI_SR; // MCI Status Register
- AT91_REG MCI_IER; // MCI Interrupt Enable Register
- AT91_REG MCI_IDR; // MCI Interrupt Disable Register
- AT91_REG MCI_IMR; // MCI Interrupt Mask Register
- AT91_REG Reserved2[44]; //
- AT91_REG MCI_RPR; // Receive Pointer Register
- AT91_REG MCI_RCR; // Receive Counter Register
- AT91_REG MCI_TPR; // Transmit Pointer Register
- AT91_REG MCI_TCR; // Transmit Counter Register
- AT91_REG MCI_RNPR; // Receive Next Pointer Register
- AT91_REG MCI_RNCR; // Receive Next Counter Register
- AT91_REG MCI_TNPR; // Transmit Next Pointer Register
- AT91_REG MCI_TNCR; // Transmit Next Counter Register
- AT91_REG MCI_PTCR; // PDC Transfer Control Register
- AT91_REG MCI_PTSR; // PDC Transfer Status Register
-} AT91S_MCI, *AT91PS_MCI;
-#else
-#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
-#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
-#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
-#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register
-#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
-#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
-#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
-#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
-#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
-#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
-#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
-#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
-#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
-
-#endif
-// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
-#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
-#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
-#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
-#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
-#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
-// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
-#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
-#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
-#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
-#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
-#define AT91C_MCI_BLKLEN (0xFFF << 18) // (MCI) Data Block Length
-// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
-#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
-#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
-#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
-#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
-#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
-#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
-#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
-#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
-#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
-#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
-// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
-#define AT91C_MCI_SCDSEL (0xF << 0) // (MCI) SD Card Selector
-#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width
-// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
-#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
-#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
-#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
-#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
-#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
-#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
-#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
-#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
-#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
-#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
-#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
-#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
-#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
-#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
-#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
-#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
-#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
-#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
-#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type
-#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type
-#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type
-#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type
-// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
-#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
-#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
-#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
-#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
-#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
-#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
-#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
-#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
-#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
-#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
-#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
-#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
-#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
-#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
-#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
-#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
-#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
-#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
-#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
-// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
-// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
-// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[8]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7A3
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-#define AT91C_SYS_GPBR1 (AT91_CAST(AT91_REG *) 0xFFFFFD54) // (SYS) General Purpose Register 1
-#define AT91C_SYS_GPBR0 (AT91_CAST(AT91_REG *) 0xFFFFFD50) // (SYS) General Purpose Register 0
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for SHDWC peripheral ==========
-#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
-#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
-#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for CAN0_MB0 peripheral ==========
-#define AT91C_CAN0_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFF80218) // (CAN0_MB0) MailBox Data High Register
-#define AT91C_CAN0_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFF80214) // (CAN0_MB0) MailBox Data Low Register
-#define AT91C_CAN0_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFF80204) // (CAN0_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFF8021C) // (CAN0_MB0) MailBox Control Register
-#define AT91C_CAN0_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFF80200) // (CAN0_MB0) MailBox Mode Register
-#define AT91C_CAN0_MB0_MID (AT91_CAST(AT91_REG *) 0xFFF80208) // (CAN0_MB0) MailBox ID Register
-#define AT91C_CAN0_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFF8020C) // (CAN0_MB0) MailBox Family ID Register
-#define AT91C_CAN0_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFF80210) // (CAN0_MB0) MailBox Status Register
-// ========== Register definition for CAN0_MB1 peripheral ==========
-#define AT91C_CAN0_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFF80230) // (CAN0_MB1) MailBox Status Register
-#define AT91C_CAN0_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFF80238) // (CAN0_MB1) MailBox Data High Register
-#define AT91C_CAN0_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFF8022C) // (CAN0_MB1) MailBox Family ID Register
-#define AT91C_CAN0_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFF80224) // (CAN0_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFF80234) // (CAN0_MB1) MailBox Data Low Register
-#define AT91C_CAN0_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFF80220) // (CAN0_MB1) MailBox Mode Register
-#define AT91C_CAN0_MB1_MID (AT91_CAST(AT91_REG *) 0xFFF80228) // (CAN0_MB1) MailBox ID Register
-#define AT91C_CAN0_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFF8023C) // (CAN0_MB1) MailBox Control Register
-// ========== Register definition for CAN0_MB2 peripheral ==========
-#define AT91C_CAN0_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFF8025C) // (CAN0_MB2) MailBox Control Register
-#define AT91C_CAN0_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFF8024C) // (CAN0_MB2) MailBox Family ID Register
-#define AT91C_CAN0_MB2_MID (AT91_CAST(AT91_REG *) 0xFFF80248) // (CAN0_MB2) MailBox ID Register
-#define AT91C_CAN0_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFF80240) // (CAN0_MB2) MailBox Mode Register
-#define AT91C_CAN0_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFF80244) // (CAN0_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFF80258) // (CAN0_MB2) MailBox Data High Register
-#define AT91C_CAN0_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFF80250) // (CAN0_MB2) MailBox Status Register
-#define AT91C_CAN0_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFF80254) // (CAN0_MB2) MailBox Data Low Register
-// ========== Register definition for CAN0_MB3 peripheral ==========
-#define AT91C_CAN0_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFF80260) // (CAN0_MB3) MailBox Mode Register
-#define AT91C_CAN0_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFF8027C) // (CAN0_MB3) MailBox Control Register
-#define AT91C_CAN0_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFF80278) // (CAN0_MB3) MailBox Data High Register
-#define AT91C_CAN0_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFF80274) // (CAN0_MB3) MailBox Data Low Register
-#define AT91C_CAN0_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFF80264) // (CAN0_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFF80270) // (CAN0_MB3) MailBox Status Register
-#define AT91C_CAN0_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFF8026C) // (CAN0_MB3) MailBox Family ID Register
-#define AT91C_CAN0_MB3_MID (AT91_CAST(AT91_REG *) 0xFFF80268) // (CAN0_MB3) MailBox ID Register
-// ========== Register definition for CAN0_MB4 peripheral ==========
-#define AT91C_CAN0_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFF8028C) // (CAN0_MB4) MailBox Family ID Register
-#define AT91C_CAN0_MB4_MID (AT91_CAST(AT91_REG *) 0xFFF80288) // (CAN0_MB4) MailBox ID Register
-#define AT91C_CAN0_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFF80298) // (CAN0_MB4) MailBox Data High Register
-#define AT91C_CAN0_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFF80294) // (CAN0_MB4) MailBox Data Low Register
-#define AT91C_CAN0_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFF80284) // (CAN0_MB4) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFF8029C) // (CAN0_MB4) MailBox Control Register
-#define AT91C_CAN0_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFF80290) // (CAN0_MB4) MailBox Status Register
-#define AT91C_CAN0_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFF80280) // (CAN0_MB4) MailBox Mode Register
-// ========== Register definition for CAN0_MB5 peripheral ==========
-#define AT91C_CAN0_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFF802B0) // (CAN0_MB5) MailBox Status Register
-#define AT91C_CAN0_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFF802AC) // (CAN0_MB5) MailBox Family ID Register
-#define AT91C_CAN0_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFF802A4) // (CAN0_MB5) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFF802B4) // (CAN0_MB5) MailBox Data Low Register
-#define AT91C_CAN0_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFF802B8) // (CAN0_MB5) MailBox Data High Register
-#define AT91C_CAN0_MB5_MID (AT91_CAST(AT91_REG *) 0xFFF802A8) // (CAN0_MB5) MailBox ID Register
-#define AT91C_CAN0_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFF802A0) // (CAN0_MB5) MailBox Mode Register
-#define AT91C_CAN0_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFF802BC) // (CAN0_MB5) MailBox Control Register
-// ========== Register definition for CAN0_MB6 peripheral ==========
-#define AT91C_CAN0_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFF802C4) // (CAN0_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB6_MID (AT91_CAST(AT91_REG *) 0xFFF802C8) // (CAN0_MB6) MailBox ID Register
-#define AT91C_CAN0_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFF802D4) // (CAN0_MB6) MailBox Data Low Register
-#define AT91C_CAN0_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFF802D8) // (CAN0_MB6) MailBox Data High Register
-#define AT91C_CAN0_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFF802DC) // (CAN0_MB6) MailBox Control Register
-#define AT91C_CAN0_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFF802C0) // (CAN0_MB6) MailBox Mode Register
-#define AT91C_CAN0_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFF802CC) // (CAN0_MB6) MailBox Family ID Register
-#define AT91C_CAN0_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFF802D0) // (CAN0_MB6) MailBox Status Register
-// ========== Register definition for CAN0_MB7 peripheral ==========
-#define AT91C_CAN0_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFF802F0) // (CAN0_MB7) MailBox Status Register
-#define AT91C_CAN0_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFF802E0) // (CAN0_MB7) MailBox Mode Register
-#define AT91C_CAN0_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFF802FC) // (CAN0_MB7) MailBox Control Register
-#define AT91C_CAN0_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFF802F4) // (CAN0_MB7) MailBox Data Low Register
-#define AT91C_CAN0_MB7_MID (AT91_CAST(AT91_REG *) 0xFFF802E8) // (CAN0_MB7) MailBox ID Register
-#define AT91C_CAN0_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFF802F8) // (CAN0_MB7) MailBox Data High Register
-#define AT91C_CAN0_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFF802EC) // (CAN0_MB7) MailBox Family ID Register
-#define AT91C_CAN0_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFF802E4) // (CAN0_MB7) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB8 peripheral ==========
-#define AT91C_CAN0_MB8_MAM (AT91_CAST(AT91_REG *) 0xFFF80304) // (CAN0_MB8) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB8_MCR (AT91_CAST(AT91_REG *) 0xFFF8031C) // (CAN0_MB8) MailBox Control Register
-#define AT91C_CAN0_MB8_MSR (AT91_CAST(AT91_REG *) 0xFFF80310) // (CAN0_MB8) MailBox Status Register
-#define AT91C_CAN0_MB8_MID (AT91_CAST(AT91_REG *) 0xFFF80308) // (CAN0_MB8) MailBox ID Register
-#define AT91C_CAN0_MB8_MDH (AT91_CAST(AT91_REG *) 0xFFF80318) // (CAN0_MB8) MailBox Data High Register
-#define AT91C_CAN0_MB8_MFID (AT91_CAST(AT91_REG *) 0xFFF8030C) // (CAN0_MB8) MailBox Family ID Register
-#define AT91C_CAN0_MB8_MMR (AT91_CAST(AT91_REG *) 0xFFF80300) // (CAN0_MB8) MailBox Mode Register
-#define AT91C_CAN0_MB8_MDL (AT91_CAST(AT91_REG *) 0xFFF80314) // (CAN0_MB8) MailBox Data Low Register
-// ========== Register definition for CAN0_MB9 peripheral ==========
-#define AT91C_CAN0_MB9_MMR (AT91_CAST(AT91_REG *) 0xFFF80320) // (CAN0_MB9) MailBox Mode Register
-#define AT91C_CAN0_MB9_MDH (AT91_CAST(AT91_REG *) 0xFFF80338) // (CAN0_MB9) MailBox Data High Register
-#define AT91C_CAN0_MB9_MSR (AT91_CAST(AT91_REG *) 0xFFF80330) // (CAN0_MB9) MailBox Status Register
-#define AT91C_CAN0_MB9_MDL (AT91_CAST(AT91_REG *) 0xFFF80334) // (CAN0_MB9) MailBox Data Low Register
-#define AT91C_CAN0_MB9_MID (AT91_CAST(AT91_REG *) 0xFFF80328) // (CAN0_MB9) MailBox ID Register
-#define AT91C_CAN0_MB9_MFID (AT91_CAST(AT91_REG *) 0xFFF8032C) // (CAN0_MB9) MailBox Family ID Register
-#define AT91C_CAN0_MB9_MCR (AT91_CAST(AT91_REG *) 0xFFF8033C) // (CAN0_MB9) MailBox Control Register
-#define AT91C_CAN0_MB9_MAM (AT91_CAST(AT91_REG *) 0xFFF80324) // (CAN0_MB9) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB10 peripheral ==========
-#define AT91C_CAN0_MB10_MCR (AT91_CAST(AT91_REG *) 0xFFF8035C) // (CAN0_MB10) MailBox Control Register
-#define AT91C_CAN0_MB10_MID (AT91_CAST(AT91_REG *) 0xFFF80348) // (CAN0_MB10) MailBox ID Register
-#define AT91C_CAN0_MB10_MAM (AT91_CAST(AT91_REG *) 0xFFF80344) // (CAN0_MB10) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB10_MFID (AT91_CAST(AT91_REG *) 0xFFF8034C) // (CAN0_MB10) MailBox Family ID Register
-#define AT91C_CAN0_MB10_MDL (AT91_CAST(AT91_REG *) 0xFFF80354) // (CAN0_MB10) MailBox Data Low Register
-#define AT91C_CAN0_MB10_MMR (AT91_CAST(AT91_REG *) 0xFFF80340) // (CAN0_MB10) MailBox Mode Register
-#define AT91C_CAN0_MB10_MDH (AT91_CAST(AT91_REG *) 0xFFF80358) // (CAN0_MB10) MailBox Data High Register
-#define AT91C_CAN0_MB10_MSR (AT91_CAST(AT91_REG *) 0xFFF80350) // (CAN0_MB10) MailBox Status Register
-// ========== Register definition for CAN0_MB11 peripheral ==========
-#define AT91C_CAN0_MB11_MCR (AT91_CAST(AT91_REG *) 0xFFF8037C) // (CAN0_MB11) MailBox Control Register
-#define AT91C_CAN0_MB11_MFID (AT91_CAST(AT91_REG *) 0xFFF8036C) // (CAN0_MB11) MailBox Family ID Register
-#define AT91C_CAN0_MB11_MDH (AT91_CAST(AT91_REG *) 0xFFF80378) // (CAN0_MB11) MailBox Data High Register
-#define AT91C_CAN0_MB11_MAM (AT91_CAST(AT91_REG *) 0xFFF80364) // (CAN0_MB11) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB11_MID (AT91_CAST(AT91_REG *) 0xFFF80368) // (CAN0_MB11) MailBox ID Register
-#define AT91C_CAN0_MB11_MMR (AT91_CAST(AT91_REG *) 0xFFF80360) // (CAN0_MB11) MailBox Mode Register
-#define AT91C_CAN0_MB11_MSR (AT91_CAST(AT91_REG *) 0xFFF80370) // (CAN0_MB11) MailBox Status Register
-#define AT91C_CAN0_MB11_MDL (AT91_CAST(AT91_REG *) 0xFFF80374) // (CAN0_MB11) MailBox Data Low Register
-// ========== Register definition for CAN0_MB12 peripheral ==========
-#define AT91C_CAN0_MB12_MCR (AT91_CAST(AT91_REG *) 0xFFF8039C) // (CAN0_MB12) MailBox Control Register
-#define AT91C_CAN0_MB12_MID (AT91_CAST(AT91_REG *) 0xFFF80388) // (CAN0_MB12) MailBox ID Register
-#define AT91C_CAN0_MB12_MDH (AT91_CAST(AT91_REG *) 0xFFF80398) // (CAN0_MB12) MailBox Data High Register
-#define AT91C_CAN0_MB12_MAM (AT91_CAST(AT91_REG *) 0xFFF80384) // (CAN0_MB12) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB12_MFID (AT91_CAST(AT91_REG *) 0xFFF8038C) // (CAN0_MB12) MailBox Family ID Register
-#define AT91C_CAN0_MB12_MDL (AT91_CAST(AT91_REG *) 0xFFF80394) // (CAN0_MB12) MailBox Data Low Register
-#define AT91C_CAN0_MB12_MMR (AT91_CAST(AT91_REG *) 0xFFF80380) // (CAN0_MB12) MailBox Mode Register
-#define AT91C_CAN0_MB12_MSR (AT91_CAST(AT91_REG *) 0xFFF80390) // (CAN0_MB12) MailBox Status Register
-// ========== Register definition for CAN0_MB13 peripheral ==========
-#define AT91C_CAN0_MB13_MCR (AT91_CAST(AT91_REG *) 0xFFF803BC) // (CAN0_MB13) MailBox Control Register
-#define AT91C_CAN0_MB13_MDL (AT91_CAST(AT91_REG *) 0xFFF803B4) // (CAN0_MB13) MailBox Data Low Register
-#define AT91C_CAN0_MB13_MAM (AT91_CAST(AT91_REG *) 0xFFF803A4) // (CAN0_MB13) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB13_MFID (AT91_CAST(AT91_REG *) 0xFFF803AC) // (CAN0_MB13) MailBox Family ID Register
-#define AT91C_CAN0_MB13_MDH (AT91_CAST(AT91_REG *) 0xFFF803B8) // (CAN0_MB13) MailBox Data High Register
-#define AT91C_CAN0_MB13_MID (AT91_CAST(AT91_REG *) 0xFFF803A8) // (CAN0_MB13) MailBox ID Register
-#define AT91C_CAN0_MB13_MSR (AT91_CAST(AT91_REG *) 0xFFF803B0) // (CAN0_MB13) MailBox Status Register
-#define AT91C_CAN0_MB13_MMR (AT91_CAST(AT91_REG *) 0xFFF803A0) // (CAN0_MB13) MailBox Mode Register
-// ========== Register definition for CAN0_MB14 peripheral ==========
-#define AT91C_CAN0_MB14_MSR (AT91_CAST(AT91_REG *) 0xFFF803D0) // (CAN0_MB14) MailBox Status Register
-#define AT91C_CAN0_MB14_MMR (AT91_CAST(AT91_REG *) 0xFFF803C0) // (CAN0_MB14) MailBox Mode Register
-#define AT91C_CAN0_MB14_MDL (AT91_CAST(AT91_REG *) 0xFFF803D4) // (CAN0_MB14) MailBox Data Low Register
-#define AT91C_CAN0_MB14_MDH (AT91_CAST(AT91_REG *) 0xFFF803D8) // (CAN0_MB14) MailBox Data High Register
-#define AT91C_CAN0_MB14_MID (AT91_CAST(AT91_REG *) 0xFFF803C8) // (CAN0_MB14) MailBox ID Register
-#define AT91C_CAN0_MB14_MCR (AT91_CAST(AT91_REG *) 0xFFF803DC) // (CAN0_MB14) MailBox Control Register
-#define AT91C_CAN0_MB14_MFID (AT91_CAST(AT91_REG *) 0xFFF803CC) // (CAN0_MB14) MailBox Family ID Register
-#define AT91C_CAN0_MB14_MAM (AT91_CAST(AT91_REG *) 0xFFF803C4) // (CAN0_MB14) MailBox Acceptance Mask Register
-// ========== Register definition for CAN0_MB15 peripheral ==========
-#define AT91C_CAN0_MB15_MDH (AT91_CAST(AT91_REG *) 0xFFF803F8) // (CAN0_MB15) MailBox Data High Register
-#define AT91C_CAN0_MB15_MMR (AT91_CAST(AT91_REG *) 0xFFF803E0) // (CAN0_MB15) MailBox Mode Register
-#define AT91C_CAN0_MB15_MCR (AT91_CAST(AT91_REG *) 0xFFF803FC) // (CAN0_MB15) MailBox Control Register
-#define AT91C_CAN0_MB15_MAM (AT91_CAST(AT91_REG *) 0xFFF803E4) // (CAN0_MB15) MailBox Acceptance Mask Register
-#define AT91C_CAN0_MB15_MID (AT91_CAST(AT91_REG *) 0xFFF803E8) // (CAN0_MB15) MailBox ID Register
-#define AT91C_CAN0_MB15_MFID (AT91_CAST(AT91_REG *) 0xFFF803EC) // (CAN0_MB15) MailBox Family ID Register
-#define AT91C_CAN0_MB15_MSR (AT91_CAST(AT91_REG *) 0xFFF803F0) // (CAN0_MB15) MailBox Status Register
-#define AT91C_CAN0_MB15_MDL (AT91_CAST(AT91_REG *) 0xFFF803F4) // (CAN0_MB15) MailBox Data Low Register
-// ========== Register definition for CAN0 peripheral ==========
-#define AT91C_CAN0_BR (AT91_CAST(AT91_REG *) 0xFFF80014) // (CAN0) Baudrate Register
-#define AT91C_CAN0_TIMESTP (AT91_CAST(AT91_REG *) 0xFFF8001C) // (CAN0) Time Stamp Register
-#define AT91C_CAN0_IER (AT91_CAST(AT91_REG *) 0xFFF80004) // (CAN0) Interrupt Enable Register
-#define AT91C_CAN0_MR (AT91_CAST(AT91_REG *) 0xFFF80000) // (CAN0) Mode Register
-#define AT91C_CAN0_TCR (AT91_CAST(AT91_REG *) 0xFFF80024) // (CAN0) Transfer Command Register
-#define AT91C_CAN0_ACR (AT91_CAST(AT91_REG *) 0xFFF80028) // (CAN0) Abort Command Register
-#define AT91C_CAN0_IDR (AT91_CAST(AT91_REG *) 0xFFF80008) // (CAN0) Interrupt Disable Register
-#define AT91C_CAN0_IMR (AT91_CAST(AT91_REG *) 0xFFF8000C) // (CAN0) Interrupt Mask Register
-#define AT91C_CAN0_TIM (AT91_CAST(AT91_REG *) 0xFFF80018) // (CAN0) Timer Register
-#define AT91C_CAN0_VR (AT91_CAST(AT91_REG *) 0xFFF800FC) // (CAN0) Version Register
-#define AT91C_CAN0_ECR (AT91_CAST(AT91_REG *) 0xFFF80020) // (CAN0) Error Counter Register
-#define AT91C_CAN0_SR (AT91_CAST(AT91_REG *) 0xFFF80010) // (CAN0) Status Register
-// ========== Register definition for CAN1_MB0 peripheral ==========
-#define AT91C_CAN1_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFF8420C) // (CAN1_MB0) MailBox Family ID Register
-#define AT91C_CAN1_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFF84214) // (CAN1_MB0) MailBox Data Low Register
-#define AT91C_CAN1_MB0_MID (AT91_CAST(AT91_REG *) 0xFFF84208) // (CAN1_MB0) MailBox ID Register
-#define AT91C_CAN1_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFF84200) // (CAN1_MB0) MailBox Mode Register
-#define AT91C_CAN1_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFF84204) // (CAN1_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFF84210) // (CAN1_MB0) MailBox Status Register
-#define AT91C_CAN1_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFF84218) // (CAN1_MB0) MailBox Data High Register
-#define AT91C_CAN1_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFF8421C) // (CAN1_MB0) MailBox Control Register
-// ========== Register definition for CAN1_MB1 peripheral ==========
-#define AT91C_CAN1_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFF8422C) // (CAN1_MB1) MailBox Family ID Register
-#define AT91C_CAN1_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFF84230) // (CAN1_MB1) MailBox Status Register
-#define AT91C_CAN1_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFF84220) // (CAN1_MB1) MailBox Mode Register
-#define AT91C_CAN1_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFF84238) // (CAN1_MB1) MailBox Data High Register
-#define AT91C_CAN1_MB1_MID (AT91_CAST(AT91_REG *) 0xFFF84228) // (CAN1_MB1) MailBox ID Register
-#define AT91C_CAN1_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFF84234) // (CAN1_MB1) MailBox Data Low Register
-#define AT91C_CAN1_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFF8423C) // (CAN1_MB1) MailBox Control Register
-#define AT91C_CAN1_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFF84224) // (CAN1_MB1) MailBox Acceptance Mask Register
-// ========== Register definition for CAN1_MB2 peripheral ==========
-#define AT91C_CAN1_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFF84250) // (CAN1_MB2) MailBox Status Register
-#define AT91C_CAN1_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFF84240) // (CAN1_MB2) MailBox Mode Register
-#define AT91C_CAN1_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFF84244) // (CAN1_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB2_MID (AT91_CAST(AT91_REG *) 0xFFF84248) // (CAN1_MB2) MailBox ID Register
-#define AT91C_CAN1_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFF8424C) // (CAN1_MB2) MailBox Family ID Register
-#define AT91C_CAN1_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFF84254) // (CAN1_MB2) MailBox Data Low Register
-#define AT91C_CAN1_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFF84258) // (CAN1_MB2) MailBox Data High Register
-#define AT91C_CAN1_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFF8425C) // (CAN1_MB2) MailBox Control Register
-// ========== Register definition for CAN1_MB3 peripheral ==========
-#define AT91C_CAN1_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFF8427C) // (CAN1_MB3) MailBox Control Register
-#define AT91C_CAN1_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFF84278) // (CAN1_MB3) MailBox Data High Register
-#define AT91C_CAN1_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFF84264) // (CAN1_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFF84274) // (CAN1_MB3) MailBox Data Low Register
-#define AT91C_CAN1_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFF84260) // (CAN1_MB3) MailBox Mode Register
-#define AT91C_CAN1_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFF84270) // (CAN1_MB3) MailBox Status Register
-#define AT91C_CAN1_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFF8426C) // (CAN1_MB3) MailBox Family ID Register
-#define AT91C_CAN1_MB3_MID (AT91_CAST(AT91_REG *) 0xFFF84268) // (CAN1_MB3) MailBox ID Register
-// ========== Register definition for CAN1_MB4 peripheral ==========
-#define AT91C_CAN1_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFF8429C) // (CAN1_MB4) MailBox Control Register
-#define AT91C_CAN1_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFF84298) // (CAN1_MB4) MailBox Data High Register
-#define AT91C_CAN1_MB4_MID (AT91_CAST(AT91_REG *) 0xFFF84288) // (CAN1_MB4) MailBox ID Register
-#define AT91C_CAN1_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFF84294) // (CAN1_MB4) MailBox Data Low Register
-#define AT91C_CAN1_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFF8428C) // (CAN1_MB4) MailBox Family ID Register
-#define AT91C_CAN1_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFF84284) // (CAN1_MB4) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFF84290) // (CAN1_MB4) MailBox Status Register
-#define AT91C_CAN1_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFF84280) // (CAN1_MB4) MailBox Mode Register
-// ========== Register definition for CAN1_MB5 peripheral ==========
-#define AT91C_CAN1_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFF842BC) // (CAN1_MB5) MailBox Control Register
-#define AT91C_CAN1_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFF842B0) // (CAN1_MB5) MailBox Status Register
-#define AT91C_CAN1_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFF842A0) // (CAN1_MB5) MailBox Mode Register
-#define AT91C_CAN1_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFF842B4) // (CAN1_MB5) MailBox Data Low Register
-#define AT91C_CAN1_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFF842A4) // (CAN1_MB5) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB5_MID (AT91_CAST(AT91_REG *) 0xFFF842A8) // (CAN1_MB5) MailBox ID Register
-#define AT91C_CAN1_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFF842B8) // (CAN1_MB5) MailBox Data High Register
-#define AT91C_CAN1_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFF842AC) // (CAN1_MB5) MailBox Family ID Register
-// ========== Register definition for CAN1_MB6 peripheral ==========
-#define AT91C_CAN1_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFF842D8) // (CAN1_MB6) MailBox Data High Register
-#define AT91C_CAN1_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFF842D4) // (CAN1_MB6) MailBox Data Low Register
-#define AT91C_CAN1_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFF842C4) // (CAN1_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFF842DC) // (CAN1_MB6) MailBox Control Register
-#define AT91C_CAN1_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFF842C0) // (CAN1_MB6) MailBox Mode Register
-#define AT91C_CAN1_MB6_MID (AT91_CAST(AT91_REG *) 0xFFF842C8) // (CAN1_MB6) MailBox ID Register
-#define AT91C_CAN1_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFF842D0) // (CAN1_MB6) MailBox Status Register
-#define AT91C_CAN1_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFF842CC) // (CAN1_MB6) MailBox Family ID Register
-// ========== Register definition for CAN1_MB7 peripheral ==========
-#define AT91C_CAN1_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFF842F8) // (CAN1_MB7) MailBox Data High Register
-#define AT91C_CAN1_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFF842F4) // (CAN1_MB7) MailBox Data Low Register
-#define AT91C_CAN1_MB7_MID (AT91_CAST(AT91_REG *) 0xFFF842E8) // (CAN1_MB7) MailBox ID Register
-#define AT91C_CAN1_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFF842F0) // (CAN1_MB7) MailBox Status Register
-#define AT91C_CAN1_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFF842EC) // (CAN1_MB7) MailBox Family ID Register
-#define AT91C_CAN1_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFF842E4) // (CAN1_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFF842E0) // (CAN1_MB7) MailBox Mode Register
-#define AT91C_CAN1_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFF842FC) // (CAN1_MB7) MailBox Control Register
-// ========== Register definition for CAN1_MB8 peripheral ==========
-#define AT91C_CAN1_MB8_MCR (AT91_CAST(AT91_REG *) 0xFFF8431C) // (CAN1_MB8) MailBox Control Register
-#define AT91C_CAN1_MB8_MFID (AT91_CAST(AT91_REG *) 0xFFF8430C) // (CAN1_MB8) MailBox Family ID Register
-#define AT91C_CAN1_MB8_MSR (AT91_CAST(AT91_REG *) 0xFFF84310) // (CAN1_MB8) MailBox Status Register
-#define AT91C_CAN1_MB8_MAM (AT91_CAST(AT91_REG *) 0xFFF84304) // (CAN1_MB8) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB8_MDL (AT91_CAST(AT91_REG *) 0xFFF84314) // (CAN1_MB8) MailBox Data Low Register
-#define AT91C_CAN1_MB8_MID (AT91_CAST(AT91_REG *) 0xFFF84308) // (CAN1_MB8) MailBox ID Register
-#define AT91C_CAN1_MB8_MDH (AT91_CAST(AT91_REG *) 0xFFF84318) // (CAN1_MB8) MailBox Data High Register
-#define AT91C_CAN1_MB8_MMR (AT91_CAST(AT91_REG *) 0xFFF84300) // (CAN1_MB8) MailBox Mode Register
-// ========== Register definition for CAN1_MB9 peripheral ==========
-#define AT91C_CAN1_MB9_MDH (AT91_CAST(AT91_REG *) 0xFFF84338) // (CAN1_MB9) MailBox Data High Register
-#define AT91C_CAN1_MB9_MDL (AT91_CAST(AT91_REG *) 0xFFF84334) // (CAN1_MB9) MailBox Data Low Register
-#define AT91C_CAN1_MB9_MFID (AT91_CAST(AT91_REG *) 0xFFF8432C) // (CAN1_MB9) MailBox Family ID Register
-#define AT91C_CAN1_MB9_MMR (AT91_CAST(AT91_REG *) 0xFFF84320) // (CAN1_MB9) MailBox Mode Register
-#define AT91C_CAN1_MB9_MAM (AT91_CAST(AT91_REG *) 0xFFF84324) // (CAN1_MB9) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB9_MID (AT91_CAST(AT91_REG *) 0xFFF84328) // (CAN1_MB9) MailBox ID Register
-#define AT91C_CAN1_MB9_MCR (AT91_CAST(AT91_REG *) 0xFFF8433C) // (CAN1_MB9) MailBox Control Register
-#define AT91C_CAN1_MB9_MSR (AT91_CAST(AT91_REG *) 0xFFF84330) // (CAN1_MB9) MailBox Status Register
-// ========== Register definition for CAN1_MB10 peripheral ==========
-#define AT91C_CAN1_MB10_MFID (AT91_CAST(AT91_REG *) 0xFFF8434C) // (CAN1_MB10) MailBox Family ID Register
-#define AT91C_CAN1_MB10_MSR (AT91_CAST(AT91_REG *) 0xFFF84350) // (CAN1_MB10) MailBox Status Register
-#define AT91C_CAN1_MB10_MDL (AT91_CAST(AT91_REG *) 0xFFF84354) // (CAN1_MB10) MailBox Data Low Register
-#define AT91C_CAN1_MB10_MMR (AT91_CAST(AT91_REG *) 0xFFF84340) // (CAN1_MB10) MailBox Mode Register
-#define AT91C_CAN1_MB10_MCR (AT91_CAST(AT91_REG *) 0xFFF8435C) // (CAN1_MB10) MailBox Control Register
-#define AT91C_CAN1_MB10_MAM (AT91_CAST(AT91_REG *) 0xFFF84344) // (CAN1_MB10) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB10_MID (AT91_CAST(AT91_REG *) 0xFFF84348) // (CAN1_MB10) MailBox ID Register
-#define AT91C_CAN1_MB10_MDH (AT91_CAST(AT91_REG *) 0xFFF84358) // (CAN1_MB10) MailBox Data High Register
-// ========== Register definition for CAN1_MB11 peripheral ==========
-#define AT91C_CAN1_MB11_MMR (AT91_CAST(AT91_REG *) 0xFFF84360) // (CAN1_MB11) MailBox Mode Register
-#define AT91C_CAN1_MB11_MDL (AT91_CAST(AT91_REG *) 0xFFF84374) // (CAN1_MB11) MailBox Data Low Register
-#define AT91C_CAN1_MB11_MAM (AT91_CAST(AT91_REG *) 0xFFF84364) // (CAN1_MB11) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB11_MID (AT91_CAST(AT91_REG *) 0xFFF84368) // (CAN1_MB11) MailBox ID Register
-#define AT91C_CAN1_MB11_MCR (AT91_CAST(AT91_REG *) 0xFFF8437C) // (CAN1_MB11) MailBox Control Register
-#define AT91C_CAN1_MB11_MDH (AT91_CAST(AT91_REG *) 0xFFF84378) // (CAN1_MB11) MailBox Data High Register
-#define AT91C_CAN1_MB11_MSR (AT91_CAST(AT91_REG *) 0xFFF84370) // (CAN1_MB11) MailBox Status Register
-#define AT91C_CAN1_MB11_MFID (AT91_CAST(AT91_REG *) 0xFFF8436C) // (CAN1_MB11) MailBox Family ID Register
-// ========== Register definition for CAN1_MB12 peripheral ==========
-#define AT91C_CAN1_MB12_MFID (AT91_CAST(AT91_REG *) 0xFFF8438C) // (CAN1_MB12) MailBox Family ID Register
-#define AT91C_CAN1_MB12_MAM (AT91_CAST(AT91_REG *) 0xFFF84384) // (CAN1_MB12) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB12_MDH (AT91_CAST(AT91_REG *) 0xFFF84398) // (CAN1_MB12) MailBox Data High Register
-#define AT91C_CAN1_MB12_MMR (AT91_CAST(AT91_REG *) 0xFFF84380) // (CAN1_MB12) MailBox Mode Register
-#define AT91C_CAN1_MB12_MID (AT91_CAST(AT91_REG *) 0xFFF84388) // (CAN1_MB12) MailBox ID Register
-#define AT91C_CAN1_MB12_MCR (AT91_CAST(AT91_REG *) 0xFFF8439C) // (CAN1_MB12) MailBox Control Register
-#define AT91C_CAN1_MB12_MDL (AT91_CAST(AT91_REG *) 0xFFF84394) // (CAN1_MB12) MailBox Data Low Register
-#define AT91C_CAN1_MB12_MSR (AT91_CAST(AT91_REG *) 0xFFF84390) // (CAN1_MB12) MailBox Status Register
-// ========== Register definition for CAN1_MB13 peripheral ==========
-#define AT91C_CAN1_MB13_MDL (AT91_CAST(AT91_REG *) 0xFFF843B4) // (CAN1_MB13) MailBox Data Low Register
-#define AT91C_CAN1_MB13_MSR (AT91_CAST(AT91_REG *) 0xFFF843B0) // (CAN1_MB13) MailBox Status Register
-#define AT91C_CAN1_MB13_MFID (AT91_CAST(AT91_REG *) 0xFFF843AC) // (CAN1_MB13) MailBox Family ID Register
-#define AT91C_CAN1_MB13_MAM (AT91_CAST(AT91_REG *) 0xFFF843A4) // (CAN1_MB13) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB13_MMR (AT91_CAST(AT91_REG *) 0xFFF843A0) // (CAN1_MB13) MailBox Mode Register
-#define AT91C_CAN1_MB13_MCR (AT91_CAST(AT91_REG *) 0xFFF843BC) // (CAN1_MB13) MailBox Control Register
-#define AT91C_CAN1_MB13_MDH (AT91_CAST(AT91_REG *) 0xFFF843B8) // (CAN1_MB13) MailBox Data High Register
-#define AT91C_CAN1_MB13_MID (AT91_CAST(AT91_REG *) 0xFFF843A8) // (CAN1_MB13) MailBox ID Register
-// ========== Register definition for CAN1_MB14 peripheral ==========
-#define AT91C_CAN1_MB14_MCR (AT91_CAST(AT91_REG *) 0xFFF843DC) // (CAN1_MB14) MailBox Control Register
-#define AT91C_CAN1_MB14_MID (AT91_CAST(AT91_REG *) 0xFFF843C8) // (CAN1_MB14) MailBox ID Register
-#define AT91C_CAN1_MB14_MMR (AT91_CAST(AT91_REG *) 0xFFF843C0) // (CAN1_MB14) MailBox Mode Register
-#define AT91C_CAN1_MB14_MDH (AT91_CAST(AT91_REG *) 0xFFF843D8) // (CAN1_MB14) MailBox Data High Register
-#define AT91C_CAN1_MB14_MSR (AT91_CAST(AT91_REG *) 0xFFF843D0) // (CAN1_MB14) MailBox Status Register
-#define AT91C_CAN1_MB14_MFID (AT91_CAST(AT91_REG *) 0xFFF843CC) // (CAN1_MB14) MailBox Family ID Register
-#define AT91C_CAN1_MB14_MDL (AT91_CAST(AT91_REG *) 0xFFF843D4) // (CAN1_MB14) MailBox Data Low Register
-#define AT91C_CAN1_MB14_MAM (AT91_CAST(AT91_REG *) 0xFFF843C4) // (CAN1_MB14) MailBox Acceptance Mask Register
-// ========== Register definition for CAN1_MB15 peripheral ==========
-#define AT91C_CAN1_MB15_MSR (AT91_CAST(AT91_REG *) 0xFFF843F0) // (CAN1_MB15) MailBox Status Register
-#define AT91C_CAN1_MB15_MDL (AT91_CAST(AT91_REG *) 0xFFF843F4) // (CAN1_MB15) MailBox Data Low Register
-#define AT91C_CAN1_MB15_MDH (AT91_CAST(AT91_REG *) 0xFFF843F8) // (CAN1_MB15) MailBox Data High Register
-#define AT91C_CAN1_MB15_MMR (AT91_CAST(AT91_REG *) 0xFFF843E0) // (CAN1_MB15) MailBox Mode Register
-#define AT91C_CAN1_MB15_MAM (AT91_CAST(AT91_REG *) 0xFFF843E4) // (CAN1_MB15) MailBox Acceptance Mask Register
-#define AT91C_CAN1_MB15_MFID (AT91_CAST(AT91_REG *) 0xFFF843EC) // (CAN1_MB15) MailBox Family ID Register
-#define AT91C_CAN1_MB15_MCR (AT91_CAST(AT91_REG *) 0xFFF843FC) // (CAN1_MB15) MailBox Control Register
-#define AT91C_CAN1_MB15_MID (AT91_CAST(AT91_REG *) 0xFFF843E8) // (CAN1_MB15) MailBox ID Register
-// ========== Register definition for CAN1 peripheral ==========
-#define AT91C_CAN1_ECR (AT91_CAST(AT91_REG *) 0xFFF84020) // (CAN1) Error Counter Register
-#define AT91C_CAN1_BR (AT91_CAST(AT91_REG *) 0xFFF84014) // (CAN1) Baudrate Register
-#define AT91C_CAN1_IDR (AT91_CAST(AT91_REG *) 0xFFF84008) // (CAN1) Interrupt Disable Register
-#define AT91C_CAN1_ACR (AT91_CAST(AT91_REG *) 0xFFF84028) // (CAN1) Abort Command Register
-#define AT91C_CAN1_IMR (AT91_CAST(AT91_REG *) 0xFFF8400C) // (CAN1) Interrupt Mask Register
-#define AT91C_CAN1_TCR (AT91_CAST(AT91_REG *) 0xFFF84024) // (CAN1) Transfer Command Register
-#define AT91C_CAN1_SR (AT91_CAST(AT91_REG *) 0xFFF84010) // (CAN1) Status Register
-#define AT91C_CAN1_TIM (AT91_CAST(AT91_REG *) 0xFFF84018) // (CAN1) Timer Register
-#define AT91C_CAN1_VR (AT91_CAST(AT91_REG *) 0xFFF840FC) // (CAN1) Version Register
-#define AT91C_CAN1_MR (AT91_CAST(AT91_REG *) 0xFFF84000) // (CAN1) Mode Register
-#define AT91C_CAN1_IER (AT91_CAST(AT91_REG *) 0xFFF84004) // (CAN1) Interrupt Enable Register
-#define AT91C_CAN1_TIMESTP (AT91_CAST(AT91_REG *) 0xFFF8401C) // (CAN1) Time Stamp Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB0 peripheral ==========
-#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
-#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
-// ========== Register definition for TC3 peripheral ==========
-#define AT91C_TC3_IMR (AT91_CAST(AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register
-#define AT91C_TC3_CMR (AT91_CAST(AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC3_IDR (AT91_CAST(AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register
-#define AT91C_TC3_CCR (AT91_CAST(AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register
-#define AT91C_TC3_RA (AT91_CAST(AT91_REG *) 0xFFFA4014) // (TC3) Register A
-#define AT91C_TC3_RB (AT91_CAST(AT91_REG *) 0xFFFA4018) // (TC3) Register B
-#define AT91C_TC3_CV (AT91_CAST(AT91_REG *) 0xFFFA4010) // (TC3) Counter Value
-#define AT91C_TC3_SR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (TC3) Status Register
-#define AT91C_TC3_IER (AT91_CAST(AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register
-#define AT91C_TC3_RC (AT91_CAST(AT91_REG *) 0xFFFA401C) // (TC3) Register C
-// ========== Register definition for TC4 peripheral ==========
-#define AT91C_TC4_SR (AT91_CAST(AT91_REG *) 0xFFFA4060) // (TC4) Status Register
-#define AT91C_TC4_RA (AT91_CAST(AT91_REG *) 0xFFFA4054) // (TC4) Register A
-#define AT91C_TC4_CV (AT91_CAST(AT91_REG *) 0xFFFA4050) // (TC4) Counter Value
-#define AT91C_TC4_CMR (AT91_CAST(AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC4_RB (AT91_CAST(AT91_REG *) 0xFFFA4058) // (TC4) Register B
-#define AT91C_TC4_CCR (AT91_CAST(AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register
-#define AT91C_TC4_IER (AT91_CAST(AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register
-#define AT91C_TC4_IMR (AT91_CAST(AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register
-#define AT91C_TC4_RC (AT91_CAST(AT91_REG *) 0xFFFA405C) // (TC4) Register C
-#define AT91C_TC4_IDR (AT91_CAST(AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register
-// ========== Register definition for TC5 peripheral ==========
-#define AT91C_TC5_CMR (AT91_CAST(AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC5_IDR (AT91_CAST(AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register
-#define AT91C_TC5_CCR (AT91_CAST(AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register
-#define AT91C_TC5_RB (AT91_CAST(AT91_REG *) 0xFFFA4098) // (TC5) Register B
-#define AT91C_TC5_IMR (AT91_CAST(AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register
-#define AT91C_TC5_CV (AT91_CAST(AT91_REG *) 0xFFFA4090) // (TC5) Counter Value
-#define AT91C_TC5_RC (AT91_CAST(AT91_REG *) 0xFFFA409C) // (TC5) Register C
-#define AT91C_TC5_SR (AT91_CAST(AT91_REG *) 0xFFFA40A0) // (TC5) Status Register
-#define AT91C_TC5_IER (AT91_CAST(AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register
-#define AT91C_TC5_RA (AT91_CAST(AT91_REG *) 0xFFFA4094) // (TC5) Register A
-// ========== Register definition for TCB1 peripheral ==========
-#define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0xFFFA40C4) // (TCB1) TC Block Mode Register
-#define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0xFFFA40C0) // (TCB1) TC Block Control Register
-// ========== Register definition for TC6 peripheral ==========
-#define AT91C_TC6_IDR (AT91_CAST(AT91_REG *) 0xFFFA8028) // (TC6) Interrupt Disable Register
-#define AT91C_TC6_RA (AT91_CAST(AT91_REG *) 0xFFFA8014) // (TC6) Register A
-#define AT91C_TC6_IER (AT91_CAST(AT91_REG *) 0xFFFA8024) // (TC6) Interrupt Enable Register
-#define AT91C_TC6_RB (AT91_CAST(AT91_REG *) 0xFFFA8018) // (TC6) Register B
-#define AT91C_TC6_CMR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (TC6) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC6_CCR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (TC6) Channel Control Register
-#define AT91C_TC6_CV (AT91_CAST(AT91_REG *) 0xFFFA8010) // (TC6) Counter Value
-#define AT91C_TC6_RC (AT91_CAST(AT91_REG *) 0xFFFA801C) // (TC6) Register C
-#define AT91C_TC6_IMR (AT91_CAST(AT91_REG *) 0xFFFA802C) // (TC6) Interrupt Mask Register
-#define AT91C_TC6_SR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (TC6) Status Register
-// ========== Register definition for TC7 peripheral ==========
-#define AT91C_TC7_IMR (AT91_CAST(AT91_REG *) 0xFFFA806C) // (TC7) Interrupt Mask Register
-#define AT91C_TC7_SR (AT91_CAST(AT91_REG *) 0xFFFA8060) // (TC7) Status Register
-#define AT91C_TC7_IDR (AT91_CAST(AT91_REG *) 0xFFFA8068) // (TC7) Interrupt Disable Register
-#define AT91C_TC7_CMR (AT91_CAST(AT91_REG *) 0xFFFA8044) // (TC7) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC7_CV (AT91_CAST(AT91_REG *) 0xFFFA8050) // (TC7) Counter Value
-#define AT91C_TC7_RA (AT91_CAST(AT91_REG *) 0xFFFA8054) // (TC7) Register A
-#define AT91C_TC7_RB (AT91_CAST(AT91_REG *) 0xFFFA8058) // (TC7) Register B
-#define AT91C_TC7_RC (AT91_CAST(AT91_REG *) 0xFFFA805C) // (TC7) Register C
-#define AT91C_TC7_CCR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (TC7) Channel Control Register
-#define AT91C_TC7_IER (AT91_CAST(AT91_REG *) 0xFFFA8064) // (TC7) Interrupt Enable Register
-// ========== Register definition for TC8 peripheral ==========
-#define AT91C_TC8_RA (AT91_CAST(AT91_REG *) 0xFFFA8094) // (TC8) Register A
-#define AT91C_TC8_IDR (AT91_CAST(AT91_REG *) 0xFFFA80A8) // (TC8) Interrupt Disable Register
-#define AT91C_TC8_RC (AT91_CAST(AT91_REG *) 0xFFFA809C) // (TC8) Register C
-#define AT91C_TC8_CCR (AT91_CAST(AT91_REG *) 0xFFFA8080) // (TC8) Channel Control Register
-#define AT91C_TC8_SR (AT91_CAST(AT91_REG *) 0xFFFA80A0) // (TC8) Status Register
-#define AT91C_TC8_RB (AT91_CAST(AT91_REG *) 0xFFFA8098) // (TC8) Register B
-#define AT91C_TC8_IMR (AT91_CAST(AT91_REG *) 0xFFFA80AC) // (TC8) Interrupt Mask Register
-#define AT91C_TC8_CMR (AT91_CAST(AT91_REG *) 0xFFFA8084) // (TC8) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC8_IER (AT91_CAST(AT91_REG *) 0xFFFA80A4) // (TC8) Interrupt Enable Register
-#define AT91C_TC8_CV (AT91_CAST(AT91_REG *) 0xFFFA8090) // (TC8) Counter Value
-// ========== Register definition for TCB2 peripheral ==========
-#define AT91C_TCB2_BMR (AT91_CAST(AT91_REG *) 0xFFFA80C4) // (TCB2) TC Block Mode Register
-#define AT91C_TCB2_BCR (AT91_CAST(AT91_REG *) 0xFFFA80C0) // (TCB2) TC Block Control Register
-// ========== Register definition for PDC_MCI peripheral ==========
-#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_MCI) PDC Transfer Status Register
-#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_MCI) Receive Pointer Register
-#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_MCI) Receive Next Counter Register
-#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_MCI) Receive Counter Register
-#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_MCI) PDC Transfer Control Register
-#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_MCI) Transmit Pointer Register
-#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_MCI) Receive Next Pointer Register
-#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_MCI) Transmit Next Pointer Register
-#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_MCI) Transmit Counter Register
-#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_MCI) Transmit Next Counter Register
-// ========== Register definition for MCI peripheral ==========
-#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (MCI) MCI Transmit Data Register
-#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFAC048) // (MCI) MCI Interrupt Disable Register
-#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFAC040) // (MCI) MCI Status Register
-#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFAC014) // (MCI) MCI Command Register
-#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (MCI) MCI Data Timeout Register
-#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFAC044) // (MCI) MCI Interrupt Enable Register
-#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (MCI) MCI Argument Register
-#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (MCI) MCI SD Card Register
-#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (MCI) MCI Receive Data Register
-#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFAC04C) // (MCI) MCI Interrupt Mask Register
-#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (MCI) MCI Mode Register
-#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (MCI) MCI Response Register
-#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (MCI) MCI Control Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US2 peripheral ==========
-#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
-#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register
-#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register
-#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register
-#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
-#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register
-#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
-#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register
-#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
-#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
-// ========== Register definition for US2 peripheral ==========
-#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register
-#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register
-#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register
-#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register
-#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register
-#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (US2) Control Register
-#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register
-#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register
-#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register
-#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register
-#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (US2) Mode Register
-#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register
-#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register
-#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH4 peripheral ==========
-#define AT91C_PWMC_CH4_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC294) // (PWMC_CH4) Reserved
-#define AT91C_PWMC_CH4_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC284) // (PWMC_CH4) Channel Duty Cycle Register
-#define AT91C_PWMC_CH4_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC290) // (PWMC_CH4) Channel Update Register
-#define AT91C_PWMC_CH4_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC28C) // (PWMC_CH4) Channel Counter Register
-#define AT91C_PWMC_CH4_CMR (AT91_CAST(AT91_REG *) 0xFFFCC280) // (PWMC_CH4) Channel Mode Register
-#define AT91C_PWMC_CH4_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC288) // (PWMC_CH4) Channel Period Register
-// ========== Register definition for PWMC_CH5 peripheral ==========
-#define AT91C_PWMC_CH5_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2B4) // (PWMC_CH5) Reserved
-#define AT91C_PWMC_CH5_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2AC) // (PWMC_CH5) Channel Counter Register
-#define AT91C_PWMC_CH5_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2A4) // (PWMC_CH5) Channel Duty Cycle Register
-#define AT91C_PWMC_CH5_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2A8) // (PWMC_CH5) Channel Period Register
-#define AT91C_PWMC_CH5_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2A0) // (PWMC_CH5) Channel Mode Register
-#define AT91C_PWMC_CH5_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2B0) // (PWMC_CH5) Channel Update Register
-// ========== Register definition for PWMC_CH6 peripheral ==========
-#define AT91C_PWMC_CH6_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2CC) // (PWMC_CH6) Channel Counter Register
-#define AT91C_PWMC_CH6_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2C0) // (PWMC_CH6) Channel Mode Register
-#define AT91C_PWMC_CH6_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2C4) // (PWMC_CH6) Channel Duty Cycle Register
-#define AT91C_PWMC_CH6_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2D4) // (PWMC_CH6) Reserved
-#define AT91C_PWMC_CH6_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2C8) // (PWMC_CH6) Channel Period Register
-#define AT91C_PWMC_CH6_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2D0) // (PWMC_CH6) Channel Update Register
-// ========== Register definition for PWMC_CH7 peripheral ==========
-#define AT91C_PWMC_CH7_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC2EC) // (PWMC_CH7) Channel Counter Register
-#define AT91C_PWMC_CH7_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC2E4) // (PWMC_CH7) Channel Duty Cycle Register
-#define AT91C_PWMC_CH7_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC2E8) // (PWMC_CH7) Channel Period Register
-#define AT91C_PWMC_CH7_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC2F4) // (PWMC_CH7) Reserved
-#define AT91C_PWMC_CH7_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC2F0) // (PWMC_CH7) Channel Update Register
-#define AT91C_PWMC_CH7_CMR (AT91_CAST(AT91_REG *) 0xFFFCC2E0) // (PWMC_CH7) Channel Mode Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for PDC_SSC0 peripheral ==========
-#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
-#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
-#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
-#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
-#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
-#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
-#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register
-#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
-#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
-#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
-// ========== Register definition for SSC0 peripheral ==========
-#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register
-#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register
-#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register
-#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register
-#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFD0040) // (SSC0) Status Register
-#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register
-#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register
-#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (SSC0) Control Register
-#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register
-#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register
-#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister
-#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register
-#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register
-#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register
-// ========== Register definition for PDC_SSC1 peripheral ==========
-#define AT91C_SSC1_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
-#define AT91C_SSC1_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
-#define AT91C_SSC1_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
-#define AT91C_SSC1_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
-#define AT91C_SSC1_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
-#define AT91C_SSC1_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
-#define AT91C_SSC1_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register
-#define AT91C_SSC1_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
-#define AT91C_SSC1_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
-#define AT91C_SSC1_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
-// ========== Register definition for SSC1 peripheral ==========
-#define AT91C_SSC1_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register
-#define AT91C_SSC1_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register
-#define AT91C_SSC1_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register
-#define AT91C_SSC1_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register
-#define AT91C_SSC1_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register
-#define AT91C_SSC1_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister
-#define AT91C_SSC1_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register
-#define AT91C_SSC1_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register
-#define AT91C_SSC1_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC1) Status Register
-#define AT91C_SSC1_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register
-#define AT91C_SSC1_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register
-#define AT91C_SSC1_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC1) Control Register
-#define AT91C_SSC1_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register
-#define AT91C_SSC1_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register
-// ========== Register definition for PDC_ADC0 peripheral ==========
-#define AT91C_ADC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC0) PDC Transfer Status Register
-#define AT91C_ADC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC0) PDC Transfer Control Register
-#define AT91C_ADC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC0) Transmit Next Pointer Register
-#define AT91C_ADC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC0) Transmit Next Counter Register
-#define AT91C_ADC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC0) Receive Next Pointer Register
-#define AT91C_ADC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC0) Receive Next Counter Register
-#define AT91C_ADC0_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC0) Receive Pointer Register
-#define AT91C_ADC0_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC0) Transmit Counter Register
-#define AT91C_ADC0_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC0) Transmit Pointer Register
-#define AT91C_ADC0_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC0) Receive Counter Register
-// ========== Register definition for ADC0 peripheral ==========
-#define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC0) ADC Channel Data Register 2
-#define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC0) ADC Channel Data Register 3
-#define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC0) ADC Channel Data Register 0
-#define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC0) ADC Channel Data Register 5
-#define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC0) ADC Channel Disable Register
-#define AT91C_ADC0_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC0) ADC Status Register
-#define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC0) ADC Channel Data Register 4
-#define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC0) ADC Channel Data Register 1
-#define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC0) ADC Last Converted Data Register
-#define AT91C_ADC0_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC0) ADC Interrupt Disable Register
-#define AT91C_ADC0_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC0) ADC Control Register
-#define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC0) ADC Channel Data Register 7
-#define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC0) ADC Channel Data Register 6
-#define AT91C_ADC0_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC0) ADC Interrupt Enable Register
-#define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC0) ADC Channel Enable Register
-#define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC0) ADC Channel Status Register
-#define AT91C_ADC0_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC0) ADC Mode Register
-#define AT91C_ADC0_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC0) ADC Interrupt Mask Register
-// ========== Register definition for PDC_ADC1 peripheral ==========
-#define AT91C_ADC1_RCR (AT91_CAST(AT91_REG *) 0xFFFDC104) // (PDC_ADC1) Receive Counter Register
-#define AT91C_ADC1_TPR (AT91_CAST(AT91_REG *) 0xFFFDC108) // (PDC_ADC1) Transmit Pointer Register
-#define AT91C_ADC1_TNPR (AT91_CAST(AT91_REG *) 0xFFFDC118) // (PDC_ADC1) Transmit Next Pointer Register
-#define AT91C_ADC1_RNCR (AT91_CAST(AT91_REG *) 0xFFFDC114) // (PDC_ADC1) Receive Next Counter Register
-#define AT91C_ADC1_PTSR (AT91_CAST(AT91_REG *) 0xFFFDC124) // (PDC_ADC1) PDC Transfer Status Register
-#define AT91C_ADC1_PTCR (AT91_CAST(AT91_REG *) 0xFFFDC120) // (PDC_ADC1) PDC Transfer Control Register
-#define AT91C_ADC1_RNPR (AT91_CAST(AT91_REG *) 0xFFFDC110) // (PDC_ADC1) Receive Next Pointer Register
-#define AT91C_ADC1_TNCR (AT91_CAST(AT91_REG *) 0xFFFDC11C) // (PDC_ADC1) Transmit Next Counter Register
-#define AT91C_ADC1_TCR (AT91_CAST(AT91_REG *) 0xFFFDC10C) // (PDC_ADC1) Transmit Counter Register
-#define AT91C_ADC1_RPR (AT91_CAST(AT91_REG *) 0xFFFDC100) // (PDC_ADC1) Receive Pointer Register
-// ========== Register definition for ADC1 peripheral ==========
-#define AT91C_ADC1_IER (AT91_CAST(AT91_REG *) 0xFFFDC024) // (ADC1) ADC Interrupt Enable Register
-#define AT91C_ADC1_CHSR (AT91_CAST(AT91_REG *) 0xFFFDC018) // (ADC1) ADC Channel Status Register
-#define AT91C_ADC1_MR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (ADC1) ADC Mode Register
-#define AT91C_ADC1_CR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (ADC1) ADC Control Register
-#define AT91C_ADC1_LCDR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (ADC1) ADC Last Converted Data Register
-#define AT91C_ADC1_CHER (AT91_CAST(AT91_REG *) 0xFFFDC010) // (ADC1) ADC Channel Enable Register
-#define AT91C_ADC1_CHDR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (ADC1) ADC Channel Disable Register
-#define AT91C_ADC1_IMR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (ADC1) ADC Interrupt Mask Register
-#define AT91C_ADC1_CDR1 (AT91_CAST(AT91_REG *) 0xFFFDC034) // (ADC1) ADC Channel Data Register 1
-#define AT91C_ADC1_CDR4 (AT91_CAST(AT91_REG *) 0xFFFDC040) // (ADC1) ADC Channel Data Register 4
-#define AT91C_ADC1_CDR0 (AT91_CAST(AT91_REG *) 0xFFFDC030) // (ADC1) ADC Channel Data Register 0
-#define AT91C_ADC1_CDR5 (AT91_CAST(AT91_REG *) 0xFFFDC044) // (ADC1) ADC Channel Data Register 5
-#define AT91C_ADC1_CDR3 (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (ADC1) ADC Channel Data Register 3
-#define AT91C_ADC1_CDR6 (AT91_CAST(AT91_REG *) 0xFFFDC048) // (ADC1) ADC Channel Data Register 6
-#define AT91C_ADC1_SR (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (ADC1) ADC Status Register
-#define AT91C_ADC1_CDR2 (AT91_CAST(AT91_REG *) 0xFFFDC038) // (ADC1) ADC Channel Data Register 2
-#define AT91C_ADC1_CDR7 (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (ADC1) ADC Channel Data Register 7
-#define AT91C_ADC1_IDR (AT91_CAST(AT91_REG *) 0xFFFDC028) // (ADC1) ADC Interrupt Disable Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_TWD (AT91C_PIO_PA0) // TWI Two-wire Serial Data
-#define AT91C_PA0_ADTRG0 (AT91C_PIO_PA0) // ADC0 External Trigger
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TWCK (AT91C_PIO_PA1) // TWI Two-wire Serial Clock
-#define AT91C_PA1_ADTRG1 (AT91C_PIO_PA1) // ADC1 External Trigger
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TXD2 (AT91C_PIO_PA10) // USART 2 Transmit Data
-#define AT91C_PA10_SPI1_SPCK (AT91C_PIO_PA10) // SPI1 Serial Clock
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_SPI0_NPCS0 (AT91C_PIO_PA11) // SPI0 Peripheral Chip Select 0
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS1 (AT91C_PIO_PA12) // SPI0 Peripheral Chip Select 1
-#define AT91C_PA12_MCDA1 (AT91C_PIO_PA12) // Multimedia Card A Data 1
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS2 (AT91C_PIO_PA13) // SPI0 Peripheral Chip Select 2
-#define AT91C_PA13_MCDA2 (AT91C_PIO_PA13) // Multimedia Card A Data 2
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS3 (AT91C_PIO_PA14) // SPI0 Peripheral Chip Select 3
-#define AT91C_PA14_MCDA3 (AT91C_PIO_PA14) // Multimedia Card A Data 3
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_MISO (AT91C_PIO_PA15) // SPI0 Master In Slave
-#define AT91C_PA15_MCDA0 (AT91C_PIO_PA15) // Multimedia Card A Data 0
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MOSI (AT91C_PIO_PA16) // SPI0 Master Out Slave
-#define AT91C_PA16_MCCDA (AT91C_PIO_PA16) // Multimedia Card A Command
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_SPCK (AT91C_PIO_PA17) // SPI0 Serial Clock
-#define AT91C_PA17_MCCK (AT91C_PIO_PA17) // Multimedia Card Clock
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_PWM0 (AT91C_PIO_PA18) // PWMC Channel 0
-#define AT91C_PA18_PCK0 (AT91C_PIO_PA18) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_PWM1 (AT91C_PIO_PA19) // PWMC Channel 1
-#define AT91C_PA19_PCK1 (AT91C_PIO_PA19) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_RXD0 (AT91C_PIO_PA2) // USART 0 Receive Data
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_PWM2 (AT91C_PIO_PA20) // PWMC Channel 2
-#define AT91C_PA20_PCK2 (AT91C_PIO_PA20) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_PWM3 (AT91C_PIO_PA21) // PWMC Channel 3
-#define AT91C_PA21_PCK3 (AT91C_PIO_PA21) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_PWM4 (AT91C_PIO_PA22) // PWMC Channel 4
-#define AT91C_PA22_IRQ0 (AT91C_PIO_PA22) // Interrupt input 0
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_PWM5 (AT91C_PIO_PA23) // PWMC Channel 5
-#define AT91C_PA23_IRQ1 (AT91C_PIO_PA23) // Interrupt input 1
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_PWM6 (AT91C_PIO_PA24) // PWMC Channel 6
-#define AT91C_PA24_TCLK4 (AT91C_PIO_PA24) // Timer Counter 4 external Clock Input
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_PWM7 (AT91C_PIO_PA25) // PWMC Channel 7
-#define AT91C_PA25_TCLK5 (AT91C_PIO_PA25) // Timer Counter 5 external Clock Input
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_CANRX0 (AT91C_PIO_PA26) // CAN Receive 0
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_CANTX0 (AT91C_PIO_PA27) // CAN Transmit 0
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_CANRX1 (AT91C_PIO_PA28) // CAN Receive 1
-#define AT91C_PA28_TCLK3 (AT91C_PIO_PA28) // Timer Counter 3 external Clock Input
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_CANTX1 (AT91C_PIO_PA29) // CAN Transmit 1
-#define AT91C_PA29_TCLK6 (AT91C_PIO_PA29) // Timer Counter 6 external clock input
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_TXD0 (AT91C_PIO_PA3) // USART 0 Transmit Data
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data
-#define AT91C_PA30_TCLK7 (AT91C_PIO_PA30) // Timer Counter 7 external clock input
-#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data
-#define AT91C_PA31_TCLK8 (AT91C_PIO_PA31) // Timer Counter 8 external clock input
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_SCK0 (AT91C_PIO_PA4) // USART 0 Serial Clock
-#define AT91C_PA4_SPI1_NPCS0 (AT91C_PIO_PA4) // SPI1 Peripheral Chip Select 0
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RTS0 (AT91C_PIO_PA5) // USART 0 Ready To Send
-#define AT91C_PA5_SPI1_NPCS1 (AT91C_PIO_PA5) // SPI1 Peripheral Chip Select 1
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_CTS0 (AT91C_PIO_PA6) // USART 0 Clear To Send
-#define AT91C_PA6_SPI1_NPCS2 (AT91C_PIO_PA6) // SPI1 Peripheral Chip Select 2
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_RXD1 (AT91C_PIO_PA7) // USART 1 Receive Data
-#define AT91C_PA7_SPI1_NPCS3 (AT91C_PIO_PA7) // SPI1 Peripheral Chip Select 3
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_TXD1 (AT91C_PIO_PA8) // USART 1 Transmit Data
-#define AT91C_PA8_SPI1_MISO (AT91C_PIO_PA8) // SPI1 Master In Slave
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_RXD2 (AT91C_PIO_PA9) // USART 2 Receive Data
-#define AT91C_PA9_SPI1_MOSI (AT91C_PIO_PA9) // SPI1 Master Out Slave
-#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_IRQ2 (AT91C_PIO_PB0) // Interrupt input 2
-#define AT91C_PB0_PWM5 (AT91C_PIO_PB0) // PWMC Channel 5
-#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_IRQ3 (AT91C_PIO_PB1) // Interrupt input 3
-#define AT91C_PB1_PWM6 (AT91C_PIO_PB1) // PWMC Channel 6
-#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_TCLK1 (AT91C_PIO_PB10) // Timer Counter 1 external clock input
-#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1
-#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_TCLK2 (AT91C_PIO_PB11) // Timer Counter 2 external clock input
-#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1
-#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_TIOA0 (AT91C_PIO_PB12) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB12_TD1 (AT91C_PIO_PB12) // SSC Transmit Data 1
-#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_TIOB0 (AT91C_PIO_PB13) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB13_RD1 (AT91C_PIO_PB13) // SSC Receive Data 1
-#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_TIOA1 (AT91C_PIO_PB14) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB14_PWM0 (AT91C_PIO_PB14) // PWMC Channel 0
-#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_TIOB1 (AT91C_PIO_PB15) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB15_PWM1 (AT91C_PIO_PB15) // PWMC Channel 1
-#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_TIOA2 (AT91C_PIO_PB16) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB16_PWM2 (AT91C_PIO_PB16) // PWMC Channel 2
-#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_TIOB2 (AT91C_PIO_PB17) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB17_PWM3 (AT91C_PIO_PB17) // PWMC Channel 3
-#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_TIOA3 (AT91C_PIO_PB18) // Timer Counter 3 Multipurpose Timer I/O Pin A
-#define AT91C_PB18_PWM4 (AT91C_PIO_PB18) // PWMC Channel 4
-#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_TIOB3 (AT91C_PIO_PB19) // Timer Counter 3 Multipurpose Timer I/O Pin B
-#define AT91C_PB19_SPI1_NPCS1 (AT91C_PIO_PB19) // SPI1 Peripheral Chip Select 1
-#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_TF0 (AT91C_PIO_PB2) // SSC Transmit Frame Sync 0
-#define AT91C_PB2_PWM7 (AT91C_PIO_PB2) // PWMC Channel 7
-#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_TIOA4 (AT91C_PIO_PB20) // Timer Counter 4 Multipurpose Timer I/O Pin A
-#define AT91C_PB20_SPI1_NPCS2 (AT91C_PIO_PB20) // SPI1 Peripheral Chip Select 2
-#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_TIOB4 (AT91C_PIO_PB21) // Timer Counter 4 Multipurpose Timer I/O Pin B
-#define AT91C_PB21_SPI1_NPCS3 (AT91C_PIO_PB21) // SPI1 Peripheral Chip Select 3
-#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_TIOA5 (AT91C_PIO_PB22) // Timer Counter 5 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOB5 (AT91C_PIO_PB23) // Timer Counter 5 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOA6 (AT91C_PIO_PB24) // Timer Counter 6 Multipurpose Timer I/O Pin A
-#define AT91C_PB24_RTS1 (AT91C_PIO_PB24) // USART 1 Ready To Send
-#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOB6 (AT91C_PIO_PB25) // Timer Counter 6 Multipurpose Timer I/O Pin B
-#define AT91C_PB25_CTS1 (AT91C_PIO_PB25) // USART 1 Clear To Send
-#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOA7 (AT91C_PIO_PB26) // Timer Counter 7 Multipurpose Timer I/O Pin A
-#define AT91C_PB26_SCK1 (AT91C_PIO_PB26) // USART 1 Serial Clock
-#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOB7 (AT91C_PIO_PB27) // Timer Counter 7 Multipurpose Timer I/O Pin B
-#define AT91C_PB27_RTS2 (AT91C_PIO_PB27) // USART 2 Ready To Send
-#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOA8 (AT91C_PIO_PB28) // Timer Counter 8 Multipurpose Timer I/O Pin A
-#define AT91C_PB28_CTS2 (AT91C_PIO_PB28) // USART 2 Clear To Send
-#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_TIOB8 (AT91C_PIO_PB29) // Timer Counter 8 Multipurpose Timer I/O Pin B
-#define AT91C_PB29_SCK2 (AT91C_PIO_PB29) // USART 2 Serial Clock
-#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_TK0 (AT91C_PIO_PB3) // SSC Transmit Clock 0
-#define AT91C_PB3_PCK0 (AT91C_PIO_PB3) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_TD0 (AT91C_PIO_PB4) // SSC Transmit data
-#define AT91C_PB4_PCK1 (AT91C_PIO_PB4) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_RD0 (AT91C_PIO_PB5) // SSC Receive Data
-#define AT91C_PB5_PCK2 (AT91C_PIO_PB5) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_RK0 (AT91C_PIO_PB6) // SSC Receive Clock
-#define AT91C_PB6_PCK3 (AT91C_PIO_PB6) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_RF0 (AT91C_PIO_PB7) // SSC Receive Frame Sync 0
-#define AT91C_PB7_CANTX1 (AT91C_PIO_PB7) // CAN Transmit 1
-#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_FIQ (AT91C_PIO_PB8) // AIC Fast Interrupt Input
-#define AT91C_PB8_TF1 (AT91C_PIO_PB8) // SSC Transmit Frame Sync 1
-#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_TCLK0 (AT91C_PIO_PB9) // Timer Counter 0 external clock input
-#define AT91C_PB9_TK1 (AT91C_PIO_PB9) // SSC Transmit Clock 1
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
-#define AT91C_ID_CAN0 ( 4) // Control Area Network Controller 0
-#define AT91C_ID_CAN1 ( 5) // Control Area Network Controller 1
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_US2 ( 8) // USART 2
-#define AT91C_ID_MCI ( 9) // Multimedia Card Interface
-#define AT91C_ID_TWI (10) // Two-Wire Interface
-#define AT91C_ID_SPI0 (11) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 (12) // Serial Peripheral Interface 1
-#define AT91C_ID_SSC0 (13) // Serial Synchronous Controller 0
-#define AT91C_ID_SSC1 (14) // Serial Synchronous Controller 1
-#define AT91C_ID_TC0 (15) // Timer Counter 0
-#define AT91C_ID_TC1 (16) // Timer Counter 1
-#define AT91C_ID_TC2 (17) // Timer Counter 2
-#define AT91C_ID_TC3 (18) // Timer Counter 3
-#define AT91C_ID_TC4 (19) // Timer Counter 4
-#define AT91C_ID_TC5 (20) // Timer Counter 5
-#define AT91C_ID_TC6 (21) // Timer Counter 6
-#define AT91C_ID_TC7 (22) // Timer Counter 7
-#define AT91C_ID_TC8 (23) // Timer Counter 8
-#define AT91C_ID_ADC0 (24) // Analog To Digital Converter 0
-#define AT91C_ID_ADC1 (25) // Analog To Digital Converter 1
-#define AT91C_ID_PWMC (26) // Pulse Width Modulation Controller
-#define AT91C_ID_UDP (27) // USB Device Port
-#define AT91C_ID_IRQ0 (28) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (29) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ID_IRQ2 (30) // Advanced Interrupt Controller (IRQ2)
-#define AT91C_ID_IRQ3 (31) // Advanced Interrupt Controller (IRQ3)
-#define AT91C_ALL_INT (0xFFFFFFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_CAN0_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80200) // (CAN0_MB0) Base Address
-#define AT91C_BASE_CAN0_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80220) // (CAN0_MB1) Base Address
-#define AT91C_BASE_CAN0_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80240) // (CAN0_MB2) Base Address
-#define AT91C_BASE_CAN0_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80260) // (CAN0_MB3) Base Address
-#define AT91C_BASE_CAN0_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80280) // (CAN0_MB4) Base Address
-#define AT91C_BASE_CAN0_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802A0) // (CAN0_MB5) Base Address
-#define AT91C_BASE_CAN0_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802C0) // (CAN0_MB6) Base Address
-#define AT91C_BASE_CAN0_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFF802E0) // (CAN0_MB7) Base Address
-#define AT91C_BASE_CAN0_MB8 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80300) // (CAN0_MB8) Base Address
-#define AT91C_BASE_CAN0_MB9 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80320) // (CAN0_MB9) Base Address
-#define AT91C_BASE_CAN0_MB10 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80340) // (CAN0_MB10) Base Address
-#define AT91C_BASE_CAN0_MB11 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80360) // (CAN0_MB11) Base Address
-#define AT91C_BASE_CAN0_MB12 (AT91_CAST(AT91PS_CAN_MB) 0xFFF80380) // (CAN0_MB12) Base Address
-#define AT91C_BASE_CAN0_MB13 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803A0) // (CAN0_MB13) Base Address
-#define AT91C_BASE_CAN0_MB14 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803C0) // (CAN0_MB14) Base Address
-#define AT91C_BASE_CAN0_MB15 (AT91_CAST(AT91PS_CAN_MB) 0xFFF803E0) // (CAN0_MB15) Base Address
-#define AT91C_BASE_CAN0 (AT91_CAST(AT91PS_CAN) 0xFFF80000) // (CAN0) Base Address
-#define AT91C_BASE_CAN1_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84200) // (CAN1_MB0) Base Address
-#define AT91C_BASE_CAN1_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84220) // (CAN1_MB1) Base Address
-#define AT91C_BASE_CAN1_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84240) // (CAN1_MB2) Base Address
-#define AT91C_BASE_CAN1_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84260) // (CAN1_MB3) Base Address
-#define AT91C_BASE_CAN1_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84280) // (CAN1_MB4) Base Address
-#define AT91C_BASE_CAN1_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842A0) // (CAN1_MB5) Base Address
-#define AT91C_BASE_CAN1_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842C0) // (CAN1_MB6) Base Address
-#define AT91C_BASE_CAN1_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFF842E0) // (CAN1_MB7) Base Address
-#define AT91C_BASE_CAN1_MB8 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84300) // (CAN1_MB8) Base Address
-#define AT91C_BASE_CAN1_MB9 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84320) // (CAN1_MB9) Base Address
-#define AT91C_BASE_CAN1_MB10 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84340) // (CAN1_MB10) Base Address
-#define AT91C_BASE_CAN1_MB11 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84360) // (CAN1_MB11) Base Address
-#define AT91C_BASE_CAN1_MB12 (AT91_CAST(AT91PS_CAN_MB) 0xFFF84380) // (CAN1_MB12) Base Address
-#define AT91C_BASE_CAN1_MB13 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843A0) // (CAN1_MB13) Base Address
-#define AT91C_BASE_CAN1_MB14 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843C0) // (CAN1_MB14) Base Address
-#define AT91C_BASE_CAN1_MB15 (AT91_CAST(AT91PS_CAN_MB) 0xFFF843E0) // (CAN1_MB15) Base Address
-#define AT91C_BASE_CAN1 (AT91_CAST(AT91PS_CAN) 0xFFF84000) // (CAN1) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
-#define AT91C_BASE_TC3 (AT91_CAST(AT91PS_TC) 0xFFFA4000) // (TC3) Base Address
-#define AT91C_BASE_TC4 (AT91_CAST(AT91PS_TC) 0xFFFA4040) // (TC4) Base Address
-#define AT91C_BASE_TC5 (AT91_CAST(AT91PS_TC) 0xFFFA4080) // (TC5) Base Address
-#define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0xFFFA4000) // (TCB1) Base Address
-#define AT91C_BASE_TC6 (AT91_CAST(AT91PS_TC) 0xFFFA8000) // (TC6) Base Address
-#define AT91C_BASE_TC7 (AT91_CAST(AT91PS_TC) 0xFFFA8040) // (TC7) Base Address
-#define AT91C_BASE_TC8 (AT91_CAST(AT91PS_TC) 0xFFFA8080) // (TC8) Base Address
-#define AT91C_BASE_TCB2 (AT91_CAST(AT91PS_TCB) 0xFFFA8000) // (TCB2) Base Address
-#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_MCI) Base Address
-#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFAC000) // (MCI) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address
-#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFC8000) // (US2) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH4 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC280) // (PWMC_CH4) Base Address
-#define AT91C_BASE_PWMC_CH5 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2A0) // (PWMC_CH5) Base Address
-#define AT91C_BASE_PWMC_CH6 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2C0) // (PWMC_CH6) Base Address
-#define AT91C_BASE_PWMC_CH7 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC2E0) // (PWMC_CH7) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address
-#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address
-#define AT91C_BASE_PDC_SSC1 (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address
-#define AT91C_BASE_SSC1 (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address
-#define AT91C_BASE_PDC_ADC0 (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC0) Base Address
-#define AT91C_BASE_ADC0 (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC0) Base Address
-#define AT91C_BASE_PDC_ADC1 (AT91_CAST(AT91PS_PDC) 0xFFFDC100) // (PDC_ADC1) Base Address
-#define AT91C_BASE_ADC1 (AT91_CAST(AT91PS_ADC) 0xFFFDC000) // (ADC1) Base Address
-#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7A3
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h deleted file mode 100644 index 8fc3a9883..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S128.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7S128.h
-// Object : AT91SAM7S128 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:12:49)
-//
-// CVS Reference : /AT91SAM7S128.pl/1.12/Wed Aug 30 14:08:34 2006//
-// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
-// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//
-// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S128_H
-#define AT91SAM7S128_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[469]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved15[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved16[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved17[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved18[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved19[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved20[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved4[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register
- AT91_REG Reserved3[4]; //
- AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[5]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7S128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
-#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
-#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
-#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
-#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
-#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
-#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
-#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
-#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
-#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
-#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
-#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
-#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
-#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
-#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
-#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
-#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
-#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
-#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
-#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
-#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S128
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h deleted file mode 100644 index a4f1af138..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S256.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7S256.h
-// Object : AT91SAM7S256 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:12:57)
-//
-// CVS Reference : /AT91SAM7S256.pl/1.12/Wed Aug 30 14:08:39 2006//
-// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
-// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//
-// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S256_H
-#define AT91SAM7S256_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[469]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved15[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved16[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved17[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved18[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved19[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved20[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved4[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register
- AT91_REG Reserved3[4]; //
- AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[5]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
-#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
-#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
-#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
-#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
-#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
-#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
-#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
-#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
-#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
-#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
-#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
-#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
-#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
-#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
-#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
-#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
-#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
-#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
-#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
-#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h deleted file mode 100644 index aa45c3924..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S512.h +++ /dev/null @@ -1,2303 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7S512.h
-// Object : AT91SAM7S512 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:13:20)
-//
-// CVS Reference : /AT91SAM7S512.pl/1.6/Wed Aug 30 14:08:44 2006//
-// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
-// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
-// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//
-// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005//
-// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005//
-// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005//
-// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S512_H
-#define AT91SAM7S512_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[469]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved15[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved16[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved17[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved18[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved19[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved20[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved4[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EFC {
- AT91_REG EFC_FMR; // MC Flash Mode Register
- AT91_REG EFC_FCR; // MC Flash Command Register
- AT91_REG EFC_FSR; // MC Flash Status Register
- AT91_REG EFC_VR; // MC Flash Version Register
-} AT91S_EFC, *AT91PS_EFC;
-#else
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register
-#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register
-
-#endif
-// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key
-// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status
-// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
-#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number
-#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG MC_PUIA[16]; // MC Protection Unit Area
- AT91_REG MC_PUP; // MC Protection Unit Peripherals
- AT91_REG MC_PUER; // MC Protection Unit Enable Register
- AT91_REG Reserved1[2]; //
- AT91_REG MC0_FMR; // MC Flash Mode Register
- AT91_REG MC0_FCR; // MC Flash Command Register
- AT91_REG MC0_FSR; // MC Flash Status Register
- AT91_REG MC0_VR; // MC Flash Version Register
- AT91_REG MC1_FMR; // MC Flash Mode Register
- AT91_REG MC1_FCR; // MC Flash Command Register
- AT91_REG MC1_FSR; // MC Flash Status Register
- AT91_REG MC1_VR; // MC Flash Version Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection
-#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access
-#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size
-#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte
-#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte
-#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte
-#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte
-#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte
-#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte
-#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte
-#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte
-#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte
-#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte
-#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte
-#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte
-#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte
-#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte
-#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte
-#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte
-#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register
- AT91_REG Reserved3[4]; //
- AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[5]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7S512
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for EFC0 peripheral ==========
-#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register
-#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register
-#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register
-#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register
-// ========== Register definition for EFC1 peripheral ==========
-#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register
-#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register
-#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register
-#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
-#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
-#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
-#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
-#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
-#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
-#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
-#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
-#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
-#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
-#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
-#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
-#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
-#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
-#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
-#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
-#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
-#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
-#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
-#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
-#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address
-#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S512
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h deleted file mode 100644 index d124ce2a9..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7S64.h +++ /dev/null @@ -1,2229 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7S64.h
-// Object : AT91SAM7S64 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:13:29)
-//
-// CVS Reference : /AT91SAM7S64.pl/1.23/Wed Aug 30 14:08:51 2006//
-// CVS Reference : /SYS_SAM7S.pl/1.2/Thu Feb 3 10:47:39 2005//
-// CVS Reference : /MC_SAM7S.pl/1.4/Thu Feb 16 16:45:50 2006//
-// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_4ept.pl/1.1/Thu Aug 3 12:26:00 2006//
-// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S64_H
-#define AT91SAM7S64_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[469]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved15[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved16[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved17[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved18[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved19[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved20[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[3]; // Programmable Clock Register
- AT91_REG Reserved4[5]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register
- AT91_REG Reserved3[4]; //
- AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[5]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI peripheral ==========
-#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
-#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-// ========== Register definition for SPI peripheral ==========
-#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
-#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
-#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
-#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
-#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
-#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
-#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
-#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
-#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
-#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
-#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
-#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
-#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
-#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
-#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
-#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
-#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
-#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
-#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
-#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
-#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
-#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ( 3) // Reserved
-#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved (15) // Reserved
-#define AT91C_ID_16_Reserved (16) // Reserved
-#define AT91C_ID_17_Reserved (17) // Reserved
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h deleted file mode 100644 index 7fab07f8b..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X128.h +++ /dev/null @@ -1,2914 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7X128.h
-// Object : AT91SAM7X128 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:15:23)
-//
-// CVS Reference : /AT91SAM7X128.pl/1.19/Wed Aug 30 14:09:08 2006//
-// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005//
-// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005//
-// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X128_H
-#define AT91SAM7X128_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
-#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
-#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
-#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_CAN (15) // Control Area Network Controller
-#define AT91C_ID_EMAC (16) // Ethernet MAC
-#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00020000) // Internal FLASH size in byte (128 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (512) // Internal FLASH Number of Pages: 512 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h deleted file mode 100644 index 20b0e747d..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X256.h +++ /dev/null @@ -1,2918 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the disclaimer below in the documentation and/or
-// other materials provided with the distribution.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7X256.h
-// Object : AT91SAM7X256 definitions
-// Generated : AT91 SW Application Group 06/19/2007 (15:41:06)
-//
-// CVS Reference : /AT91SAM7X256.pl/1.16/Wed Aug 30 14:16:22 2006//
-// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005//
-// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005//
-// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 14:20:52 2006//
-// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
-// CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[21]; //
- AT91_REG MC_FMR; // MC Flash Mode Register
- AT91_REG MC_FCR; // MC Flash Command Register
- AT91_REG MC_FSR; // MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000060) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000068) // (MC_FSR) MC Flash Status Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
-#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
-#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
-#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_CAN (15) // Control Area Network Controller
-#define AT91C_ID_EMAC (16) // Ethernet MAC
-#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00010000) // Internal SRAM size in byte (64 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00040000) // Internal FLASH size in byte (256 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH Number of Pages: 1024 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH Number of Lock Bits: 16 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h b/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h deleted file mode 100644 index 7c03a0db4..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/AT91SAM7X512.h +++ /dev/null @@ -1,2984 +0,0 @@ -// ----------------------------------------------------------------------------
-// ATMEL Microcontroller Software Support - ROUSSET -
-// ----------------------------------------------------------------------------
-// Copyright (c) 2006, Atmel Corporation
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the disclaimer below.
-//
-// Atmel's name may not be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ----------------------------------------------------------------------------
-// File Name : AT91SAM7X512.h
-// Object : AT91SAM7X512 definitions
-// Generated : AT91 SW Application Group 07/07/2008 (16:15:41)
-//
-// CVS Reference : /AT91SAM7X512.pl/1.7/Wed Aug 30 14:09:17 2006//
-// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005//
-// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006//
-// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005//
-// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
-// CVS Reference : /UDP_6ept.pl/1.1/Wed Aug 30 10:56:49 2006//
-// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
-// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
-// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
-// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
-// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
-// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
-// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
-// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
-// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
-// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
-// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
-// CVS Reference : /SSC_6078B.pl/1.2/Wed Apr 16 08:28:18 2008//
-// CVS Reference : /TWI_6061A.pl/1.2/Fri Oct 27 11:40:48 2006//
-// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
-// CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
-// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
-// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X512_H
-#define AT91SAM7X512_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-#define AT91_CAST(a) (a)
-#else
-#define AT91_CAST(a)
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR System Peripherals
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SYS {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
- AT91_REG Reserved2[45]; //
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved3[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved4[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
- AT91_REG Reserved5[54]; //
- AT91_REG PIOA_PER; // PIO Enable Register
- AT91_REG PIOA_PDR; // PIO Disable Register
- AT91_REG PIOA_PSR; // PIO Status Register
- AT91_REG Reserved6[1]; //
- AT91_REG PIOA_OER; // Output Enable Register
- AT91_REG PIOA_ODR; // Output Disable Registerr
- AT91_REG PIOA_OSR; // Output Status Register
- AT91_REG Reserved7[1]; //
- AT91_REG PIOA_IFER; // Input Filter Enable Register
- AT91_REG PIOA_IFDR; // Input Filter Disable Register
- AT91_REG PIOA_IFSR; // Input Filter Status Register
- AT91_REG Reserved8[1]; //
- AT91_REG PIOA_SODR; // Set Output Data Register
- AT91_REG PIOA_CODR; // Clear Output Data Register
- AT91_REG PIOA_ODSR; // Output Data Status Register
- AT91_REG PIOA_PDSR; // Pin Data Status Register
- AT91_REG PIOA_IER; // Interrupt Enable Register
- AT91_REG PIOA_IDR; // Interrupt Disable Register
- AT91_REG PIOA_IMR; // Interrupt Mask Register
- AT91_REG PIOA_ISR; // Interrupt Status Register
- AT91_REG PIOA_MDER; // Multi-driver Enable Register
- AT91_REG PIOA_MDDR; // Multi-driver Disable Register
- AT91_REG PIOA_MDSR; // Multi-driver Status Register
- AT91_REG Reserved9[1]; //
- AT91_REG PIOA_PPUDR; // Pull-up Disable Register
- AT91_REG PIOA_PPUER; // Pull-up Enable Register
- AT91_REG PIOA_PPUSR; // Pull-up Status Register
- AT91_REG Reserved10[1]; //
- AT91_REG PIOA_ASR; // Select A Register
- AT91_REG PIOA_BSR; // Select B Register
- AT91_REG PIOA_ABSR; // AB Select Status Register
- AT91_REG Reserved11[9]; //
- AT91_REG PIOA_OWER; // Output Write Enable Register
- AT91_REG PIOA_OWDR; // Output Write Disable Register
- AT91_REG PIOA_OWSR; // Output Write Status Register
- AT91_REG Reserved12[85]; //
- AT91_REG PIOB_PER; // PIO Enable Register
- AT91_REG PIOB_PDR; // PIO Disable Register
- AT91_REG PIOB_PSR; // PIO Status Register
- AT91_REG Reserved13[1]; //
- AT91_REG PIOB_OER; // Output Enable Register
- AT91_REG PIOB_ODR; // Output Disable Registerr
- AT91_REG PIOB_OSR; // Output Status Register
- AT91_REG Reserved14[1]; //
- AT91_REG PIOB_IFER; // Input Filter Enable Register
- AT91_REG PIOB_IFDR; // Input Filter Disable Register
- AT91_REG PIOB_IFSR; // Input Filter Status Register
- AT91_REG Reserved15[1]; //
- AT91_REG PIOB_SODR; // Set Output Data Register
- AT91_REG PIOB_CODR; // Clear Output Data Register
- AT91_REG PIOB_ODSR; // Output Data Status Register
- AT91_REG PIOB_PDSR; // Pin Data Status Register
- AT91_REG PIOB_IER; // Interrupt Enable Register
- AT91_REG PIOB_IDR; // Interrupt Disable Register
- AT91_REG PIOB_IMR; // Interrupt Mask Register
- AT91_REG PIOB_ISR; // Interrupt Status Register
- AT91_REG PIOB_MDER; // Multi-driver Enable Register
- AT91_REG PIOB_MDDR; // Multi-driver Disable Register
- AT91_REG PIOB_MDSR; // Multi-driver Status Register
- AT91_REG Reserved16[1]; //
- AT91_REG PIOB_PPUDR; // Pull-up Disable Register
- AT91_REG PIOB_PPUER; // Pull-up Enable Register
- AT91_REG PIOB_PPUSR; // Pull-up Status Register
- AT91_REG Reserved17[1]; //
- AT91_REG PIOB_ASR; // Select A Register
- AT91_REG PIOB_BSR; // Select B Register
- AT91_REG PIOB_ABSR; // AB Select Status Register
- AT91_REG Reserved18[9]; //
- AT91_REG PIOB_OWER; // Output Write Enable Register
- AT91_REG PIOB_OWDR; // Output Write Disable Register
- AT91_REG PIOB_OWSR; // Output Write Status Register
- AT91_REG Reserved19[341]; //
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved20[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved21[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved22[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved23[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved24[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
- AT91_REG Reserved25[36]; //
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
- AT91_REG Reserved26[5]; //
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
- AT91_REG Reserved27[5]; //
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-#else
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_AIC {
- AT91_REG AIC_SMR[32]; // Source Mode Register
- AT91_REG AIC_SVR[32]; // Source Vector Register
- AT91_REG AIC_IVR; // IRQ Vector Register
- AT91_REG AIC_FVR; // FIQ Vector Register
- AT91_REG AIC_ISR; // Interrupt Status Register
- AT91_REG AIC_IPR; // Interrupt Pending Register
- AT91_REG AIC_IMR; // Interrupt Mask Register
- AT91_REG AIC_CISR; // Core Interrupt Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG AIC_IECR; // Interrupt Enable Command Register
- AT91_REG AIC_IDCR; // Interrupt Disable Command Register
- AT91_REG AIC_ICCR; // Interrupt Clear Command Register
- AT91_REG AIC_ISCR; // Interrupt Set Command Register
- AT91_REG AIC_EOICR; // End of Interrupt Command Register
- AT91_REG AIC_SPU; // Spurious Vector Register
- AT91_REG AIC_DCR; // Debug Control Register (Protect)
- AT91_REG Reserved1[1]; //
- AT91_REG AIC_FFER; // Fast Forcing Enable Register
- AT91_REG AIC_FFDR; // Fast Forcing Disable Register
- AT91_REG AIC_FFSR; // Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-#else
-#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
-#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
-#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
-#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
-#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
-#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
-#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
-#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
-#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
-#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
-#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
-#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
-#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
-#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
-#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
-#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
-#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
-#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
-
-#endif
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
-#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
-#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
-#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
-#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
-#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PDC {
- AT91_REG PDC_RPR; // Receive Pointer Register
- AT91_REG PDC_RCR; // Receive Counter Register
- AT91_REG PDC_TPR; // Transmit Pointer Register
- AT91_REG PDC_TCR; // Transmit Counter Register
- AT91_REG PDC_RNPR; // Receive Next Pointer Register
- AT91_REG PDC_RNCR; // Receive Next Counter Register
- AT91_REG PDC_TNPR; // Transmit Next Pointer Register
- AT91_REG PDC_TNCR; // Transmit Next Counter Register
- AT91_REG PDC_PTCR; // PDC Transfer Control Register
- AT91_REG PDC_PTSR; // PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-#else
-#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
-#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
-#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
-#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
-#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
-#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
-#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
-#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
-#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
-#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
-
-#endif
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Debug Unit
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_DBGU {
- AT91_REG DBGU_CR; // Control Register
- AT91_REG DBGU_MR; // Mode Register
- AT91_REG DBGU_IER; // Interrupt Enable Register
- AT91_REG DBGU_IDR; // Interrupt Disable Register
- AT91_REG DBGU_IMR; // Interrupt Mask Register
- AT91_REG DBGU_CSR; // Channel Status Register
- AT91_REG DBGU_RHR; // Receiver Holding Register
- AT91_REG DBGU_THR; // Transmitter Holding Register
- AT91_REG DBGU_BRGR; // Baud Rate Generator Register
- AT91_REG Reserved0[7]; //
- AT91_REG DBGU_CIDR; // Chip ID Register
- AT91_REG DBGU_EXID; // Chip ID Extension Register
- AT91_REG DBGU_FNTR; // Force NTRST Register
- AT91_REG Reserved1[45]; //
- AT91_REG DBGU_RPR; // Receive Pointer Register
- AT91_REG DBGU_RCR; // Receive Counter Register
- AT91_REG DBGU_TPR; // Transmit Pointer Register
- AT91_REG DBGU_TCR; // Transmit Counter Register
- AT91_REG DBGU_RNPR; // Receive Next Pointer Register
- AT91_REG DBGU_RNCR; // Receive Next Counter Register
- AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
- AT91_REG DBGU_TNCR; // Transmit Next Counter Register
- AT91_REG DBGU_PTCR; // PDC Transfer Control Register
- AT91_REG DBGU_PTSR; // PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-#else
-#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
-#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
-#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
-#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
-#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
-#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
-#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
-#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
-#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
-#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
-#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
-#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
-
-#endif
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
-#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
-#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
-#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
-#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
-#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
-#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
-#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PIO {
- AT91_REG PIO_PER; // PIO Enable Register
- AT91_REG PIO_PDR; // PIO Disable Register
- AT91_REG PIO_PSR; // PIO Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PIO_OER; // Output Enable Register
- AT91_REG PIO_ODR; // Output Disable Registerr
- AT91_REG PIO_OSR; // Output Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PIO_IFER; // Input Filter Enable Register
- AT91_REG PIO_IFDR; // Input Filter Disable Register
- AT91_REG PIO_IFSR; // Input Filter Status Register
- AT91_REG Reserved2[1]; //
- AT91_REG PIO_SODR; // Set Output Data Register
- AT91_REG PIO_CODR; // Clear Output Data Register
- AT91_REG PIO_ODSR; // Output Data Status Register
- AT91_REG PIO_PDSR; // Pin Data Status Register
- AT91_REG PIO_IER; // Interrupt Enable Register
- AT91_REG PIO_IDR; // Interrupt Disable Register
- AT91_REG PIO_IMR; // Interrupt Mask Register
- AT91_REG PIO_ISR; // Interrupt Status Register
- AT91_REG PIO_MDER; // Multi-driver Enable Register
- AT91_REG PIO_MDDR; // Multi-driver Disable Register
- AT91_REG PIO_MDSR; // Multi-driver Status Register
- AT91_REG Reserved3[1]; //
- AT91_REG PIO_PPUDR; // Pull-up Disable Register
- AT91_REG PIO_PPUER; // Pull-up Enable Register
- AT91_REG PIO_PPUSR; // Pull-up Status Register
- AT91_REG Reserved4[1]; //
- AT91_REG PIO_ASR; // Select A Register
- AT91_REG PIO_BSR; // Select B Register
- AT91_REG PIO_ABSR; // AB Select Status Register
- AT91_REG Reserved5[9]; //
- AT91_REG PIO_OWER; // Output Write Enable Register
- AT91_REG PIO_OWDR; // Output Write Disable Register
- AT91_REG PIO_OWSR; // Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-#else
-#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
-#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
-#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
-#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
-#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
-#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
-#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
-#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
-#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
-#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
-#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
-#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
-#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
-#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
-#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
-#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
-#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
-#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
-#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
-#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
-#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
-#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
-#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
-#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
-#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
-#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
-#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
-#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
-#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
-
-#endif
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Clock Generator Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CKGR {
- AT91_REG CKGR_MOR; // Main Oscillator Register
- AT91_REG CKGR_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved0[1]; //
- AT91_REG CKGR_PLLR; // PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-#else
-#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
-#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
-#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register
-
-#endif
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
-#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
-#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Power Management Controler
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PMC {
- AT91_REG PMC_SCER; // System Clock Enable Register
- AT91_REG PMC_SCDR; // System Clock Disable Register
- AT91_REG PMC_SCSR; // System Clock Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG PMC_PCER; // Peripheral Clock Enable Register
- AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
- AT91_REG PMC_PCSR; // Peripheral Clock Status Register
- AT91_REG Reserved1[1]; //
- AT91_REG PMC_MOR; // Main Oscillator Register
- AT91_REG PMC_MCFR; // Main Clock Frequency Register
- AT91_REG Reserved2[1]; //
- AT91_REG PMC_PLLR; // PLL Register
- AT91_REG PMC_MCKR; // Master Clock Register
- AT91_REG Reserved3[3]; //
- AT91_REG PMC_PCKR[4]; // Programmable Clock Register
- AT91_REG Reserved4[4]; //
- AT91_REG PMC_IER; // Interrupt Enable Register
- AT91_REG PMC_IDR; // Interrupt Disable Register
- AT91_REG PMC_SR; // Status Register
- AT91_REG PMC_IMR; // Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-#else
-#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
-#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
-#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
-#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
-#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
-#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
-#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
-#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
-#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
-#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
-#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
-#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
-
-#endif
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
-#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
-#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
-#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
-#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
-#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
-#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
-#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
-#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
-#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
-#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Reset Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RSTC {
- AT91_REG RSTC_RCR; // Reset Control Register
- AT91_REG RSTC_RSR; // Reset Status Register
- AT91_REG RSTC_RMR; // Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-#else
-#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
-#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
-#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
-
-#endif
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
-#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
-#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
-#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
-#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_RTTC {
- AT91_REG RTTC_RTMR; // Real-time Mode Register
- AT91_REG RTTC_RTAR; // Real-time Alarm Register
- AT91_REG RTTC_RTVR; // Real-time Value Register
- AT91_REG RTTC_RTSR; // Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-#else
-#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
-#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
-#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
-#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
-
-#endif
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PITC {
- AT91_REG PITC_PIMR; // Period Interval Mode Register
- AT91_REG PITC_PISR; // Period Interval Status Register
- AT91_REG PITC_PIVR; // Period Interval Value Register
- AT91_REG PITC_PIIR; // Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-#else
-#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
-#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
-#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
-#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
-
-#endif
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_WDTC {
- AT91_REG WDTC_WDCR; // Watchdog Control Register
- AT91_REG WDTC_WDMR; // Watchdog Mode Register
- AT91_REG WDTC_WDSR; // Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-#else
-#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
-#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
-#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
-
-#endif
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_VREG {
- AT91_REG VREG_MR; // Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-#else
-#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register
-
-#endif
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EFC {
- AT91_REG EFC_FMR; // MC Flash Mode Register
- AT91_REG EFC_FCR; // MC Flash Command Register
- AT91_REG EFC_FSR; // MC Flash Status Register
- AT91_REG EFC_VR; // MC Flash Version Register
-} AT91S_EFC, *AT91PS_EFC;
-#else
-#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register
-#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register
-#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register
-#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register
-
-#endif
-// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register --------
-#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready
-#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error
-#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error
-#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming
-#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State
-#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations
-#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations
-#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations
-#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register --------
-#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command
-#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN.
-#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed.
-#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits.
-#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits.
-#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit.
-#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number
-#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key
-// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register --------
-#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status
-#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status
-// -------- EFC_VR : (EFC Offset: 0xc) EFC version register --------
-#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number
-#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Memory Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_MC {
- AT91_REG MC_RCR; // MC Remap Control Register
- AT91_REG MC_ASR; // MC Abort Status Register
- AT91_REG MC_AASR; // MC Abort Address Status Register
- AT91_REG Reserved0[1]; //
- AT91_REG MC_PUIA[16]; // MC Protection Unit Area
- AT91_REG MC_PUP; // MC Protection Unit Peripherals
- AT91_REG MC_PUER; // MC Protection Unit Enable Register
- AT91_REG Reserved1[2]; //
- AT91_REG MC0_FMR; // MC Flash Mode Register
- AT91_REG MC0_FCR; // MC Flash Command Register
- AT91_REG MC0_FSR; // MC Flash Status Register
- AT91_REG MC0_VR; // MC Flash Version Register
- AT91_REG MC1_FMR; // MC Flash Mode Register
- AT91_REG MC1_FCR; // MC Flash Command Register
- AT91_REG MC1_FSR; // MC Flash Status Register
- AT91_REG MC1_VR; // MC Flash Version Register
-} AT91S_MC, *AT91PS_MC;
-#else
-#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register
-#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register
-#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register
-#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area
-#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals
-#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register
-
-#endif
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status
-#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
-#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
-#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
-#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
-#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
-#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
-#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
-#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
-#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection
-#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access
-#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access
-#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only
-#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write
-#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size
-#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte
-#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte
-#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte
-#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte
-#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte
-#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte
-#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte
-#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte
-#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte
-#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte
-#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte
-#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte
-#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte
-#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte
-#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte
-#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte
-#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address
-// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
-// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
-#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Serial Parallel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SPI {
- AT91_REG SPI_CR; // Control Register
- AT91_REG SPI_MR; // Mode Register
- AT91_REG SPI_RDR; // Receive Data Register
- AT91_REG SPI_TDR; // Transmit Data Register
- AT91_REG SPI_SR; // Status Register
- AT91_REG SPI_IER; // Interrupt Enable Register
- AT91_REG SPI_IDR; // Interrupt Disable Register
- AT91_REG SPI_IMR; // Interrupt Mask Register
- AT91_REG Reserved0[4]; //
- AT91_REG SPI_CSR[4]; // Chip Select Register
- AT91_REG Reserved1[48]; //
- AT91_REG SPI_RPR; // Receive Pointer Register
- AT91_REG SPI_RCR; // Receive Counter Register
- AT91_REG SPI_TPR; // Transmit Pointer Register
- AT91_REG SPI_TCR; // Transmit Counter Register
- AT91_REG SPI_RNPR; // Receive Next Pointer Register
- AT91_REG SPI_RNCR; // Receive Next Counter Register
- AT91_REG SPI_TNPR; // Transmit Next Pointer Register
- AT91_REG SPI_TNCR; // Transmit Next Counter Register
- AT91_REG SPI_PTCR; // PDC Transfer Control Register
- AT91_REG SPI_PTSR; // PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-#else
-#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
-#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
-#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
-#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
-#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
-#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
-#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
-#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
-#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
-
-#endif
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
-#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
-#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
-#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
-#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
-#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
-#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
-#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
-#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
-#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
-#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
-#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Usart
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_USART {
- AT91_REG US_CR; // Control Register
- AT91_REG US_MR; // Mode Register
- AT91_REG US_IER; // Interrupt Enable Register
- AT91_REG US_IDR; // Interrupt Disable Register
- AT91_REG US_IMR; // Interrupt Mask Register
- AT91_REG US_CSR; // Channel Status Register
- AT91_REG US_RHR; // Receiver Holding Register
- AT91_REG US_THR; // Transmitter Holding Register
- AT91_REG US_BRGR; // Baud Rate Generator Register
- AT91_REG US_RTOR; // Receiver Time-out Register
- AT91_REG US_TTGR; // Transmitter Time-guard Register
- AT91_REG Reserved0[5]; //
- AT91_REG US_FIDI; // FI_DI_Ratio Register
- AT91_REG US_NER; // Nb Errors Register
- AT91_REG Reserved1[1]; //
- AT91_REG US_IF; // IRDA_FILTER Register
- AT91_REG Reserved2[44]; //
- AT91_REG US_RPR; // Receive Pointer Register
- AT91_REG US_RCR; // Receive Counter Register
- AT91_REG US_TPR; // Transmit Pointer Register
- AT91_REG US_TCR; // Transmit Counter Register
- AT91_REG US_RNPR; // Receive Next Pointer Register
- AT91_REG US_RNCR; // Receive Next Counter Register
- AT91_REG US_TNPR; // Transmit Next Pointer Register
- AT91_REG US_TNCR; // Transmit Next Counter Register
- AT91_REG US_PTCR; // PDC Transfer Control Register
- AT91_REG US_PTSR; // PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-#else
-#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
-#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
-#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
-#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
-#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
-#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
-#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
-#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
-#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
-#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
-#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
-#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
-#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
-#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
-
-#endif
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
-#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
-#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
-#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
-#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
-#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
-#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
-#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
-#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
-#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
-#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
-#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
-#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
-#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
-#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
-#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
-#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
-#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
-#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_SSC {
- AT91_REG SSC_CR; // Control Register
- AT91_REG SSC_CMR; // Clock Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG SSC_RCMR; // Receive Clock ModeRegister
- AT91_REG SSC_RFMR; // Receive Frame Mode Register
- AT91_REG SSC_TCMR; // Transmit Clock Mode Register
- AT91_REG SSC_TFMR; // Transmit Frame Mode Register
- AT91_REG SSC_RHR; // Receive Holding Register
- AT91_REG SSC_THR; // Transmit Holding Register
- AT91_REG Reserved1[2]; //
- AT91_REG SSC_RSHR; // Receive Sync Holding Register
- AT91_REG SSC_TSHR; // Transmit Sync Holding Register
- AT91_REG Reserved2[2]; //
- AT91_REG SSC_SR; // Status Register
- AT91_REG SSC_IER; // Interrupt Enable Register
- AT91_REG SSC_IDR; // Interrupt Disable Register
- AT91_REG SSC_IMR; // Interrupt Mask Register
- AT91_REG Reserved3[44]; //
- AT91_REG SSC_RPR; // Receive Pointer Register
- AT91_REG SSC_RCR; // Receive Counter Register
- AT91_REG SSC_TPR; // Transmit Pointer Register
- AT91_REG SSC_TCR; // Transmit Counter Register
- AT91_REG SSC_RNPR; // Receive Next Pointer Register
- AT91_REG SSC_RNCR; // Receive Next Counter Register
- AT91_REG SSC_TNPR; // Transmit Next Pointer Register
- AT91_REG SSC_TNCR; // Transmit Next Counter Register
- AT91_REG SSC_PTCR; // PDC Transfer Control Register
- AT91_REG SSC_PTSR; // PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-#else
-#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
-#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
-#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
-#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
-#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
-#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
-#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
-#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
-#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
-#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
-#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
-#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
-#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
-#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
-
-#endif
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
-#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
-#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
-#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
-#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
-#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
-#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
-#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
-#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
-#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
-#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
-#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
-#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
-#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
-#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
-#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Two-wire Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TWI {
- AT91_REG TWI_CR; // Control Register
- AT91_REG TWI_MMR; // Master Mode Register
- AT91_REG Reserved0[1]; //
- AT91_REG TWI_IADR; // Internal Address Register
- AT91_REG TWI_CWGR; // Clock Waveform Generator Register
- AT91_REG Reserved1[3]; //
- AT91_REG TWI_SR; // Status Register
- AT91_REG TWI_IER; // Interrupt Enable Register
- AT91_REG TWI_IDR; // Interrupt Disable Register
- AT91_REG TWI_IMR; // Interrupt Mask Register
- AT91_REG TWI_RHR; // Receive Holding Register
- AT91_REG TWI_THR; // Transmit Holding Register
- AT91_REG Reserved2[50]; //
- AT91_REG TWI_RPR; // Receive Pointer Register
- AT91_REG TWI_RCR; // Receive Counter Register
- AT91_REG TWI_TPR; // Transmit Pointer Register
- AT91_REG TWI_TCR; // Transmit Counter Register
- AT91_REG TWI_RNPR; // Receive Next Pointer Register
- AT91_REG TWI_RNCR; // Receive Next Counter Register
- AT91_REG TWI_TNPR; // Transmit Next Pointer Register
- AT91_REG TWI_TNCR; // Transmit Next Counter Register
- AT91_REG TWI_PTCR; // PDC Transfer Control Register
- AT91_REG TWI_PTSR; // PDC Transfer Status Register
-} AT91S_TWI, *AT91PS_TWI;
-#else
-#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
-#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
-#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
-#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
-#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
-#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
-#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
-#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
-#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
-#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
-
-#endif
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
-#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
-#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
-#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
-#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI)
-#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI)
-#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI)
-#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI)
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR PWMC Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC_CH {
- AT91_REG PWMC_CMR; // Channel Mode Register
- AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register
- AT91_REG PWMC_CPRDR; // Channel Period Register
- AT91_REG PWMC_CCNTR; // Channel Counter Register
- AT91_REG PWMC_CUPDR; // Channel Update Register
- AT91_REG PWMC_Reserved[3]; // Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-#else
-#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register
-#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register
-#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register
-#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register
-#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register
-#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved
-
-#endif
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
-#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
-#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_PWMC {
- AT91_REG PWMC_MR; // PWMC Mode Register
- AT91_REG PWMC_ENA; // PWMC Enable Register
- AT91_REG PWMC_DIS; // PWMC Disable Register
- AT91_REG PWMC_SR; // PWMC Status Register
- AT91_REG PWMC_IER; // PWMC Interrupt Enable Register
- AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register
- AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register
- AT91_REG PWMC_ISR; // PWMC Interrupt Status Register
- AT91_REG Reserved0[55]; //
- AT91_REG PWMC_VR; // PWMC Version Register
- AT91_REG Reserved1[64]; //
- AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-#else
-#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register
-#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register
-#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register
-#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register
-#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register
-#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register
-#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register
-#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register
-#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register
-
-#endif
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
-#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
-#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR USB Device Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_UDP {
- AT91_REG UDP_NUM; // Frame Number Register
- AT91_REG UDP_GLBSTATE; // Global State Register
- AT91_REG UDP_FADDR; // Function Address Register
- AT91_REG Reserved0[1]; //
- AT91_REG UDP_IER; // Interrupt Enable Register
- AT91_REG UDP_IDR; // Interrupt Disable Register
- AT91_REG UDP_IMR; // Interrupt Mask Register
- AT91_REG UDP_ISR; // Interrupt Status Register
- AT91_REG UDP_ICR; // Interrupt Clear Register
- AT91_REG Reserved1[1]; //
- AT91_REG UDP_RSTEP; // Reset Endpoint Register
- AT91_REG Reserved2[1]; //
- AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
- AT91_REG Reserved3[2]; //
- AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
- AT91_REG Reserved4[3]; //
- AT91_REG UDP_TXVC; // Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-#else
-#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
-#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
-#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
-#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
-#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
-#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
-#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
-#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
-#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
-#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
-#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
-#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
-
-#endif
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
-#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
-#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
-#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
-#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
-#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
-#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
-#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
-#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
-#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TC {
- AT91_REG TC_CCR; // Channel Control Register
- AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
- AT91_REG Reserved0[2]; //
- AT91_REG TC_CV; // Counter Value
- AT91_REG TC_RA; // Register A
- AT91_REG TC_RB; // Register B
- AT91_REG TC_RC; // Register C
- AT91_REG TC_SR; // Status Register
- AT91_REG TC_IER; // Interrupt Enable Register
- AT91_REG TC_IDR; // Interrupt Disable Register
- AT91_REG TC_IMR; // Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-#else
-#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
-#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
-#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
-#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
-#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
-#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
-#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
-#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
-#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
-
-#endif
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
-#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
-#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
-#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
-#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
-#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
-#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
-#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
-#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
-#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
-#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
-#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
-#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
-#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
-#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE (0x1 << 15) // (TC)
-#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
-#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
-#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
-#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
-#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
-#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
-#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
-#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
-#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
-#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
-#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
-#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
-#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
-#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
-#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
-#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
-#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
-#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
-#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
-#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
-#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
-#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
-#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
-#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
-#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
-#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
-#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
-#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
-#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
-#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
-#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
-#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
-#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
-#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
-#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
-#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
-#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Timer Counter Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_TCB {
- AT91S_TC TCB_TC0; // TC Channel 0
- AT91_REG Reserved0[4]; //
- AT91S_TC TCB_TC1; // TC Channel 1
- AT91_REG Reserved1[4]; //
- AT91S_TC TCB_TC2; // TC Channel 2
- AT91_REG Reserved2[4]; //
- AT91_REG TCB_BCR; // TC Block Control Register
- AT91_REG TCB_BMR; // TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-#else
-#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
-#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
-
-#endif
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
-#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
-#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
-#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
-#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
-#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
-#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
-#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
-#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
-#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN_MB {
- AT91_REG CAN_MB_MMR; // MailBox Mode Register
- AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register
- AT91_REG CAN_MB_MID; // MailBox ID Register
- AT91_REG CAN_MB_MFID; // MailBox Family ID Register
- AT91_REG CAN_MB_MSR; // MailBox Status Register
- AT91_REG CAN_MB_MDL; // MailBox Data Low Register
- AT91_REG CAN_MB_MDH; // MailBox Data High Register
- AT91_REG CAN_MB_MCR; // MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-#else
-#define CAN_MMR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MMR) MailBox Mode Register
-#define CAN_MAM (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_MAM) MailBox Acceptance Mask Register
-#define CAN_MID (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_MID) MailBox ID Register
-#define CAN_MFID (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_MFID) MailBox Family ID Register
-#define CAN_MSR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_MSR) MailBox Status Register
-#define CAN_MDL (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_MDL) MailBox Data Low Register
-#define CAN_MDH (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_MDH) MailBox Data High Register
-#define CAN_MCR (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_MCR) MailBox Control Register
-
-#endif
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
-#define AT91C_CAN_MTIMEMARK (0xFFFF << 0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define AT91C_CAN_MOT_DIS (0x0 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RX (0x1 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_RXOVERWRITE (0x2 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_TX (0x3 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_CONSUMER (0x4 << 24) // (CAN_MB)
-#define AT91C_CAN_MOT_PRODUCER (0x5 << 24) // (CAN_MB)
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
-#define AT91C_CAN_MIDvB (0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
-#define AT91C_CAN_MTIMESTAMP (0xFFFF << 0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
-#define AT91C_CAN_MACR (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Control Area Network Interface
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_CAN {
- AT91_REG CAN_MR; // Mode Register
- AT91_REG CAN_IER; // Interrupt Enable Register
- AT91_REG CAN_IDR; // Interrupt Disable Register
- AT91_REG CAN_IMR; // Interrupt Mask Register
- AT91_REG CAN_SR; // Status Register
- AT91_REG CAN_BR; // Baudrate Register
- AT91_REG CAN_TIM; // Timer Register
- AT91_REG CAN_TIMESTP; // Time Stamp Register
- AT91_REG CAN_ECR; // Error Counter Register
- AT91_REG CAN_TCR; // Transfer Command Register
- AT91_REG CAN_ACR; // Abort Command Register
- AT91_REG Reserved0[52]; //
- AT91_REG CAN_VR; // Version Register
- AT91_REG Reserved1[64]; //
- AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0
- AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1
- AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2
- AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3
- AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4
- AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5
- AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6
- AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7
- AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8
- AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9
- AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10
- AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11
- AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12
- AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13
- AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14
- AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-#else
-#define CAN_MR (AT91_CAST(AT91_REG *) 0x00000000) // (CAN_MR) Mode Register
-#define CAN_IER (AT91_CAST(AT91_REG *) 0x00000004) // (CAN_IER) Interrupt Enable Register
-#define CAN_IDR (AT91_CAST(AT91_REG *) 0x00000008) // (CAN_IDR) Interrupt Disable Register
-#define CAN_IMR (AT91_CAST(AT91_REG *) 0x0000000C) // (CAN_IMR) Interrupt Mask Register
-#define CAN_SR (AT91_CAST(AT91_REG *) 0x00000010) // (CAN_SR) Status Register
-#define CAN_BR (AT91_CAST(AT91_REG *) 0x00000014) // (CAN_BR) Baudrate Register
-#define CAN_TIM (AT91_CAST(AT91_REG *) 0x00000018) // (CAN_TIM) Timer Register
-#define CAN_TIMESTP (AT91_CAST(AT91_REG *) 0x0000001C) // (CAN_TIMESTP) Time Stamp Register
-#define CAN_ECR (AT91_CAST(AT91_REG *) 0x00000020) // (CAN_ECR) Error Counter Register
-#define CAN_TCR (AT91_CAST(AT91_REG *) 0x00000024) // (CAN_TCR) Transfer Command Register
-#define CAN_ACR (AT91_CAST(AT91_REG *) 0x00000028) // (CAN_ACR) Abort Command Register
-#define CAN_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (CAN_VR) Version Register
-
-#endif
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register --------
-#define AT91C_CAN_CANEN (0x1 << 0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM (0x1 << 1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM (0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL (0x1 << 3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF (0x1 << 4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM (0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ (0x1 << 6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT (0x1 << 7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register --------
-#define AT91C_CAN_MB0 (0x1 << 0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1 (0x1 << 1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2 (0x1 << 2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3 (0x1 << 3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4 (0x1 << 4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5 (0x1 << 5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6 (0x1 << 6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7 (0x1 << 7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8 (0x1 << 8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9 (0x1 << 9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10 (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11 (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12 (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13 (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14 (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15 (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register --------
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register --------
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register --------
-#define AT91C_CAN_RBSY (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register --------
-#define AT91C_CAN_PHASE2 (0x7 << 0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1 (0x7 << 4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG (0x7 << 8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register --------
-#define AT91C_CAN_TIMER (0xFFFF << 0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register --------
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register --------
-#define AT91C_CAN_REC (0xFF << 0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register --------
-#define AT91C_CAN_TIMRST (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register --------
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_EMAC {
- AT91_REG EMAC_NCR; // Network Control Register
- AT91_REG EMAC_NCFGR; // Network Configuration Register
- AT91_REG EMAC_NSR; // Network Status Register
- AT91_REG Reserved0[2]; //
- AT91_REG EMAC_TSR; // Transmit Status Register
- AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
- AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer
- AT91_REG EMAC_RSR; // Receive Status Register
- AT91_REG EMAC_ISR; // Interrupt Status Register
- AT91_REG EMAC_IER; // Interrupt Enable Register
- AT91_REG EMAC_IDR; // Interrupt Disable Register
- AT91_REG EMAC_IMR; // Interrupt Mask Register
- AT91_REG EMAC_MAN; // PHY Maintenance Register
- AT91_REG EMAC_PTR; // Pause Time Register
- AT91_REG EMAC_PFR; // Pause Frames received Register
- AT91_REG EMAC_FTO; // Frames Transmitted OK Register
- AT91_REG EMAC_SCF; // Single Collision Frame Register
- AT91_REG EMAC_MCF; // Multiple Collision Frame Register
- AT91_REG EMAC_FRO; // Frames Received OK Register
- AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register
- AT91_REG EMAC_ALE; // Alignment Error Register
- AT91_REG EMAC_DTF; // Deferred Transmission Frame Register
- AT91_REG EMAC_LCOL; // Late Collision Register
- AT91_REG EMAC_ECOL; // Excessive Collision Register
- AT91_REG EMAC_TUND; // Transmit Underrun Error Register
- AT91_REG EMAC_CSE; // Carrier Sense Error Register
- AT91_REG EMAC_RRE; // Receive Ressource Error Register
- AT91_REG EMAC_ROV; // Receive Overrun Errors Register
- AT91_REG EMAC_RSE; // Receive Symbol Errors Register
- AT91_REG EMAC_ELE; // Excessive Length Errors Register
- AT91_REG EMAC_RJA; // Receive Jabbers Register
- AT91_REG EMAC_USF; // Undersize Frames Register
- AT91_REG EMAC_STE; // SQE Test Error Register
- AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register
- AT91_REG EMAC_TPF; // Transmitted Pause Frames Register
- AT91_REG EMAC_HRB; // Hash Address Bottom[31:0]
- AT91_REG EMAC_HRT; // Hash Address Top[63:32]
- AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes
- AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes
- AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes
- AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes
- AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes
- AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes
- AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes
- AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes
- AT91_REG EMAC_TID; // Type ID Checking Register
- AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register
- AT91_REG EMAC_USRIO; // USER Input/Output Register
- AT91_REG EMAC_WOL; // Wake On LAN Register
- AT91_REG Reserved1[13]; //
- AT91_REG EMAC_REV; // Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-#else
-#define EMAC_NCR (AT91_CAST(AT91_REG *) 0x00000000) // (EMAC_NCR) Network Control Register
-#define EMAC_NCFGR (AT91_CAST(AT91_REG *) 0x00000004) // (EMAC_NCFGR) Network Configuration Register
-#define EMAC_NSR (AT91_CAST(AT91_REG *) 0x00000008) // (EMAC_NSR) Network Status Register
-#define EMAC_TSR (AT91_CAST(AT91_REG *) 0x00000014) // (EMAC_TSR) Transmit Status Register
-#define EMAC_RBQP (AT91_CAST(AT91_REG *) 0x00000018) // (EMAC_RBQP) Receive Buffer Queue Pointer
-#define EMAC_TBQP (AT91_CAST(AT91_REG *) 0x0000001C) // (EMAC_TBQP) Transmit Buffer Queue Pointer
-#define EMAC_RSR (AT91_CAST(AT91_REG *) 0x00000020) // (EMAC_RSR) Receive Status Register
-#define EMAC_ISR (AT91_CAST(AT91_REG *) 0x00000024) // (EMAC_ISR) Interrupt Status Register
-#define EMAC_IER (AT91_CAST(AT91_REG *) 0x00000028) // (EMAC_IER) Interrupt Enable Register
-#define EMAC_IDR (AT91_CAST(AT91_REG *) 0x0000002C) // (EMAC_IDR) Interrupt Disable Register
-#define EMAC_IMR (AT91_CAST(AT91_REG *) 0x00000030) // (EMAC_IMR) Interrupt Mask Register
-#define EMAC_MAN (AT91_CAST(AT91_REG *) 0x00000034) // (EMAC_MAN) PHY Maintenance Register
-#define EMAC_PTR (AT91_CAST(AT91_REG *) 0x00000038) // (EMAC_PTR) Pause Time Register
-#define EMAC_PFR (AT91_CAST(AT91_REG *) 0x0000003C) // (EMAC_PFR) Pause Frames received Register
-#define EMAC_FTO (AT91_CAST(AT91_REG *) 0x00000040) // (EMAC_FTO) Frames Transmitted OK Register
-#define EMAC_SCF (AT91_CAST(AT91_REG *) 0x00000044) // (EMAC_SCF) Single Collision Frame Register
-#define EMAC_MCF (AT91_CAST(AT91_REG *) 0x00000048) // (EMAC_MCF) Multiple Collision Frame Register
-#define EMAC_FRO (AT91_CAST(AT91_REG *) 0x0000004C) // (EMAC_FRO) Frames Received OK Register
-#define EMAC_FCSE (AT91_CAST(AT91_REG *) 0x00000050) // (EMAC_FCSE) Frame Check Sequence Error Register
-#define EMAC_ALE (AT91_CAST(AT91_REG *) 0x00000054) // (EMAC_ALE) Alignment Error Register
-#define EMAC_DTF (AT91_CAST(AT91_REG *) 0x00000058) // (EMAC_DTF) Deferred Transmission Frame Register
-#define EMAC_LCOL (AT91_CAST(AT91_REG *) 0x0000005C) // (EMAC_LCOL) Late Collision Register
-#define EMAC_ECOL (AT91_CAST(AT91_REG *) 0x00000060) // (EMAC_ECOL) Excessive Collision Register
-#define EMAC_TUND (AT91_CAST(AT91_REG *) 0x00000064) // (EMAC_TUND) Transmit Underrun Error Register
-#define EMAC_CSE (AT91_CAST(AT91_REG *) 0x00000068) // (EMAC_CSE) Carrier Sense Error Register
-#define EMAC_RRE (AT91_CAST(AT91_REG *) 0x0000006C) // (EMAC_RRE) Receive Ressource Error Register
-#define EMAC_ROV (AT91_CAST(AT91_REG *) 0x00000070) // (EMAC_ROV) Receive Overrun Errors Register
-#define EMAC_RSE (AT91_CAST(AT91_REG *) 0x00000074) // (EMAC_RSE) Receive Symbol Errors Register
-#define EMAC_ELE (AT91_CAST(AT91_REG *) 0x00000078) // (EMAC_ELE) Excessive Length Errors Register
-#define EMAC_RJA (AT91_CAST(AT91_REG *) 0x0000007C) // (EMAC_RJA) Receive Jabbers Register
-#define EMAC_USF (AT91_CAST(AT91_REG *) 0x00000080) // (EMAC_USF) Undersize Frames Register
-#define EMAC_STE (AT91_CAST(AT91_REG *) 0x00000084) // (EMAC_STE) SQE Test Error Register
-#define EMAC_RLE (AT91_CAST(AT91_REG *) 0x00000088) // (EMAC_RLE) Receive Length Field Mismatch Register
-#define EMAC_TPF (AT91_CAST(AT91_REG *) 0x0000008C) // (EMAC_TPF) Transmitted Pause Frames Register
-#define EMAC_HRB (AT91_CAST(AT91_REG *) 0x00000090) // (EMAC_HRB) Hash Address Bottom[31:0]
-#define EMAC_HRT (AT91_CAST(AT91_REG *) 0x00000094) // (EMAC_HRT) Hash Address Top[63:32]
-#define EMAC_SA1L (AT91_CAST(AT91_REG *) 0x00000098) // (EMAC_SA1L) Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H (AT91_CAST(AT91_REG *) 0x0000009C) // (EMAC_SA1H) Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L (AT91_CAST(AT91_REG *) 0x000000A0) // (EMAC_SA2L) Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H (AT91_CAST(AT91_REG *) 0x000000A4) // (EMAC_SA2H) Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L (AT91_CAST(AT91_REG *) 0x000000A8) // (EMAC_SA3L) Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H (AT91_CAST(AT91_REG *) 0x000000AC) // (EMAC_SA3H) Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L (AT91_CAST(AT91_REG *) 0x000000B0) // (EMAC_SA4L) Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H (AT91_CAST(AT91_REG *) 0x000000B4) // (EMAC_SA4H) Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID (AT91_CAST(AT91_REG *) 0x000000B8) // (EMAC_TID) Type ID Checking Register
-#define EMAC_TPQ (AT91_CAST(AT91_REG *) 0x000000BC) // (EMAC_TPQ) Transmit Pause Quantum Register
-#define EMAC_USRIO (AT91_CAST(AT91_REG *) 0x000000C0) // (EMAC_USRIO) USER Input/Output Register
-#define EMAC_WOL (AT91_CAST(AT91_REG *) 0x000000C4) // (EMAC_WOL) Wake On LAN Register
-#define EMAC_REV (AT91_CAST(AT91_REG *) 0x000000FC) // (EMAC_REV) Revision Register
-
-#endif
-// -------- EMAC_NCR : (EMAC Offset: 0x0) --------
-#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB (0x1 << 1) // (EMAC) Loopback local.
-#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable.
-#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable.
-#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable.
-#define AT91C_EMAC_CLRSTAT (0x1 << 5) // (EMAC) Clear statistics registers.
-#define AT91C_EMAC_INCSTAT (0x1 << 6) // (EMAC) Increment statistics registers.
-#define AT91C_EMAC_WESTAT (0x1 << 7) // (EMAC) Write enable for statistics registers.
-#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure.
-#define AT91C_EMAC_TSTART (0x1 << 9) // (EMAC) Start Transmission.
-#define AT91C_EMAC_THALT (0x1 << 10) // (EMAC) Transmission Halt.
-#define AT91C_EMAC_TPFR (0x1 << 11) // (EMAC) Transmit pause frame
-#define AT91C_EMAC_TZQ (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register --------
-#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed.
-#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex.
-#define AT91C_EMAC_JFRAME (0x1 << 3) // (EMAC) Jumbo Frames.
-#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames.
-#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast.
-#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable.
-#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes.
-#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable.
-#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC)
-#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8
-#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16
-#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32
-#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PAE (0x1 << 13) // (EMAC)
-#define AT91C_EMAC_RBOF (0x3 << 14) // (EMAC)
-#define AT91C_EMAC_RBOF_OFFSET_0 (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_1 (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_2 (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define AT91C_EMAC_RBOF_OFFSET_3 (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD (0x1 << 18) // (EMAC)
-#define AT91C_EMAC_IRXFCS (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register --------
-#define AT91C_EMAC_LINKR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC)
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register --------
-#define AT91C_EMAC_UBR (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_COL (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RLES (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TGO (0x1 << 3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX (0x1 << 4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_UND (0x1 << 6) // (EMAC)
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
-#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_REC (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_OVR (0x1 << 2) // (EMAC)
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
-#define AT91C_EMAC_MFD (0x1 << 0) // (EMAC)
-#define AT91C_EMAC_RCOMP (0x1 << 1) // (EMAC)
-#define AT91C_EMAC_RXUBR (0x1 << 2) // (EMAC)
-#define AT91C_EMAC_TXUBR (0x1 << 3) // (EMAC)
-#define AT91C_EMAC_TUNDR (0x1 << 4) // (EMAC)
-#define AT91C_EMAC_RLEX (0x1 << 5) // (EMAC)
-#define AT91C_EMAC_TXERR (0x1 << 6) // (EMAC)
-#define AT91C_EMAC_TCOMP (0x1 << 7) // (EMAC)
-#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC)
-#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC)
-#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC)
-#define AT91C_EMAC_PFRE (0x1 << 12) // (EMAC)
-#define AT91C_EMAC_PTZ (0x1 << 13) // (EMAC)
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
-#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC)
-#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC)
-#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC)
-#define AT91C_EMAC_RW (0x3 << 28) // (EMAC)
-#define AT91C_EMAC_SOF (0x3 << 30) // (EMAC)
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register --------
-#define AT91C_EMAC_RMII (0x1 << 0) // (EMAC) Reduce MII
-#define AT91C_EMAC_CLKEN (0x1 << 1) // (EMAC) Clock Enable
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register --------
-#define AT91C_EMAC_IP (0xFFFF << 0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1 (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register --------
-#define AT91C_EMAC_REVREF (0xFFFF << 0) // (EMAC)
-#define AT91C_EMAC_PARTREF (0xFFFF << 16) // (EMAC)
-
-// *****************************************************************************
-// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-// *****************************************************************************
-#ifndef __ASSEMBLY__
-typedef struct _AT91S_ADC {
- AT91_REG ADC_CR; // ADC Control Register
- AT91_REG ADC_MR; // ADC Mode Register
- AT91_REG Reserved0[2]; //
- AT91_REG ADC_CHER; // ADC Channel Enable Register
- AT91_REG ADC_CHDR; // ADC Channel Disable Register
- AT91_REG ADC_CHSR; // ADC Channel Status Register
- AT91_REG ADC_SR; // ADC Status Register
- AT91_REG ADC_LCDR; // ADC Last Converted Data Register
- AT91_REG ADC_IER; // ADC Interrupt Enable Register
- AT91_REG ADC_IDR; // ADC Interrupt Disable Register
- AT91_REG ADC_IMR; // ADC Interrupt Mask Register
- AT91_REG ADC_CDR0; // ADC Channel Data Register 0
- AT91_REG ADC_CDR1; // ADC Channel Data Register 1
- AT91_REG ADC_CDR2; // ADC Channel Data Register 2
- AT91_REG ADC_CDR3; // ADC Channel Data Register 3
- AT91_REG ADC_CDR4; // ADC Channel Data Register 4
- AT91_REG ADC_CDR5; // ADC Channel Data Register 5
- AT91_REG ADC_CDR6; // ADC Channel Data Register 6
- AT91_REG ADC_CDR7; // ADC Channel Data Register 7
- AT91_REG Reserved1[44]; //
- AT91_REG ADC_RPR; // Receive Pointer Register
- AT91_REG ADC_RCR; // Receive Counter Register
- AT91_REG ADC_TPR; // Transmit Pointer Register
- AT91_REG ADC_TCR; // Transmit Counter Register
- AT91_REG ADC_RNPR; // Receive Next Pointer Register
- AT91_REG ADC_RNCR; // Receive Next Counter Register
- AT91_REG ADC_TNPR; // Transmit Next Pointer Register
- AT91_REG ADC_TNCR; // Transmit Next Counter Register
- AT91_REG ADC_PTCR; // PDC Transfer Control Register
- AT91_REG ADC_PTSR; // PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-#else
-#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
-#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
-#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
-#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
-#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
-#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
-#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
-#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
-#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
-#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
-#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
-#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
-#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
-#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
-#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
-#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
-#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
-#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
-
-#endif
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
-#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
-#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
-#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
-#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
-#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
-#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
-#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
-#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
-#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
-#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
-#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
-#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
-// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
-#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
-#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
-#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
-#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
-#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
-#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
-#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
-// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-// *****************************************************************************
-// REGISTER ADDRESS DEFINITION FOR AT91SAM7X512
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ==========
-// ========== Register definition for AIC peripheral ==========
-#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ==========
-#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ==========
-#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ==========
-#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
-// ========== Register definition for PMC peripheral ==========
-#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
-#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ==========
-#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ==========
-#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ==========
-#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ==========
-#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ==========
-#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for EFC0 peripheral ==========
-#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register
-#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register
-#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register
-#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register
-// ========== Register definition for EFC1 peripheral ==========
-#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register
-#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register
-#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register
-#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register
-// ========== Register definition for MC peripheral ==========
-#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals
-#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area
-#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register
-// ========== Register definition for PDC_SPI1 peripheral ==========
-#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ==========
-#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ==========
-#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ==========
-#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ==========
-#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ==========
-#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ==========
-#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ==========
-#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ==========
-#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ==========
-#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ==========
-#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ==========
-#define AT91C_PWMC_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ==========
-#define AT91C_PWMC_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ==========
-#define AT91C_PWMC_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ==========
-#define AT91C_PWMC_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ==========
-#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ==========
-#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ==========
-#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ==========
-#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ==========
-#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ==========
-#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ==========
-#define AT91C_CAN_MB0_MDL (AT91_CAST(AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM (AT91_CAST(AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR (AT91_CAST(AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID (AT91_CAST(AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR (AT91_CAST(AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID (AT91_CAST(AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH (AT91_CAST(AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR (AT91_CAST(AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ==========
-#define AT91C_CAN_MB1_MDL (AT91_CAST(AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID (AT91_CAST(AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR (AT91_CAST(AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR (AT91_CAST(AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM (AT91_CAST(AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH (AT91_CAST(AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR (AT91_CAST(AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID (AT91_CAST(AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ==========
-#define AT91C_CAN_MB2_MCR (AT91_CAST(AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH (AT91_CAST(AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID (AT91_CAST(AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL (AT91_CAST(AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR (AT91_CAST(AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM (AT91_CAST(AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID (AT91_CAST(AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR (AT91_CAST(AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ==========
-#define AT91C_CAN_MB3_MFID (AT91_CAST(AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM (AT91_CAST(AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID (AT91_CAST(AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR (AT91_CAST(AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR (AT91_CAST(AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR (AT91_CAST(AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL (AT91_CAST(AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH (AT91_CAST(AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ==========
-#define AT91C_CAN_MB4_MID (AT91_CAST(AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR (AT91_CAST(AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH (AT91_CAST(AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID (AT91_CAST(AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR (AT91_CAST(AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR (AT91_CAST(AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL (AT91_CAST(AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM (AT91_CAST(AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ==========
-#define AT91C_CAN_MB5_MSR (AT91_CAST(AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR (AT91_CAST(AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID (AT91_CAST(AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH (AT91_CAST(AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID (AT91_CAST(AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR (AT91_CAST(AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL (AT91_CAST(AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM (AT91_CAST(AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ==========
-#define AT91C_CAN_MB6_MFID (AT91_CAST(AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID (AT91_CAST(AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM (AT91_CAST(AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR (AT91_CAST(AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL (AT91_CAST(AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR (AT91_CAST(AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH (AT91_CAST(AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR (AT91_CAST(AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ==========
-#define AT91C_CAN_MB7_MCR (AT91_CAST(AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH (AT91_CAST(AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID (AT91_CAST(AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL (AT91_CAST(AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID (AT91_CAST(AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR (AT91_CAST(AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM (AT91_CAST(AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR (AT91_CAST(AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ==========
-#define AT91C_CAN_TCR (AT91_CAST(AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR (AT91_CAST(AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER (AT91_CAST(AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR (AT91_CAST(AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP (AT91_CAST(AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR (AT91_CAST(AT91_REG *) 0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR (AT91_CAST(AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR (AT91_CAST(AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM (AT91_CAST(AT91_REG *) 0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR (AT91_CAST(AT91_REG *) 0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR (AT91_CAST(AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR (AT91_CAST(AT91_REG *) 0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ==========
-#define AT91C_EMAC_ISR (AT91_CAST(AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H (AT91_CAST(AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L (AT91_CAST(AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE (AT91_CAST(AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL (AT91_CAST(AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE (AT91_CAST(AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL (AT91_CAST(AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF (AT91_CAST(AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND (AT91_CAST(AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR (AT91_CAST(AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L (AT91_CAST(AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR (AT91_CAST(AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L (AT91_CAST(AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR (AT91_CAST(AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR (AT91_CAST(AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE (AT91_CAST(AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL (AT91_CAST(AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID (AT91_CAST(AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB (AT91_CAST(AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP (AT91_CAST(AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO (AT91_CAST(AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR (AT91_CAST(AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H (AT91_CAST(AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV (AT91_CAST(AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE (AT91_CAST(AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA (AT91_CAST(AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP (AT91_CAST(AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF (AT91_CAST(AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR (AT91_CAST(AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT (AT91_CAST(AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF (AT91_CAST(AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE (AT91_CAST(AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ (AT91_CAST(AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN (AT91_CAST(AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO (AT91_CAST(AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV (AT91_CAST(AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR (AT91_CAST(AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF (AT91_CAST(AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR (AT91_CAST(AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF (AT91_CAST(AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR (AT91_CAST(AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L (AT91_CAST(AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO (AT91_CAST(AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER (AT91_CAST(AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H (AT91_CAST(AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE (AT91_CAST(AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H (AT91_CAST(AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE (AT91_CAST(AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE (AT91_CAST(AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ==========
-#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ==========
-#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-
-// *****************************************************************************
-// PIO DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0 (AT91C_PIO_PA0) // USART 0 Receive Data
-#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0 (AT91C_PIO_PA1) // USART 0 Transmit Data
-#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD (AT91C_PIO_PA10) // TWI Two-wire Serial Data
-#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK (AT91C_PIO_PA11) // TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_SPI0_NPCS0 (AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_SPI0_NPCS1 (AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1 (AT91C_PIO_PA13) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPI0_NPCS2 (AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1 (AT91C_PIO_PA14) // External Interrupt 1
-#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_SPI0_NPCS3 (AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input
-#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_SPI0_MISO (AT91C_PIO_PA16) // SPI 0 Master In Slave
-#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_SPI0_MOSI (AT91C_PIO_PA17) // SPI 0 Master Out Slave
-#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPI0_SPCK (AT91C_PIO_PA18) // SPI 0 Serial Clock
-#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX (AT91C_PIO_PA19) // CAN Receive
-#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
-#define AT91C_PA2_SPI1_NPCS1 (AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX (AT91C_PIO_PA20) // CAN Transmit
-#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF (AT91C_PIO_PA21) // SSC Transmit Frame Sync
-#define AT91C_PA21_SPI1_NPCS0 (AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK (AT91C_PIO_PA22) // SSC Transmit Clock
-#define AT91C_PA22_SPI1_SPCK (AT91C_PIO_PA22) // SPI 1 Serial Clock
-#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD (AT91C_PIO_PA23) // SSC Transmit data
-#define AT91C_PA23_SPI1_MOSI (AT91C_PIO_PA23) // SPI 1 Master Out Slave
-#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD (AT91C_PIO_PA24) // SSC Receive Data
-#define AT91C_PA24_SPI1_MISO (AT91C_PIO_PA24) // SPI 1 Master In Slave
-#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK (AT91C_PIO_PA25) // SSC Receive Clock
-#define AT91C_PA25_SPI1_NPCS1 (AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF (AT91C_PIO_PA26) // SSC Receive Frame Sync
-#define AT91C_PA26_SPI1_NPCS2 (AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD (AT91C_PIO_PA27) // DBGU Debug Receive Data
-#define AT91C_PA27_PCK3 (AT91C_PIO_PA27) // PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD (AT91C_PIO_PA28) // DBGU Debug Transmit Data
-#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ (AT91C_PIO_PA29) // AIC Fast Interrupt Input
-#define AT91C_PA29_SPI1_NPCS3 (AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) // USART 0 Ready To Send
-#define AT91C_PA3_SPI1_NPCS2 (AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0 (AT91C_PIO_PA30) // External Interrupt 0
-#define AT91C_PA30_PCK2 (AT91C_PIO_PA30) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) // USART 0 Clear To Send
-#define AT91C_PA4_SPI1_NPCS3 (AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1 (AT91C_PIO_PA5) // USART 1 Receive Data
-#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1 (AT91C_PIO_PA6) // USART 1 Transmit Data
-#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1 (AT91C_PIO_PA7) // USART 1 Serial Clock
-#define AT91C_PA7_SPI0_NPCS1 (AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1 (AT91C_PIO_PA8) // USART 1 Ready To Send
-#define AT91C_PA8_SPI0_NPCS2 (AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1 (AT91C_PIO_PA9) // USART 1 Clear To Send
-#define AT91C_PA9_SPI0_NPCS3 (AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK (AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0 (AT91C_PIO_PB0) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN (AT91C_PIO_PB1) // Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2 (AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2
-#define AT91C_PB10_SPI1_NPCS1 (AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3 (AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3
-#define AT91C_PB11_SPI1_NPCS2 (AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER (AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0 (AT91C_PIO_PB12) // Timer Counter 0 external clock input
-#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2 (AT91C_PIO_PB13) // Ethernet MAC Receive Data 2
-#define AT91C_PB13_SPI0_NPCS1 (AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3 (AT91C_PIO_PB14) // Ethernet MAC Receive Data 3
-#define AT91C_PB14_SPI0_NPCS2 (AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV_ECRSDV (AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL (AT91C_PIO_PB16) // Ethernet MAC Collision Detected
-#define AT91C_PB16_SPI1_NPCS3 (AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK (AT91C_PIO_PB17) // Ethernet MAC Receive Clock
-#define AT91C_PB17_SPI0_NPCS3 (AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100 (AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG (AT91C_PIO_PB18) // ADC External Trigger
-#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0 (AT91C_PIO_PB19) // PWM Channel 0
-#define AT91C_PB19_TCLK1 (AT91C_PIO_PB19) // Timer Counter 1 external clock input
-#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0 (AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1 (AT91C_PIO_PB20) // PWM Channel 1
-#define AT91C_PB20_PCK0 (AT91C_PIO_PB20) // PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2 (AT91C_PIO_PB21) // PWM Channel 2
-#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3 (AT91C_PIO_PB22) // PWM Channel 3
-#define AT91C_PB22_PCK2 (AT91C_PIO_PB22) // PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0 (AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0 (AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1 (AT91C_PIO_PB24) // USART 1 Data Set ready
-#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1 (AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1 (AT91C_PIO_PB25) // USART 1 Data Terminal ready
-#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1 (AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1 (AT91C_PIO_PB26) // USART 1 Ring Indicator
-#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2 (AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0 (AT91C_PIO_PB27) // PWM Channel 0
-#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2 (AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1 (AT91C_PIO_PB28) // PWM Channel 1
-#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1 (AT91C_PIO_PB29) // PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2 (AT91C_PIO_PB29) // PWM Channel 2
-#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1 (AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2 (AT91C_PIO_PB30) // PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3 (AT91C_PIO_PB30) // PWM Channel 3
-#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS (AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0 (AT91C_PIO_PB5) // Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1 (AT91C_PIO_PB6) // Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER (AT91C_PIO_PB7) // Ethernet MAC Receive Error
-#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC (AT91C_PIO_PB8) // Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO (AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS ( 1) // System Peripheral
-#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0 ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1 ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0 ( 6) // USART 0
-#define AT91C_ID_US1 ( 7) // USART 1
-#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC (10) // PWM Controller
-#define AT91C_ID_UDP (11) // USB Device Port
-#define AT91C_ID_TC0 (12) // Timer Counter 0
-#define AT91C_ID_TC1 (13) // Timer Counter 1
-#define AT91C_ID_TC2 (14) // Timer Counter 2
-#define AT91C_ID_CAN (15) // Control Area Network Controller
-#define AT91C_ID_EMAC (16) // Ethernet MAC
-#define AT91C_ID_ADC (17) // Analog-to-Digital Converter
-#define AT91C_ID_18_Reserved (18) // Reserved
-#define AT91C_ID_19_Reserved (19) // Reserved
-#define AT91C_ID_20_Reserved (20) // Reserved
-#define AT91C_ID_21_Reserved (21) // Reserved
-#define AT91C_ID_22_Reserved (22) // Reserved
-#define AT91C_ID_23_Reserved (23) // Reserved
-#define AT91C_ID_24_Reserved (24) // Reserved
-#define AT91C_ID_25_Reserved (25) // Reserved
-#define AT91C_ID_26_Reserved (26) // Reserved
-#define AT91C_ID_27_Reserved (27) // Reserved
-#define AT91C_ID_28_Reserved (28) // Reserved
-#define AT91C_ID_29_Reserved (29) // Reserved
-#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
-#define AT91C_ALL_INT (0xC003FFFF) // ALL VALID INTERRUPTS
-
-// *****************************************************************************
-// BASE ADDRESS DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address
-#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address
-#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7 (AT91_CAST(AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN (AT91_CAST(AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC (AT91_CAST(AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address
-
-// *****************************************************************************
-// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X512
-// *****************************************************************************
-// ISRAM
-#define AT91C_ISRAM (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE (0x00020000) // Internal SRAM size in byte (128 Kbytes)
-// IFLASH
-#define AT91C_IFLASH (0x00100000) // Internal FLASH base address
-#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes)
-#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes
-#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes
-#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes
-#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes
-
-#endif
diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.c b/os/hal/platforms/AT91SAM7/at91lib/aic.c deleted file mode 100644 index 66eebf94e..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/aic.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support - ROUSSET -
- * ----------------------------------------------------------------------------
- * Copyright (c) 2006, Atmel Corporation
-
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaiimer below.
- *
- * - Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the disclaimer below in the documentation and/or
- * other materials provided with the distribution.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include "aic.h"
-#include <board.h>
-
-//------------------------------------------------------------------------------
-// Exported functions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-/// Configures the interrupt associated with the given source, using the
-/// specified mode and interrupt handler.
-/// \param source Interrupt source to configure.
-/// \param mode Triggering mode of the interrupt.
-/// \param handler Interrupt handler function.
-//------------------------------------------------------------------------------
-void AIC_ConfigureIT(unsigned int source,
- unsigned int mode,
- void (*handler)( void ))
-{
- // Disable the interrupt first
- AT91C_BASE_AIC->AIC_IDCR = 1 << source;
-
- // Configure mode and handler
- AT91C_BASE_AIC->AIC_SMR[source] = mode;
- AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler;
-
- // Clear interrupt
- AT91C_BASE_AIC->AIC_ICCR = 1 << source;
-}
-
-//------------------------------------------------------------------------------
-/// Enables interrupts coming from the given (unique) source.
-/// \param source Interrupt source to enable.
-//------------------------------------------------------------------------------
-void AIC_EnableIT(unsigned int source)
-{
- AT91C_BASE_AIC->AIC_IECR = 1 << source;
-}
-
-//------------------------------------------------------------------------------
-/// Disables interrupts coming from the given (unique) source.
-/// \param source Interrupt source to enable.
-//------------------------------------------------------------------------------
-void AIC_DisableIT(unsigned int source)
-{
- AT91C_BASE_AIC->AIC_IDCR = 1 << source;
-}
-
diff --git a/os/hal/platforms/AT91SAM7/at91lib/aic.h b/os/hal/platforms/AT91SAM7/at91lib/aic.h deleted file mode 100644 index e8e52c78a..000000000 --- a/os/hal/platforms/AT91SAM7/at91lib/aic.h +++ /dev/null @@ -1,78 +0,0 @@ -/* ----------------------------------------------------------------------------
- * ATMEL Microcontroller Software Support - ROUSSET -
- * ----------------------------------------------------------------------------
- * Copyright (c) 2006, Atmel Corporation
-
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * - Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the disclaiimer below.
- *
- * - Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the disclaimer below in the documentation and/or
- * other materials provided with the distribution.
- *
- * Atmel's name may not be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * ----------------------------------------------------------------------------
- */
-
-//------------------------------------------------------------------------------
-/// \dir
-/// !Purpose
-///
-/// Methods and definitions for configuring interrupts using the Advanced
-/// Interrupt Controller (AIC).
-///
-/// !Usage
-/// -# Configure an interrupt source using AIC_ConfigureIT
-/// -# Enable or disable interrupt generation of a particular source with
-/// AIC_EnableIT and AIC_DisableIT.
-//------------------------------------------------------------------------------
-
-#ifndef AIC_H
-#define AIC_H
-
-//------------------------------------------------------------------------------
-// Headers
-//------------------------------------------------------------------------------
-
-#include <board.h>
-
-//------------------------------------------------------------------------------
-// Definitions
-//------------------------------------------------------------------------------
-
-#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL
- /// Redefinition of missing constant.
- #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE
-#endif
-
-//------------------------------------------------------------------------------
-// Global functions
-//------------------------------------------------------------------------------
-
-extern void AIC_ConfigureIT(unsigned int source,
- unsigned int mode,
- void (*handler)( void ));
-
-extern void AIC_EnableIT(unsigned int source);
-
-extern void AIC_DisableIT(unsigned int source);
-
-#endif //#ifndef AIC_H
-
diff --git a/os/hal/platforms/AT91SAM7/at91sam7.h b/os/hal/platforms/AT91SAM7/at91sam7.h deleted file mode 100644 index 0d3ce288e..000000000 --- a/os/hal/platforms/AT91SAM7/at91sam7.h +++ /dev/null @@ -1,56 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _AT91SAM7_H_
-#define _AT91SAM7_H_
-
-/*
- * Supported platforms.
- */
-#define SAM7S64 0
-#define SAM7S128 1
-#define SAM7S256 2
-#define SAM7S512 3
-#define SAM7X128 4
-#define SAM7X256 5
-#define SAM7X512 6
-#define SAM7A3 7
-
-#ifndef SAM7_PLATFORM
-#error "SAM7 platform not defined"
-#endif
-
-#if SAM7_PLATFORM == SAM7S64
-#include "at91lib/AT91SAM7S64.h"
-#elif SAM7_PLATFORM == SAM7S128
-#include "at91lib/AT91SAM7S128.h"
-#elif SAM7_PLATFORM == SAM7S256
-#include "at91lib/AT91SAM7S256.h"
-#elif SAM7_PLATFORM == SAM7S512
-#include "at91lib/AT91SAM7S512.h"
-#elif SAM7_PLATFORM == SAM7X128
-#include "at91lib/AT91SAM7X128.h"
-#elif SAM7_PLATFORM == SAM7X256
-#include "at91lib/AT91SAM7X256.h"
-#elif SAM7_PLATFORM == SAM7X512
-#include "at91lib/AT91SAM7X512.h"
-#elif SAM7_PLATFORM == SAM7A3
-#include "at91lib/AT91SAM7A3.h"
-#else
-#error "SAM7 platform not supported"
-#endif
-
-#endif /* _AT91SAM7_H_ */
diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.c b/os/hal/platforms/AT91SAM7/at91sam7_mii.c deleted file mode 100644 index b64a389a2..000000000 --- a/os/hal/platforms/AT91SAM7/at91sam7_mii.c +++ /dev/null @@ -1,144 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/at91sam7_mii.c
- * @brief AT91SAM7 low level MII driver code.
- *
- * @addtogroup AT91SAM7_MII
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-#include "at91sam7_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level MII driver initialization.
- *
- * @notapi
- */
-void miiInit(void) {
-
-}
-
-/**
- * @brief Resets a PHY device.
- *
- * @param[in] macp pointer to the @p MACDriver object
- *
- * @notapi
- */
-void miiReset(MACDriver *macp) {
-
- (void)macp;
-
- /*
- * Disables the pullups on all the pins that are latched on reset by the PHY.
- */
- AT91C_BASE_PIOB->PIO_PPUDR = PHY_LATCHED_PINS;
-
-#ifdef PIOB_PHY_PD_MASK
- /*
- * PHY power control.
- */
- AT91C_BASE_PIOB->PIO_OER = PIOB_PHY_PD_MASK; /* Becomes an output. */
- AT91C_BASE_PIOB->PIO_PPUDR = PIOB_PHY_PD_MASK;/* Default pullup disabled. */
-#if (PHY_HARDWARE == PHY_DAVICOM_9161)
- AT91C_BASE_PIOB->PIO_CODR = PIOB_PHY_PD_MASK; /* Output to low level. */
-#else
- AT91C_BASE_PIOB->PIO_SODR = PIOB_PHY_PD_MASK; /* Output to high level. */
-#endif
-#endif
-
- /*
- * PHY reset by pulsing the NRST pin.
- */
- AT91C_BASE_RSTC->RSTC_RMR = 0xA5000100;
- AT91C_BASE_RSTC->RSTC_RCR = 0xA5000000 | AT91C_RSTC_EXTRST;
- while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL))
- ;
-}
-
-/**
- * @brief Reads a PHY register through the MII interface.
- *
- * @param[in] macp pointer to the @p MACDriver object
- * @param[in] addr the register address
- * @return The register value.
- *
- * @notapi
- */
-phyreg_t miiGet(MACDriver *macp, phyaddr_t addr) {
-
- (void)macp;
- AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */
- (0b10 << 28) | /* RW */
- (PHY_ADDRESS << 23) | /* PHYA */
- (addr << 18) | /* REGA */
- (0b10 << 16); /* CODE */
- while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
- ;
- return (phyreg_t)(AT91C_BASE_EMAC->EMAC_MAN & 0xFFFF);
-}
-
-/**
- * @brief Writes a PHY register through the MII interface.
- *
- * @param[in] macp pointer to the @p MACDriver object
- * @param[in] addr the register address
- * @param[in] value the new register value
- *
- * @notapi
- */
-void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value) {
-
- (void)macp;
- AT91C_BASE_EMAC->EMAC_MAN = (0b01 << 30) | /* SOF */
- (0b01 << 28) | /* RW */
- (PHY_ADDRESS << 23) | /* PHYA */
- (addr << 18) | /* REGA */
- (0b10 << 16) | /* CODE */
- value;
- while (!( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE))
- ;
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/at91sam7_mii.h b/os/hal/platforms/AT91SAM7/at91sam7_mii.h deleted file mode 100644 index f55db7e78..000000000 --- a/os/hal/platforms/AT91SAM7/at91sam7_mii.h +++ /dev/null @@ -1,111 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/at91sam7_mii.h
- * @brief AT91SAM7 low level MII driver header.
- *
- * @addtogroup AT91SAM7_MII
- * @{
- */
-
-#ifndef _AT91SAM7_MII_H_
-#define _AT91SAM7_MII_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define PHY_MICREL_KS8721 0
-#define PHY_DAVICOM_9161 1
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief PHY manufacturer and model.
- */
-#if !defined(PHY_HARDWARE) || defined(__DOXYGEN__)
-#define PHY_HARDWARE PHY_MICREL_KS8721
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/**
- * @brief Pins latched by the PHY at reset.
- */
-#if PHY_HARDWARE == PHY_MICREL_KS8721
-#define PHY_ADDRESS 1
-#define PHY_ID MII_KS8721_ID
-#define PHY_LATCHED_PINS (AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \
- AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \
- AT91C_PB13_ERX2 | AT91C_PB14_ERX3 | \
- AT91C_PB15_ERXDV_ECRSDV | AT91C_PB16_ECOL | \
- AT91C_PIO_PB26)
-
-#elif PHY_HARDWARE == PHY_DAVICOM_9161
-#define PHY_ADDRESS 0
-#define PHY_ID MII_DM9161_ID
-#define PHY_LATCHED_PINS (AT91C_PB0_ETXCK_EREFCK | AT91C_PB4_ECRS | \
- AT91C_PB5_ERX0 | AT91C_PB6_ERX1 | \
- AT91C_PB7_ERXER | AT91C_PB13_ERX2 | \
- AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \
- AT91C_PB16_ECOL | AT91C_PB17_ERXCK)
-#endif /* PHY_HARDWARE */
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a PHY register value.
- */
-typedef uint16_t phyreg_t;
-
-/**
- * @brief Type of a PHY register address.
- */
-typedef uint8_t phyaddr_t;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void miiInit(void);
- void miiReset(MACDriver *macp);
- phyreg_t miiGet(MACDriver *macp, phyaddr_t addr);
- void miiPut(MACDriver *macp, phyaddr_t addr, phyreg_t value);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _AT91SAM7_MII_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c deleted file mode 100644 index 91d0b7a8d..000000000 --- a/os/hal/platforms/AT91SAM7/ext_lld.c +++ /dev/null @@ -1,235 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/ext_lld.c
- * @brief AT91SAM7 EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief EXTDA driver identifier.
- */
-EXTDriver EXTDA;
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief EXTDB driver identifier.
- */
-EXTDriver EXTDB;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Handles external interrupts.
- *
- * @param[in] extp pointer to the driver that received the interrupt
- */
-static void ext_lld_serveInterrupt(EXTDriver *extp) {
- uint32_t irqFlags;
- uint32_t ch;
-
- chSysLockFromIsr();
-
- /* Read flags of pending PIO interrupts.*/
- irqFlags = extp->pio->PIO_ISR;
-
- /* Call callback function for any pending interrupt.*/
- for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) {
-
- /* Check if the channel is activated and if its IRQ flag is set.*/
- if((extp->config->channels[ch].mode &
- EXT_CH_MODE_ENABLED & EXT_CH_MODE_EDGES_MASK)
- && ((1 << ch) & irqFlags)) {
- (extp->config->channels[ch].cb)(extp, ch);
- }
- }
-
- chSysUnlockFromIsr();
-
- AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief EXTI[0] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTIA_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
-
- ext_lld_serveInterrupt(&EXTDA);
-
- CH_IRQ_EPILOGUE();
-}
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief EXTI[1] interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(EXTIB_IRQHandler) {
- CH_IRQ_PROLOGUE();
-
- ext_lld_serveInterrupt(&EXTDB);
-
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void) {
-
- /* Driver initialization.*/
- extObjectInit(&EXTDA);
-
- /* Set PIO base addresses.*/
- EXTDA.pio = AT91C_BASE_PIOA;
-
- /* Set peripheral IDs.*/
- EXTDA.pid = AT91C_ID_PIOA;
-
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
- /* Same for PIOB.*/
- extObjectInit(&EXTDB);
- EXTDB.pio = AT91C_BASE_PIOB;
- EXTDB.pid = AT91C_ID_PIOB;
-#endif
-}
-
-/**
- * @brief Configures and activates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp) {
- uint16_t ch;
- uint32_t ier = 0;
- const EXTConfig *config = extp->config;
-
- switch(extp->pid) {
- case AT91C_ID_PIOA:
- AIC_ConfigureIT(AT91C_ID_PIOA, SAM7_computeSMR(config->mode,
- config->priority),
- EXTIA_IRQHandler);
- break;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
- case AT91C_ID_PIOB:
- AIC_ConfigureIT(AT91C_ID_PIOB, SAM7_computeSMR(config->mode,
- config->priority),
- EXTIB_IRQHandler);
- break;
-#endif
- }
-
- /* Enable and Disable channels with respect to config.*/
- for(ch = 0; ch < EXT_MAX_CHANNELS; ch++) {
- ier |= (config->channels[ch].mode & EXT_CH_MODE_EDGES_MASK & EXT_CH_MODE_ENABLED ? 1 : 0) << ch;
- }
- extp->pio->PIO_IER = ier;
- extp->pio->PIO_IDR = ~ier;
-
- /* Enable interrupt on corresponding PIO port in AIC.*/
- AIC_EnableIT(extp->pid);
-}
-
-/**
- * @brief Deactivates the EXT peripheral.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp) {
-
- /* Disable interrupt on corresponding PIO port in AIC.*/
- AIC_DisableIT(extp->pid);
-}
-
-/**
- * @brief Enables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) {
-
- chDbgCheck((extp->config->channels[channel].cb != NULL),
- "Call back pointer can not be NULL");
-
- extp->pio->PIO_IER = (1 << channel);
-}
-
-/**
- * @brief Disables an EXT channel.
- *
- * @param[in] extp pointer to the @p EXTDriver object
- * @param[in] channel channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) {
-
- extp->pio->PIO_IDR = (1 << channel);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/ext_lld.h b/os/hal/platforms/AT91SAM7/ext_lld.h deleted file mode 100644 index 3bc0baa99..000000000 --- a/os/hal/platforms/AT91SAM7/ext_lld.h +++ /dev/null @@ -1,239 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/ext_lld.h
- * @brief AT91SAM7 EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_H_
-#define _EXT_LLD_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Pointer to the SAM7 AIC register block.
- */
-#define SAM7_EXT_AIC ((AT91PS_AIC *)AT91C_BASE_AIC)
-
-/**
- * @brief Number of channels within one ext driver.
- */
-#define EXT_MAX_CHANNELS 32
-
-/**
- * @brief Mask of priority bits in interrupt mode register.
- */
-#define SAM7_EXT_PRIORITY_MASK 0x00000007
-
-/**
- * @brief Shifter for priority bits in interrupt mode register.
- */
-#define SAM7_EXT_PRIORITY_SHIFTER 0
-
-/**
- * @brief Shifter for mode bits in interrupt mode register.
- */
-#define SAM7_EXT_MODE_SHIFTER 5
-
-/*
- * On the SAM7 architecture, a single channel can only be enables or disabled
- * Hence, undefine the other channel mode constants
- */
-#ifdef EXT_CH_MODE_RISING_EDGE
-#undef EXT_CH_MODE_RISING_EDGE
-#endif
-
-#ifdef EXT_CH_MODE_FALLING_EDGE
-#undef EXT_CH_MODE_FALLING_EDGE
-#endif
-
-#ifdef EXT_CH_MODE_BOTH_EDGES
-#undef EXT_CH_MODE_BOTH_EDGES
-#endif
-
-/**
- * @name EXT channels mode
- * @{
- */
-#define EXT_CH_MODE_ENABLED 1 /**< @brief Channel is enabled. */
-/** @} */
-
-/**
- * @name EXT drivers mode
- * @{
- */
-/**
- * @brief Mask for modes.
- */
-#define SAM7_EXT_MODE_MASK AT91C_AIC_SRCTYPE
-/**
- * @brief Falling edge callback.
- */
-#define SAM7_EXT_MODE_FALLING_EDGE AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE
-/**
- * @brief Rising edge callback.
- */
-#define SAM7_EXT_MODE_RISING_EDGE AT91C_AIC_SRCTYPE_POSITIVE_EDGE
-/**
- * @brief High-level callback.
- */
-#define SAM7_EXT_MODE_HIGH_LEVEL AT91C_AIC_SRCTYPE_HIGH_LEVEL
-/**
- * @brief Low-level callback.
- */
-#define SAM7_EXT_MODE_LOW_LEVEL AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL
-/** @} */
-
-/**
- * @name EXT drivers priorities
- * @{
- */
-#define SAM7_EXT_PRIOR_HIGHEST AT91C_AIC_PRIOR_HIGHEST
-#define SAM7_EXT_PRIOR_LOWEST AT91C_AIC_PRIOR_LOWEST
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief Type of an EXT generic notification callback.
- *
- * @param[in] extp pointer to the @p EXPDriver object triggering the
- * callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief Channel configuration structure.
- */
-typedef struct {
- /**
- * @brief Channel mode.
- */
- uint32_t mode;
- /**
- * @brief Channel callback.
- */
- extcallback_t cb;
-} EXTChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Channel configurations.
- */
- EXTChannelConfig channels[EXT_MAX_CHANNELS];
- /* End of the mandatory fields.*/
- /**
- * @brief interrupt mode.
- */
- uint32_t mode;
- /**
- * @brief interrupt priority.
- */
- uint32_t priority;
-} EXTConfig;
-
-/**
- * @brief Structure representing an EXT driver.
- */
-struct EXTDriver {
- /**
- * @brief Driver state.
- */
- extstate_t state;
- /**
- * @brief Current configuration data.
- */
- const EXTConfig *config;
- /* End of the mandatory fields.*/
-
- /**
- * @brief Pointer to the corresponding PIO registers block.
- */
- AT91PS_PIO pio;
- /**
- * @brief peripheral ID of the corresponding PIO block.
- */
- uint32_t pid;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Computes the content for the interrupt source mode register.
- */
-#define SAM7_computeSMR(mode, prio) ( \
- ((mode & SAM7_EXT_MODE_MASK) << SAM7_EXT_MODE_SHIFTER) | \
- ((prio & SAM7_EXT_PRIORITY_MASK) << SAM7_EXT_PRIORITY_SHIFTER) \
-)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTDA;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
-extern EXTDriver EXTDB;
-#endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void ext_lld_init(void);
- void ext_lld_start(EXTDriver *extp);
- void ext_lld_stop(EXTDriver *extp);
- void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
- void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/hal_lld.c b/os/hal/platforms/AT91SAM7/hal_lld.c deleted file mode 100644 index 43659ed9c..000000000 --- a/os/hal/platforms/AT91SAM7/hal_lld.c +++ /dev/null @@ -1,129 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/hal_lld.c
- * @brief AT91SAM7 HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-static CH_IRQ_HANDLER(spurious_handler) {
-
- CH_IRQ_PROLOGUE();
-
- AT91SAM7_SPURIOUS_HANDLER_HOOK();
-
- AT91C_BASE_AIC->AIC_EOICR = 0;
-
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
- unsigned i;
-
- /* FIQ Handler weak symbol defined in vectors.s.*/
- void FiqHandler(void);
-
- /* Default AIC setup, the device drivers will modify it as needed.*/
- AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
- AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
- AT91C_BASE_AIC->AIC_SVR[0] = (AT91_REG)FiqHandler;
- for (i = 1; i < 31; i++) {
- AT91C_BASE_AIC->AIC_SVR[i] = (AT91_REG)NULL;
- AT91C_BASE_AIC->AIC_EOICR = (AT91_REG)i;
- }
- AT91C_BASE_AIC->AIC_SPU = (AT91_REG)spurious_handler;
-
-}
-
-/**
- * @brief AT91SAM7 clocks and PLL initialization.
- * @note All the involved constants come from the file @p board.h.
- * @note This function must be invoked only after the system reset.
- *
- * @special
- */
-void at91sam7_clock_init(void) {
-
- /* wait for reset */
- while((AT91C_BASE_RSTC->RSTC_RSR & (AT91C_RSTC_SRCMP | AT91C_RSTC_NRSTL)) != AT91C_RSTC_NRSTL)
- ;
- /* enable reset */
- AT91C_BASE_RSTC->RSTC_RMR = ((0xA5 << 24) | AT91C_RSTC_URSTEN);
-
- /* Flash Memory: 1 wait state, about 50 cycles in a microsecond.*/
-#if SAM7_PLATFORM == SAM7X512
- AT91C_BASE_MC->MC0_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
- AT91C_BASE_MC->MC1_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
-#else
- AT91C_BASE_MC->MC_FMR = (AT91C_MC_FMCN & (50 << 16)) | AT91C_MC_FWS_1FWS;
-#endif
-
- /* Enables the main oscillator and waits 56 slow cycles as startup time.*/
- AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (7 << 8)) | AT91C_CKGR_MOSCEN;
- while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS))
- ;
-
- /* PLL setup: DIV = 14, MUL = 72, PLLCOUNT = 10
- PLLfreq = 96109714 Hz (rounded).*/
- AT91C_BASE_PMC->PMC_PLLR = (AT91C_CKGR_DIV & 14) |
- (AT91C_CKGR_PLLCOUNT & (10 << 8)) |
- (AT91SAM7_USBDIV) |
- (AT91C_CKGR_MUL & (72 << 16));
- while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK))
- ;
-
- /* Master clock = PLLfreq / 2 = 48054858 Hz (rounded).*/
- AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
- while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
- ;
-
- AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
- while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
- ;
-}
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/hal_lld.h b/os/hal/platforms/AT91SAM7/hal_lld.h deleted file mode 100644 index 2a489be6f..000000000 --- a/os/hal/platforms/AT91SAM7/hal_lld.h +++ /dev/null @@ -1,90 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/hal_lld.h
- * @brief AT91SAM7 HAL subsystem low level driver header.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "at91sam7.h"
-#include "at91lib/aic.h"
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Defines the support for realtime counters in the HAL.
- */
-#define HAL_IMPLEMENTS_COUNTERS FALSE
-
-/**
- * @brief Platform name.
- */
-#define PLATFORM_NAME "AT91SAM7x"
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief Default action for the spurious handler, nothing.
- */
-#if !defined(AT91SAM7_SPURIOUS_HANDLER_HOOK) || defined(__DOXYGEN__)
-#define AT91SAM7_SPURIOUS_HANDLER_HOOK()
-#endif
-
-/**
- * @brief Default divider for the USB clock - half the PLL clock.
- */
-#if !defined(AT91SAM7_USBDIV) || defined(__DOXYGEN__)
-#define AT91SAM7_USBDIV AT91C_CKGR_USBDIV_1
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void hal_lld_init(void);
- void at91sam7_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.c b/os/hal/platforms/AT91SAM7/i2c_lld.c deleted file mode 100644 index 1e6e02829..000000000 --- a/os/hal/platforms/AT91SAM7/i2c_lld.c +++ /dev/null @@ -1,450 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file AT91SAM7/i2c_lld.c
- * @brief AT91SAM7 I2C subsystem low level driver source.
- * @note I2C peripheral interrupts on AT91SAM7 platform must have highest
- * priority in system.
- *
- * @addtogroup I2C
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief I2C1 driver identifier.*/
-#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
-I2CDriver I2CD1;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Wakes up the waiting thread.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] msg wakeup message
- *
- * @notapi
- */
-#define wakeup_isr(i2cp, msg) { \
- chSysLockFromIsr(); \
- if ((i2cp)->thread != NULL) { \
- Thread *tp = (i2cp)->thread; \
- (i2cp)->thread = NULL; \
- tp->p_u.rdymsg = (msg); \
- chSchReadyI(tp); \
- } \
- chSysUnlockFromIsr(); \
-}
-
-/**
- * @brief Helper function.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void _i2c_lld_serve_rx_interrupt(I2CDriver *i2cp){
- if (i2cp->rxbytes == 1)
- AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
-
- *(i2cp->rxbuf) = AT91C_BASE_TWI->TWI_RHR;
- i2cp->rxbuf++;
- i2cp->rxbytes--;
- if (i2cp->rxbytes == 0){
- AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_RXRDY;
- AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
- }
-}
-
-/**
- * @brief Helper function.
- * @note During write operation you do not need to set STOP manually.
- * It sets automatically when THR and shift registers becomes empty.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void _i2c_lld_serve_tx_interrupt(I2CDriver *i2cp){
-
- if (i2cp->txbytes == 0){
- AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXRDY;
- AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXCOMP;
- }
- else{
- AT91C_BASE_TWI->TWI_THR = *(i2cp->txbuf);
- i2cp->txbuf++;
- i2cp->txbytes--;
- }
-}
-
-/**
- * @brief I2C shared ISR code.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-static void i2c_lld_serve_interrupt(I2CDriver *i2cp) {
-
- uint32_t sr;
- sr = AT91C_BASE_TWI->TWI_SR;
- /* this masking doing in official Atmel driver. Is it needed ??? */
- sr &= AT91C_BASE_TWI->TWI_IMR;
-
- if (sr & AT91C_TWI_NACK){
- i2cp->errors |= I2CD_ACK_FAILURE;
- wakeup_isr(i2cp, RDY_RESET);
- return;
- }
- if (sr & AT91C_TWI_RXRDY){
- _i2c_lld_serve_rx_interrupt(i2cp);
- }
- else if (sr & AT91C_TWI_TXRDY){
- _i2c_lld_serve_tx_interrupt(i2cp);
- }
- else if (sr & AT91C_TWI_TXCOMP){
- AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP;
- wakeup_isr(i2cp, RDY_OK);
- }
- else
- chDbgPanic("Invalid value");
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SAM7_I2C_USE_I2C1 || defined(__DOXYGEN__)
-/**
- * @brief I2C1 event interrupt handler.
- *
- * @notapi
- */
-CH_IRQ_HANDLER(TWI_IRQHandler) {
-
- CH_IRQ_PROLOGUE();
- i2c_lld_serve_interrupt(&I2CD1);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif /* STM32_I2C_USE_I2C1 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level I2C driver initialization.
- *
- * @notapi
- */
-void i2c_lld_init(void) {
-
-#if SAM7_I2C_USE_I2C1
- i2cObjectInit(&I2CD1);
- I2CD1.thread = NULL;
- I2CD1.txbuf = NULL;
- I2CD1.rxbuf = NULL;
- I2CD1.txbytes = 0;
- I2CD1.rxbytes = 0;
-
- AT91C_BASE_PIOA->PIO_PDR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
- AT91C_BASE_PIOA->PIO_ASR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
- AT91C_BASE_PIOA->PIO_MDER = AT91C_PA0_TWD | AT91C_PA1_TWCK;
- AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PA0_TWD | AT91C_PA1_TWCK;
-
- AIC_ConfigureIT(AT91C_ID_TWI,
- AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | SAM7_I2C_I2C1_IRQ_PRIORITY,
- TWI_IRQHandler);
-#endif /* STM32_I2C_USE_I2C1 */
-}
-
-/**
- * @brief Configures and activates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_start(I2CDriver *i2cp) {
-
- volatile uint32_t fake;
-
- /* If in stopped state then enables the I2C clocks.*/
- if (i2cp->state == I2C_STOP) {
-
-#if SAM7_I2C_USE_I2C1
- if (&I2CD1 == i2cp) {
- /* enable peripheral clock */
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TWI);
-
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_TWI);
-
- /* Reset */
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_SWRST;
- fake = AT91C_BASE_TWI->TWI_RHR;
-
- /* Set master mode */
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSDIS;
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_MSEN;
-
- /* Setup I2C parameters. */
- AT91C_BASE_TWI->TWI_CWGR = i2cp->config->cwgr;
- }
-#endif /* STM32_I2C_USE_I2C1 */
- }
-
- (void)fake;
-}
-
-/**
- * @brief Deactivates the I2C peripheral.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-void i2c_lld_stop(I2CDriver *i2cp) {
-
- /* If not in stopped state then disables the I2C clock.*/
- if (i2cp->state != I2C_STOP) {
-
-#if SAM7_I2C_USE_I2C1
- if (&I2CD1 == i2cp) {
- AT91C_BASE_TWI->TWI_IDR = AT91C_TWI_TXCOMP | AT91C_TWI_RXRDY |
- AT91C_TWI_TXRDY | AT91C_TWI_NACK;
- AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_TWI);
- AIC_DisableIT(AT91C_ID_TWI);
- }
-#endif
- }
-}
-
-/**
- * @brief Receives data via the I2C bus as master.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout this value is ignored on SAM7 platform.
- *
- * @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
- (void)timeout;
-
- /* delete trash from RHR*/
- volatile uint32_t fake;
- fake = AT91C_BASE_TWI->TWI_RHR;
- (void)fake;
-
- /* Initializes driver fields.*/
- i2cp->rxbuf = rxbuf;
- i2cp->rxbytes = rxbytes;
-
- i2cp->txbuf = NULL;
- i2cp->txbytes = 0;
-
- /* tune master mode register */
- AT91C_BASE_TWI->TWI_MMR = 0;
- AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | AT91C_TWI_MREAD;
-
- /* enable just needed interrupts */
- AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK;
-
- /* In single data byte master read or write, the START and STOP must both be set. */
- if (rxbytes == 1)
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START;
- else
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
-
- /* Waits for the operation completion.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
-
- return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief Read data via the I2C bus as master using internal slave addressing.
- * @details Address bytes must be written in special purpose SAM7 registers.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[in] txbuf pointer to the transmit buffer
- * @param[in] txbytes number of bytes to be transmitted
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout this value is ignored on SAM7 platform.
- *
- * @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_transceive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
- (void)timeout;
-
- /* delete trash from RHR*/
- volatile uint32_t fake;
- fake = AT91C_BASE_TWI->TWI_RHR;
- (void)fake;
-
- /* Initializes driver fields.*/
- i2cp->rxbuf = rxbuf;
- i2cp->rxbytes = rxbytes;
-
- /* tune master mode register */
- AT91C_BASE_TWI->TWI_MMR = 0;
- AT91C_BASE_TWI->TWI_MMR |= (addr << 16) | (txbytes << 8) | AT91C_TWI_MREAD;
-
- /* store internal slave address in TWI_IADR registers */
- AT91C_BASE_TWI->TWI_IADR = 0;
- while (txbytes > 0){
- AT91C_BASE_TWI->TWI_IADR = (AT91C_BASE_TWI->TWI_IADR << 8);
- AT91C_BASE_TWI->TWI_IADR |= *(txbuf++);
- txbytes--;
- }
-
- /* enable just needed interrupts */
- AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY | AT91C_TWI_NACK;
-
- /* Internal address of I2C slave was set in special Atmel registers.
- * Now we must call read function. The I2C cell automatically sends
- * bytes from IADR register to bus and issues repeated start. */
- if (rxbytes == 1)
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_START;
- else
- AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START;
-
- /* Waits for the operation completion.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
-
- return chThdSelf()->p_u.rdymsg;
-}
-
-/**
- * @brief Transmits data via the I2C bus as master.
- * @details When performing reading through write you can not write more than
- * 3 bytes of data to I2C slave. This is SAM7 platform limitation.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- * @param[in] addr slave device address
- * @param[in] txbuf pointer to the transmit buffer
- * @param[in] txbytes number of bytes to be transmitted
- * @param[out] rxbuf pointer to the receive buffer
- * @param[in] rxbytes number of bytes to be received
- * @param[in] timeout this value is ignored on SAM7 platform.
- *
- * @return The operation status.
- * @retval RDY_OK if the function succeeded.
- * @retval RDY_RESET if one or more I2C errors occurred, the errors can
- * be retrieved using @p i2cGetErrors().
- *
- * @notapi
- */
-msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout) {
- (void)timeout;
-
- /* SAM7 specific check */
- chDbgCheck(((rxbytes == 0) ||
- ((txbytes > 0) && (txbytes < 4) && (rxbuf != NULL))),
- "i2c_lld_master_transmit_timeout");
-
- /* prepare to read through write operation */
- if (rxbytes > 0){
- return i2c_lld_transceive_timeout(i2cp, addr, txbuf, txbytes, rxbuf,
- rxbytes, timeout);
- }
- else{
- if (txbytes == 1){
- /* In single data byte master read or write, the START and STOP
- * must both be set. */
- AT91C_BASE_TWI->TWI_CR |= AT91C_TWI_STOP;
- }
- AT91C_BASE_TWI->TWI_MMR = 0;
- AT91C_BASE_TWI->TWI_MMR |= addr << 16;
-
- /* enable just needed interrupts */
- AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY | AT91C_TWI_NACK;
-
- /* correct size and pointer because first byte will be written
- * for issue start condition */
- i2cp->txbuf = txbuf + 1;
- i2cp->txbytes = txbytes - 1;
-
- /* According to datasheet there is no need to set START manually
- * we just need to write first byte in THR */
- AT91C_BASE_TWI->TWI_THR = txbuf[0];
-
- /* Waits for the operation completion.*/
- i2cp->thread = chThdSelf();
- chSchGoSleepS(THD_STATE_SUSPENDED);
-
- return chThdSelf()->p_u.rdymsg;
- }
-}
-
-#endif /* HAL_USE_I2C */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/i2c_lld.h b/os/hal/platforms/AT91SAM7/i2c_lld.h deleted file mode 100644 index be4e2f1be..000000000 --- a/os/hal/platforms/AT91SAM7/i2c_lld.h +++ /dev/null @@ -1,204 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- Concepts and parts of this file have been contributed by Uladzimir Pylinsky
- aka barthess.
- */
-
-/**
- * @file AT91SAM7/i2c_lld.h
- * @brief AT91SAM7 I2C subsystem low level driver header.
- *
- * @addtogroup I2C
- * @{
- */
-
-#ifndef _I2C_LLD_H_
-#define _I2C_LLD_H_
-
-#if HAL_USE_I2C || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Peripheral clock frequency.
- */
-#define I2C_CLK_FREQ ((STM32_PCLK1) / 1000000)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief I2C1 driver enable switch.
- * @details If set to @p TRUE the support for I2C1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SAM7_I2C_USE_I2C1) || defined(__DOXYGEN__)
-#define SAM7_I2C_USE_I2C1 FALSE
-#endif
-
-/**
- * @brief I2C1 interrupt priority level setting.
- */
-#if !defined(SAM7_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_I2C_I2C1_IRQ_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/** @brief error checks */
-#if !SAM7_I2C_USE_I2C1
-#error "I2C driver activated but no I2C peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type representing I2C address.
- */
-typedef uint16_t i2caddr_t;
-
-/**
- * @brief I2C Driver condition flags type.
- */
-typedef uint32_t i2cflags_t;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief CWGR regitster content.
- */
- uint32_t cwgr;
-} I2CConfig;
-
-/**
- * @brief Type of a structure representing an I2C driver.
- */
-typedef struct I2CDriver I2CDriver;
-
-/**
- * @brief Structure representing an I2C driver.
- */
-struct I2CDriver{
- /**
- * @brief Driver state.
- */
- i2cstate_t state;
- /**
- * @brief Current configuration data.
- */
- const I2CConfig *config;
- /**
- * @brief Error flags.
- */
- i2cflags_t errors;
- /**
- * @brief Pointer to receive buffer.
- */
- uint8_t *rxbuf;
- /**
- * @brief Pointer to transmit buffer.
- */
- const uint8_t *txbuf;
- /**
- * @brief Bytes count to be received.
- */
- size_t rxbytes;
- /**
- * @brief Bytes count to be transmitted.
- */
- size_t txbytes;
-#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* I2C_USE_MUTUAL_EXCLUSION */
-#if defined(I2C_DRIVER_EXT_FIELDS)
- I2C_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Thread waiting for I/O completion.
- */
- Thread *thread;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Get errors from I2C driver.
- *
- * @param[in] i2cp pointer to the @p I2CDriver object
- *
- * @notapi
- */
-#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-#if SAM7_I2C_USE_I2C1
-extern I2CDriver I2CD1;
-#endif
-
-#endif /* !defined(__DOXYGEN__) */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void i2c_lld_init(void);
- void i2c_lld_start(I2CDriver *i2cp);
- void i2c_lld_stop(I2CDriver *i2cp);
- msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
- const uint8_t *txbuf, size_t txbytes,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
- msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
- uint8_t *rxbuf, size_t rxbytes,
- systime_t timeout);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_I2C */
-
-#endif /* _I2C_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/mac_lld.c b/os/hal/platforms/AT91SAM7/mac_lld.c deleted file mode 100644 index df1e0b88b..000000000 --- a/os/hal/platforms/AT91SAM7/mac_lld.c +++ /dev/null @@ -1,551 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/mac_lld.c
- * @brief AT91SAM7 low level MAC driver code.
- *
- * @addtogroup MAC
- * @{
- */
-
-#include <string.h>
-
-#include "ch.h"
-#include "hal.h"
-#include "mii.h"
-#include "at91sam7_mii.h"
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-#define EMAC_PIN_MASK (AT91C_PB0_ETXCK_EREFCK | AT91C_PB1_ETXEN | \
- AT91C_PB2_ETX0 | AT91C_PB3_ETX1 | \
- AT91C_PB4_ECRS | AT91C_PB5_ERX0 | \
- AT91C_PB6_ERX1 | AT91C_PB7_ERXER | \
- AT91C_PB8_EMDC | AT91C_PB9_EMDIO | \
- AT91C_PB10_ETX2 | AT91C_PB11_ETX3 | \
- AT91C_PB12_ETXER | AT91C_PB13_ERX2 | \
- AT91C_PB14_ERX3 | AT91C_PB15_ERXDV_ECRSDV | \
- AT91C_PB16_ECOL | AT91C_PB17_ERXCK)
-
-#define RSR_BITS (AT91C_EMAC_BNA | AT91C_EMAC_REC | AT91C_EMAC_OVR)
-
-#define TSR_BITS (AT91C_EMAC_UBR | AT91C_EMAC_COL | AT91C_EMAC_RLES | \
- AT91C_EMAC_BEX | AT91C_EMAC_COMP | AT91C_EMAC_UND)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief Ethernet driver 1.
- */
-MACDriver ETHD1;
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#ifndef __DOXYGEN__
-
-static uint8_t default_mac[] = {0xAA, 0x55, 0x13, 0x37, 0x01, 0x10};
-
-static EMACDescriptor *rxptr;
-static EMACDescriptor *txptr;
-static EMACDescriptor rd[EMAC_RECEIVE_DESCRIPTORS]
- __attribute__((aligned(8)));
-static EMACDescriptor td[EMAC_TRANSMIT_DESCRIPTORS]
- __attribute__((aligned(8)));
-static uint8_t rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE]
- __attribute__((aligned(8)));
-static uint8_t tb[EMAC_TRANSMIT_DESCRIPTORS * EMAC_TRANSMIT_BUFFERS_SIZE]
- __attribute__((aligned(8)));
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief IRQ handler.
- */
-/** @cond never*/
-__attribute__((noinline))
-/** @endcond*/
-static void serve_interrupt(void) {
- uint32_t isr, rsr, tsr;
-
- /* Fix for the EMAC errata */
- isr = AT91C_BASE_EMAC->EMAC_ISR;
- rsr = AT91C_BASE_EMAC->EMAC_RSR;
- tsr = AT91C_BASE_EMAC->EMAC_TSR;
-
- if ((isr & AT91C_EMAC_RCOMP) || (rsr & RSR_BITS)) {
- if (rsr & AT91C_EMAC_REC) {
- chSysLockFromIsr();
- chSemResetI(ÐD1.rdsem, 0);
-#if MAC_USE_EVENTS
- chEvtBroadcastI(ÐD1.rdevent);
-#endif
- chSysUnlockFromIsr();
- }
- AT91C_BASE_EMAC->EMAC_RSR = RSR_BITS;
- }
-
- if ((isr & AT91C_EMAC_TCOMP) || (tsr & TSR_BITS)) {
- if (tsr & AT91C_EMAC_COMP) {
- chSysLockFromIsr();
- chSemResetI(ÐD1.tdsem, 0);
- chSysUnlockFromIsr();
- }
- AT91C_BASE_EMAC->EMAC_TSR = TSR_BITS;
- }
- AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-/**
- * @brief Cleans an incomplete frame.
- *
- * @param[in] from the start position of the incomplete frame
- */
-static void cleanup(EMACDescriptor *from) {
-
- while (from != rxptr) {
- from->w1 &= ~W1_R_OWNERSHIP;
- if (++from >= &rd[EMAC_RECEIVE_DESCRIPTORS])
- from = rd;
- }
-}
-
-/**
- * @brief MAC address setup.
- *
- * @param[in] p pointer to a six bytes buffer containing the MAC
- * address
- */
-static void set_address(const uint8_t *p) {
-
- AT91C_BASE_EMAC->EMAC_SA1L = (AT91_REG)((p[3] << 24) | (p[2] << 16) |
- (p[1] << 8) | p[0]);
- AT91C_BASE_EMAC->EMAC_SA1H = (AT91_REG)((p[5] << 8) | p[4]);
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief EMAC IRQ handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(irq_handler) {
-
- CH_IRQ_PROLOGUE();
-
- serve_interrupt();
-
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level MAC initialization.
- *
- * @notapi
- */
-void mac_lld_init(void) {
-
- miiInit();
- macObjectInit(ÐD1);
-
- /*
- * Associated PHY initialization.
- */
- miiReset(ÐD1);
-
- /*
- * EMAC pins setup. Note, PB18 is not included because it is
- * used as #PD control and not as EF100.
- */
- AT91C_BASE_PIOB->PIO_ASR = EMAC_PIN_MASK;
- AT91C_BASE_PIOB->PIO_PDR = EMAC_PIN_MASK;
- AT91C_BASE_PIOB->PIO_PPUDR = EMAC_PIN_MASK;
-}
-
-/**
- * @brief Configures and activates the MAC peripheral.
- *
- * @param[in] macp pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_start(MACDriver *macp) {
- unsigned i;
-
- /*
- * Buffers initialization.
- */
- for (i = 0; i < EMAC_RECEIVE_DESCRIPTORS; i++) {
- rd[i].w1 = (uint32_t)&rb[i * EMAC_RECEIVE_BUFFERS_SIZE];
- rd[i].w2 = 0;
- }
- rd[EMAC_RECEIVE_DESCRIPTORS - 1].w1 |= W1_R_WRAP;
- rxptr = rd;
- for (i = 0; i < EMAC_TRANSMIT_DESCRIPTORS; i++) {
- td[i].w1 = (uint32_t)&tb[i * EMAC_TRANSMIT_BUFFERS_SIZE];
- td[i].w2 = EMAC_TRANSMIT_BUFFERS_SIZE | W2_T_LAST_BUFFER | W2_T_USED;
- }
- td[EMAC_TRANSMIT_DESCRIPTORS - 1].w2 |= W2_T_WRAP;
- txptr = td;
-
- /*
- * EMAC clock enable.
- */
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC;
-
- /*
- * EMAC Initial setup.
- */
- AT91C_BASE_EMAC->EMAC_NCR = 0; /* Stopped but MCE active.*/
- AT91C_BASE_EMAC->EMAC_NCFGR = 2 << 10; /* MDC-CLK = MCK / 32 */
- AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN;/* Enable EMAC in MII mode.*/
- AT91C_BASE_EMAC->EMAC_RBQP = (AT91_REG)rd; /* RX descriptors list.*/
- AT91C_BASE_EMAC->EMAC_TBQP = (AT91_REG)td; /* TX descriptors list.*/
- AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_OVR |
- AT91C_EMAC_REC |
- AT91C_EMAC_BNA; /* Clears RSR.*/
- AT91C_BASE_EMAC->EMAC_NCFGR |= AT91C_EMAC_DRFCS;/* Initial NCFGR settings.*/
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TE |
- AT91C_EMAC_RE |
- AT91C_EMAC_CLRSTAT;/* Initial NCR settings.*/
- if (macp->config->mac_address == NULL)
- set_address(default_mac);
- else
- set_address(macp->config->mac_address);
-
- /*
- * PHY device identification.
- */
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
- if ((miiGet(ÐD1, MII_PHYSID1) != (PHY_ID >> 16)) ||
- ((miiGet(ÐD1, MII_PHYSID2) & 0xFFF0) != (PHY_ID & 0xFFF0)))
- chSysHalt();
- AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
-
- /*
- * Interrupt configuration.
- */
- AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
- AIC_ConfigureIT(AT91C_ID_EMAC,
- AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | EMAC_INTERRUPT_PRIORITY,
- irq_handler);
- AIC_EnableIT(AT91C_ID_EMAC);
-}
-
-/**
- * @brief Deactivates the MAC peripheral.
- *
- * @param[in] macp pointer to the @p MACDriver object
- *
- * @notapi
- */
-void mac_lld_stop(MACDriver *macp) {
-
- (void)macp;
-}
-
-/**
- * @brief Returns a transmission descriptor.
- * @details One of the available transmission descriptors is locked and
- * returned.
- *
- * @param[in] macp pointer to the @p MACDriver object
- * @param[out] tdp pointer to a @p MACTransmitDescriptor structure
- * @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
- MACTransmitDescriptor *tdp) {
- EMACDescriptor *edp;
-
- (void)macp;
-
- if (!macp->link_up)
- return RDY_TIMEOUT;
-
- chSysLock();
- edp = txptr;
- if (!(edp->w2 & W2_T_USED) || (edp->w2 & W2_T_LOCKED)) {
- chSysUnlock();
- return RDY_TIMEOUT;
- }
- /*
- * Set the buffer size and configuration, the buffer is also marked
- * as locked.
- */
- if (++txptr >= &td[EMAC_TRANSMIT_DESCRIPTORS]) {
- edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER | W2_T_WRAP;
- txptr = td;
- }
- else
- edp->w2 = W2_T_LOCKED | W2_T_USED | W2_T_LAST_BUFFER;
- chSysUnlock();
- tdp->offset = 0;
- tdp->size = EMAC_TRANSMIT_BUFFERS_SIZE;
- tdp->physdesc = edp;
- return RDY_OK;
-}
-
-/**
- * @brief Writes to a transmit descriptor's stream.
- *
- * @param[in] tdp pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf pointer to the buffer containing the data to be
- * written
- * @param[in] size number of bytes to be written
- * @return The number of bytes written into the descriptor's
- * stream, this value can be less than the amount
- * specified in the parameter @p size if the maximum
- * frame size is reached.
- *
- * @notapi
- */
-size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
- uint8_t *buf,
- size_t size) {
-
- if (size > tdp->size - tdp->offset)
- size = tdp->size - tdp->offset;
- if (size > 0) {
- memcpy((uint8_t *)(tdp->physdesc->w1 & W1_T_ADDRESS_MASK) +
- tdp->offset,
- buf, size);
- tdp->offset += size;
- }
- return size;
-}
-
-/**
- * @brief Releases a transmit descriptor and starts the transmission of the
- * enqueued data as a single frame.
- *
- * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
-
- chSysLock();
- tdp->physdesc->w2 = (tdp->physdesc->w2 &
- ~(W2_T_LOCKED | W2_T_USED | W2_T_LENGTH_MASK)) |
- tdp->offset;
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
- chSysUnlock();
-}
-
-/**
- * @brief Returns a receive descriptor.
- *
- * @param[in] macp pointer to the @p MACDriver object
- * @param[out] rdp pointer to a @p MACReceiveDescriptor structure
- * @return The operation status.
- * @retval RDY_OK the descriptor has been obtained.
- * @retval RDY_TIMEOUT descriptor not available.
- *
- * @notapi
- */
-msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
- MACReceiveDescriptor *rdp) {
- unsigned n;
- EMACDescriptor *edp;
-
- (void)macp;
- n = EMAC_RECEIVE_DESCRIPTORS;
-
- /*
- * Skips unused buffers, if any.
- */
-skip:
- while ((n > 0) && !(rxptr->w1 & W1_R_OWNERSHIP)) {
- if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
- rxptr = rd;
- n--;
- }
-
- /*
- * Skips fragments, if any, cleaning them up.
- */
- while ((n > 0) && (rxptr->w1 & W1_R_OWNERSHIP) &&
- !(rxptr->w2 & W2_R_FRAME_START)) {
- rxptr->w1 &= ~W1_R_OWNERSHIP;
- if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
- rxptr = rd;
- n--;
- }
-
- /*
- * Now compute the total frame size skipping eventual incomplete frames
- * or holes...
- */
-restart:
- edp = rxptr;
- while (n > 0) {
- if (!(rxptr->w1 & W1_R_OWNERSHIP)) {
- /* Empty buffer for some reason... cleaning up the incomplete frame.*/
- cleanup(edp);
- goto skip;
- }
- /*
- * End Of Frame found.
- */
- if (rxptr->w2 & W2_R_FRAME_END) {
- rdp->offset = 0;
- rdp->size = rxptr->w2 & W2_T_LENGTH_MASK;
- rdp->physdesc = edp;
- return RDY_OK;
- }
-
- if ((edp != rxptr) && (rxptr->w2 & W2_R_FRAME_START)) {
- /* Found another start... cleaning up the incomplete frame.*/
- cleanup(edp);
- goto restart; /* Another start buffer for some reason... */
- }
-
- if (++rxptr >= &rd[EMAC_RECEIVE_DESCRIPTORS])
- rxptr = rd;
- n--;
- }
- return RDY_TIMEOUT;
-}
-
-/**
- * @brief Reads from a receive descriptor's stream.
- *
- * @param[in] rdp pointer to a @p MACReceiveDescriptor structure
- * @param[in] buf pointer to the buffer that will receive the read data
- * @param[in] size number of bytes to be read
- * @return The number of bytes read from the descriptor's
- * stream, this value can be less than the amount
- * specified in the parameter @p size if there are
- * no more bytes to read.
- *
- * @notapi
- */
-size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
- uint8_t *buf,
- size_t size) {
- if (size > rdp->size - rdp->offset)
- size = rdp->size - rdp->offset;
- if (size > 0) {
- uint8_t *src = (uint8_t *)(rdp->physdesc->w1 & W1_R_ADDRESS_MASK) +
- rdp->offset;
- uint8_t *limit = &rb[EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE];
- if (src >= limit)
- src -= EMAC_RECEIVE_DESCRIPTORS * EMAC_RECEIVE_BUFFERS_SIZE;
- if (src + size > limit ) {
- memcpy(buf, src, (size_t)(limit - src));
- memcpy(buf + (size_t)(limit - src), rb, size - (size_t)(limit - src));
- }
- else
- memcpy(buf, src, size);
- rdp->offset += size;
- }
- return size;
-}
-
-/**
- * @brief Releases a receive descriptor.
- * @details The descriptor and its buffer are made available for more incoming
- * frames.
- *
- * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure
- *
- * @notapi
- */
-void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) {
- bool_t done;
- EMACDescriptor *edp = rdp->physdesc;
-
- unsigned n = EMAC_RECEIVE_DESCRIPTORS;
- do {
- done = ((edp->w2 & W2_R_FRAME_END) != 0);
- chDbgAssert(edp->w1 & W1_R_OWNERSHIP,
- "mac_lld_release_receive_descriptor(), #1",
- "found not owned descriptor");
- edp->w1 &= ~(W1_R_OWNERSHIP | W2_R_FRAME_START | W2_R_FRAME_END);
- if (++edp >= &rd[EMAC_RECEIVE_DESCRIPTORS])
- edp = rd;
- n--;
- }
- while ((n > 0) && !done);
- /*
- * Make rxptr point to the descriptor where the next frame will most
- * likely appear.
- */
- rxptr = edp;
-}
-
-/**
- * @brief Updates and returns the link status.
- *
- * @param[in] macp pointer to the @p MACDriver object
- * @return The link status.
- * @retval TRUE if the link is active.
- * @retval FALSE if the link is down.
- *
- * @notapi
- */
-bool_t mac_lld_poll_link_status(MACDriver *macp) {
- uint32_t ncfgr, bmsr, bmcr, lpa;
-
- AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
- (void)miiGet(macp, MII_BMSR);
- bmsr = miiGet(macp, MII_BMSR);
- if (!(bmsr & BMSR_LSTATUS)) {
- AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
- return macp->link_up = FALSE;
- }
-
- ncfgr = AT91C_BASE_EMAC->EMAC_NCFGR & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
- bmcr = miiGet(macp, MII_BMCR);
- if (bmcr & BMCR_ANENABLE) {
- lpa = miiGet(macp, MII_LPA);
- if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4))
- ncfgr |= AT91C_EMAC_SPD;
- if (lpa & (LPA_10FULL | LPA_100FULL))
- ncfgr |= AT91C_EMAC_FD;
- }
- else {
- if (bmcr & BMCR_SPEED100)
- ncfgr |= AT91C_EMAC_SPD;
- if (bmcr & BMCR_FULLDPLX)
- ncfgr |= AT91C_EMAC_FD;
- }
- AT91C_BASE_EMAC->EMAC_NCFGR = ncfgr;
- AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
- return macp->link_up = TRUE;
-}
-
-#endif /* HAL_USE_MAC */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/mac_lld.h b/os/hal/platforms/AT91SAM7/mac_lld.h deleted file mode 100644 index 8a56b6793..000000000 --- a/os/hal/platforms/AT91SAM7/mac_lld.h +++ /dev/null @@ -1,252 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/mac_lld.h
- * @brief AT91SAM7 low level MAC driver header.
- *
- * @addtogroup MAC
- * @{
- */
-
-#ifndef _MAC_LLD_H_
-#define _MAC_LLD_H_
-
-#if HAL_USE_MAC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief This implementation does not support the zero-copy mode API.
- */
-#define MAC_SUPPORTS_ZERO_COPY FALSE
-
-#define EMAC_RECEIVE_BUFFERS_SIZE 128 /* Do not modify */
-#define EMAC_TRANSMIT_BUFFERS_SIZE MAC_BUFFERS_SIZE
-#define EMAC_RECEIVE_DESCRIPTORS \
- (((((MAC_BUFFERS_SIZE - 1) | (EMAC_RECEIVE_BUFFERS_SIZE - 1)) + 1) \
- / EMAC_RECEIVE_BUFFERS_SIZE) * MAC_RECEIVE_BUFFERS)
-#define EMAC_TRANSMIT_DESCRIPTORS MAC_TRANSMIT_BUFFERS
-
-#define W1_R_OWNERSHIP 0x00000001
-#define W1_R_WRAP 0x00000002
-#define W1_R_ADDRESS_MASK 0xFFFFFFFC
-
-#define W2_R_LENGTH_MASK 0x00000FFF
-#define W2_R_FRAME_START 0x00004000
-#define W2_R_FRAME_END 0x00008000
-#define W2_R_CFI 0x00010000
-#define W2_R_VLAN_PRIO_MASK 0x000E0000
-#define W2_R_PRIO_TAG_DETECTED 0x00100000
-#define W2_R_VLAN_TAG_DETECTED 0x00200000
-#define W2_R_TYPE_ID_MATCH 0x00400000
-#define W2_R_ADDR4_MATCH 0x00800000
-#define W2_R_ADDR3_MATCH 0x01000000
-#define W2_R_ADDR2_MATCH 0x02000000
-#define W2_R_ADDR1_MATCH 0x04000000
-#define W2_R_RFU1 0x08000000
-#define W2_R_ADDR_EXT_MATCH 0x10000000
-#define W2_R_UNICAST_MATCH 0x20000000
-#define W2_R_MULTICAST_MATCH 0x40000000
-#define W2_R_BROADCAST_DETECTED 0x80000000
-
-#define W1_T_ADDRESS_MASK 0xFFFFFFFF
-
-#define W2_T_LENGTH_MASK 0x000007FF
-#define W2_T_LOCKED 0x00000800 /* Not an EMAC flag. */
-#define W2_T_RFU1 0x00003000
-#define W2_T_LAST_BUFFER 0x00008000
-#define W2_T_NO_CRC 0x00010000
-#define W2_T_RFU2 0x07FE0000
-#define W2_T_BUFFERS_EXHAUSTED 0x08000000
-#define W2_T_TRANSMIT_UNDERRUN 0x10000000
-#define W2_T_RETRY_LIMIT_EXC 0x20000000
-#define W2_T_WRAP 0x40000000
-#define W2_T_USED 0x80000000
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief Number of available transmit buffers.
- */
-#if !defined(MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define MAC_TRANSMIT_BUFFERS 2
-#endif
-
-/**
- * @brief Number of available receive buffers.
- */
-#if !defined(MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define MAC_RECEIVE_BUFFERS 2
-#endif
-
-/**
- * @brief Maximum supported frame size.
- */
-#if !defined(MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define MAC_BUFFERS_SIZE 1518
-#endif
-
-/**
- * @brief Interrupt priority level for the EMAC device.
- */
-#if !defined(EMAC_INTERRUPT_PRIORITY) || defined(__DOXYGEN__)
-#define EMAC_INTERRUPT_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 3)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Structure representing a buffer physical descriptor.
- * @note It represents both descriptor types.
- */
-typedef struct {
- uint32_t w1;
- uint32_t w2;
-} EMACDescriptor;
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief MAC address.
- */
- const uint8_t *mac_address;
- /* End of the mandatory fields.*/
-} MACConfig;
-
-/**
- * @brief Structure representing a MAC driver.
- */
-struct MACDriver {
- /**
- * @brief Driver state.
- */
- macstate_t state;
- /**
- * @brief Current configuration data.
- */
- const MACConfig *config;
- /**
- * @brief Transmit semaphore.
- */
- Semaphore tdsem;
- /**
- * @brief Receive semaphore.
- */
- Semaphore rdsem;
-#if MAC_USE_EVENTS || defined(__DOXYGEN__)
- /**
- * @brief Receive event.
- */
- EventSource rdevent;
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Link status flag.
- */
- bool_t link_up;
-};
-
-/**
- * @brief Structure representing a transmit descriptor.
- */
-typedef struct {
- /**
- * @brief Current write offset.
- */
- size_t offset;
- /**
- * @brief Available space size.
- */
- size_t size;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the physical descriptor.
- */
- EMACDescriptor *physdesc;
-} MACTransmitDescriptor;
-
-/**
- * @brief Structure representing a receive descriptor.
- */
-typedef struct {
- /**
- * @brief Current read offset.
- */
- size_t offset;
- /**
- * @brief Available data size.
- */
- size_t size;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the first descriptor of the buffers chain.
- */
- EMACDescriptor *physdesc;
-} MACReceiveDescriptor;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern MACDriver ETHD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void mac_lld_init(void);
- void mac_lld_start(MACDriver *macp);
- void mac_lld_stop(MACDriver *macp);
- msg_t mac_lld_get_transmit_descriptor(MACDriver *macp,
- MACTransmitDescriptor *tdp);
- size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp,
- uint8_t *buf,
- size_t size);
- void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp);
- msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
- MACReceiveDescriptor *rdp);
- size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp,
- uint8_t *buf,
- size_t size);
- void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp);
- bool_t mac_lld_poll_link_status(MACDriver *macp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_MAC */
-
-#endif /* _MAC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pal_lld.c b/os/hal/platforms/AT91SAM7/pal_lld.c deleted file mode 100644 index 506d42d22..000000000 --- a/os/hal/platforms/AT91SAM7/pal_lld.c +++ /dev/null @@ -1,150 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/pal_lld.c
- * @brief AT91SAM7 PIO low level driver code.
- *
- * @addtogroup PAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief AT91SAM7 I/O ports configuration.
- * @details PIO registers initialization.
- *
- * @param[in] config the AT91SAM7 ports configuration
- *
- * @notapi
- */
-void _pal_lld_init(const PALConfig *config) {
-
- uint32_t ports = (1 << AT91C_ID_PIOA);
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
- ports |= (1 << AT91C_ID_PIOB);
-#endif
- AT91C_BASE_PMC->PMC_PCER = ports;
-
- /*
- * PIOA setup.
- */
- AT91C_BASE_PIOA->PIO_PPUER = config->P0Data.pusr; /* Pull-up as spec.*/
- AT91C_BASE_PIOA->PIO_PPUDR = ~config->P0Data.pusr;
- AT91C_BASE_PIOA->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/
- AT91C_BASE_PIOA->PIO_ODSR = config->P0Data.odsr; /* Data as specified.*/
- AT91C_BASE_PIOA->PIO_OER = config->P0Data.osr; /* Dir. as specified.*/
- AT91C_BASE_PIOA->PIO_ODR = ~config->P0Data.osr;
- AT91C_BASE_PIOA->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/
- AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/
- AT91C_BASE_PIOA->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/
- AT91C_BASE_PIOA->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/
- AT91C_BASE_PIOA->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/
-
- /*
- * PIOB setup.
- */
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
- AT91C_BASE_PIOB->PIO_PPUER = config->P1Data.pusr; /* Pull-up as spec.*/
- AT91C_BASE_PIOB->PIO_PPUDR = ~config->P1Data.pusr;
- AT91C_BASE_PIOB->PIO_PER = 0xFFFFFFFF; /* PIO enabled.*/
- AT91C_BASE_PIOB->PIO_ODSR = config->P1Data.odsr; /* Data as specified.*/
- AT91C_BASE_PIOB->PIO_OER = config->P1Data.osr; /* Dir. as specified.*/
- AT91C_BASE_PIOB->PIO_ODR = ~config->P1Data.osr;
- AT91C_BASE_PIOB->PIO_IFDR = 0xFFFFFFFF; /* Filter disabled.*/
- AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; /* Int. disabled.*/
- AT91C_BASE_PIOB->PIO_MDDR = 0xFFFFFFFF; /* Push Pull drive.*/
- AT91C_BASE_PIOB->PIO_ASR = 0xFFFFFFFF; /* Peripheral A.*/
- AT91C_BASE_PIOB->PIO_OWER = 0xFFFFFFFF; /* Write enabled.*/
-#endif
-}
-
-/**
- * @brief Pads mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note This function is not meant to be invoked directly from the
- * application code.
- * @note @p PAL_MODE_RESET is implemented as input with pull-up.
- * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- * high state.
- * @note @p PAL_MODE_OUTPUT_OPENDRAIN also enables the pull-up resistor.
- *
- * @param[in] port the port identifier
- * @param[in] mask the group mask
- * @param[in] mode the mode
- *
- * @notapi
- */
-void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode) {
-
- switch (mode) {
- case PAL_MODE_RESET:
- case PAL_MODE_INPUT_PULLUP:
- port->PIO_PPUER = mask;
- port->PIO_ODR = mask;
- break;
- case PAL_MODE_INPUT:
- case PAL_MODE_INPUT_ANALOG:
- port->PIO_PPUDR = mask;
- port->PIO_ODR = mask;
- break;
- case PAL_MODE_UNCONNECTED:
- port->PIO_SODR = mask;
- /* Falls in */
- case PAL_MODE_OUTPUT_PUSHPULL:
- port->PIO_PPUDR = mask;
- port->PIO_OER = mask;
- port->PIO_MDDR = mask;
- break;
- case PAL_MODE_OUTPUT_OPENDRAIN:
- port->PIO_PPUER = mask;
- port->PIO_OER = mask;
- port->PIO_MDER = mask;
- }
-}
-
-#endif /* HAL_USE_PAL */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pal_lld.h b/os/hal/platforms/AT91SAM7/pal_lld.h deleted file mode 100644 index 761a7142a..000000000 --- a/os/hal/platforms/AT91SAM7/pal_lld.h +++ /dev/null @@ -1,256 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/pal_lld.h
- * @brief AT91SAM7 PIO low level driver header.
- *
- * @addtogroup PAL
- * @{
- */
-
-#ifndef _PAL_LLD_H_
-#define _PAL_LLD_H_
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Unsupported modes and specific modes */
-/*===========================================================================*/
-
-#undef PAL_MODE_INPUT_PULLDOWN
-
-/*===========================================================================*/
-/* I/O Ports Types and constants. */
-/*===========================================================================*/
-
-/**
- * @brief PIO port setup info.
- */
-typedef struct {
- /** Initial value for ODSR register (data).*/
- uint32_t odsr;
- /** Initial value for OSR register (direction).*/
- uint32_t osr;
- /** Initial value for PUSR register (Pull-ups).*/
- uint32_t pusr;
-} at91sam7_pio_setup_t;
-
-/**
- * @brief AT91SAM7 PIO static initializer.
- * @details An instance of this structure must be passed to @p palInit() at
- * system startup time in order to initialize the digital I/O
- * subsystem. This represents only the initial setup, specific pads
- * or whole ports can be reprogrammed at later time.
- */
-typedef struct {
- /** @brief Port 0 setup data.*/
- at91sam7_pio_setup_t P0Data;
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \
- defined(__DOXYGEN__)
- /** @brief Port 1 setup data.*/
- at91sam7_pio_setup_t P1Data;
-#endif
-} PALConfig;
-
-/**
- * @brief Width, in bits, of an I/O port.
- */
-#define PAL_IOPORTS_WIDTH 32
-
-/**
- * @brief Whole port mask.
- * @details This macro specifies all the valid bits into a port.
- */
-#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
-
-/**
- * @brief Digital I/O port sized unsigned type.
- */
-typedef uint32_t ioportmask_t;
-
-/**
- * @brief Digital I/O modes.
- */
-typedef uint32_t iomode_t;
-
-/**
- * @brief Port Identifier.
- * @details This type can be a scalar or some kind of pointer, do not make
- * any assumption about it, use the provided macros when populating
- * variables of this type.
- */
-typedef AT91PS_PIO ioportid_t;
-
-/*===========================================================================*/
-/* I/O Ports Identifiers. */
-/*===========================================================================*/
-
-/**
- * @brief PIO port A identifier.
- */
-#define IOPORT1 AT91C_BASE_PIOA
-
-/**
- * @brief PIO port B identifier.
- */
-#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3) || \
- defined(__DOXYGEN__)
-#define IOPORT2 AT91C_BASE_PIOB
-#endif
-
-/*===========================================================================*/
-/* Implementation, some of the following macros could be implemented as */
-/* functions, if so please put them in pal_lld.c. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PAL subsystem initialization.
- *
- * @param[in] config architecture-dependent ports configuration
- *
- * @notapi
- */
-#define pal_lld_init(config) _pal_lld_init(config)
-
-/**
- * @brief Reads the physical I/O port states.
- * @details This function is implemented by reading the PIO_PDSR register, the
- * implementation has no side effects.
- *
- * @param[in] port port identifier
- * @return The port bits.
- *
- * @notapi
- */
-#define pal_lld_readport(port) ((port)->PIO_PDSR)
-
-/**
- * @brief Reads the output latch.
- * @details This function is implemented by reading the PIO_ODSR register, the
- * implementation has no side effects.
- *
- * @param[in] port port identifier
- * @return The latched logical states.
- *
- * @notapi
- */
-#define pal_lld_readlatch(port) ((port)->PIO_ODSR)
-
-/**
- * @brief Writes a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_ODSR register, the
- * implementation has no side effects.
- *
- * @param[in] port the port identifier
- * @param[in] bits the bits to be written on the specified port
- *
- * @notapi
- */
-#define pal_lld_writeport(port, bits) ((port)->PIO_ODSR = (bits))
-
-/**
- * @brief Sets a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_SODR register, the
- * implementation has no side effects.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be ORed on the specified port
- *
- * @notapi
- */
-#define pal_lld_setport(port, bits) ((port)->PIO_SODR = (bits))
-
-/**
- * @brief Clears a bits mask on a I/O port.
- * @details This function is implemented by writing the PIO_CODR register, the
- * implementation has no side effects.
- *
- * @param[in] port port identifier
- * @param[in] bits bits to be cleared on the specified port
- *
- * @notapi
- */
-#define pal_lld_clearport(port, bits) ((port)->PIO_CODR = (bits))
-
-/**
- * @brief Writes a group of bits.
- * @details This function is implemented by writing the PIO_OWER, PIO_ODSR and
- * PIO_OWDR registers, the implementation is not atomic because the
- * multiple accesses.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset the group bit offset within the port
- * @param[in] bits bits to be written. Values exceeding the group
- * width are masked.
- *
- * @notapi
- */
-#define pal_lld_writegroup(port, mask, offset, bits) \
- ((port)->PIO_OWER = (mask) << (offset), \
- (port)->PIO_ODSR = (bits) << (offset), \
- (port)->PIO_OWDR = (mask) << (offset))
-
-/**
- * @brief Pads group mode setup.
- * @details This function programs a pads group belonging to the same port
- * with the specified mode.
- * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with
- * high state.
- *
- * @param[in] port port identifier
- * @param[in] mask group mask
- * @param[in] offset group bit offset within the port
- * @param[in] mode group mode
- *
- * @notapi
- */
-#define pal_lld_setgroupmode(port, mask, offset, mode) \
- _pal_lld_setgroupmode(port, mask << offset, mode)
-
-/**
- * @brief Writes a logical state on an output pad.
- *
- * @param[in] port port identifier
- * @param[in] pad pad number within the port
- * @param[in] bit logical value, the value must be @p PAL_LOW or
- * @p PAL_HIGH
- *
- * @notapi
- */
-#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
-
-extern const PALConfig pal_default_config;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void _pal_lld_init(const PALConfig *config);
- void _pal_lld_setgroupmode(ioportid_t port,
- ioportmask_t mask,
- iomode_t mode);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PAL */
-
-#endif /* _PAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/platform.dox b/os/hal/platforms/AT91SAM7/platform.dox deleted file mode 100644 index b423bb461..000000000 --- a/os/hal/platforms/AT91SAM7/platform.dox +++ /dev/null @@ -1,136 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @defgroup AT91SAM7 AT91SAM7 Drivers
- * @details This section describes all the supported drivers on the AT91SAM7
- * platform and the implementation details of the single drivers.
- *
- * @ingroup platforms
- */
-
-/**
- * @defgroup AT91SAM7_HAL AT91SAM7 Initialization Support
- * @details The AT91SAM7 HAL support is responsible for system initialization.
- *
- * @section at91sam7_hal_1 Supported HW resources
- * - MC.
- * - PMC.
- * .
- * @section at91sam7_hal_2 AT91SAM7 HAL driver implementation features
- * - PLLs startup and stabilization.
- * - Clock source selection.
- * - Flash wait states.
- * .
-* @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_MAC AT91SAM7 MAC Support
- * @details The AT91SAM7 MAC driver supports the EMAC peripheral.
- *
- * @section at91sam7_mac_1 Supported HW resources
- * - EMAC.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_MII AT91SAM7 MII Support
- * @details This driver supports the AT91SAM7 EMAC peripheral communicating
- * with an external PHY transceiver. The driver currently supports
- * the Micrel KS8721 PHY and the Davicom DV9161 modules. This driver
- * is used internally by the MAC driver.
- *
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_PAL AT91SAM7 PAL Support
- * @details The AT91SAM7 PAL driver supports the PIO peripherals.
- *
- * @section at91sam7_pal_1 Supported HW resources
- * - PIOA.
- * - PIOB.
- * .
- * @section at91sam7_pal_2 AT91SAM7 PAL driver implementation features
- * The PAL driver implementation fully supports the following hardware
- * capabilities:
- * - 32 bits wide ports.
- * - Atomic set/reset functions.
- * - Output latched regardless of the pad setting.
- * - Direct read of input pads regardless of the pad setting.
- * .
- * @section at91sam7_pal_3 Supported PAL setup modes
- * The AT91SAM7 PAL driver supports the following I/O modes:
- * - @p PAL_MODE_RESET.
- * - @p PAL_MODE_UNCONNECTED.
- * - @p PAL_MODE_INPUT.
- * - @p PAL_MODE_INPUT_ANALOG (same as @p PAL_MODE_INPUT).
- * - @p PAL_MODE_INPUT_PULLUP.
- * - @p PAL_MODE_OUTPUT_PUSHPULL.
- * - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * .
- * Any attempt to setup an invalid mode is ignored.
- *
- * @section at91sam7_pal_4 Suboptimal behavior
- * The AT91SAM7 PIO is less than optimal in several areas, the limitations
- * should be taken in account while using the PAL driver:
- * - Pad/port toggling operations are not atomic.
- * - Pad/group mode setup is not atomic.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_SERIAL AT91SAM7 Serial Support
- * @details The AT91SAM7 Serial driver uses the USART/UART peripherals in a
- * buffered, interrupt driven, implementation.
- *
- * @section at91sam7_serial_1 Supported HW resources
- * The serial driver can support any of the following hardware resources:
- * - USART1.
- * - USART2.
- * - DBGU.
- * .
- * @section at91sam7_serial_2 AT91SAM7 Serial driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each USART can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Fully interrupt driven.
- * - Programmable priority levels for each USART.
- * .
- * @ingroup AT91SAM7
- */
-
-/**
- * @defgroup AT91SAM7_SPI AT91SAM7 SPI Support
- * @details The SPI driver supports the AT91SAM7 SPI peripherals using DMA
- * channels for maximum performance.
- *
- * @section at91sam7_spi_1 Supported HW resources
- * - SPI1.
- * - SPI2.
- * .
- * @section at91sam7_spi_2 AT91SAM7 SPI driver implementation features
- * - Clock stop for reduced power usage when the driver is in stop state.
- * - Each SPI can be independently enabled and programmed. Unused
- * peripherals are left in low power mode.
- * - Programmable interrupt priority levels for each SPI.
- * - DMA is used for receiving and transmitting.
- * .
- * @ingroup AT91SAM7
- */
diff --git a/os/hal/platforms/AT91SAM7/platform.mk b/os/hal/platforms/AT91SAM7/platform.mk deleted file mode 100644 index 40a71afc9..000000000 --- a/os/hal/platforms/AT91SAM7/platform.mk +++ /dev/null @@ -1,15 +0,0 @@ -# List of all the AT91SAM7 platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/AT91SAM7/hal_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/pal_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/i2c_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/adc_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/ext_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/serial_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/spi_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/mac_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/pwm_lld.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91sam7_mii.c \
- ${CHIBIOS}/os/hal/platforms/AT91SAM7/at91lib/aic.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/AT91SAM7
diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.c b/os/hal/platforms/AT91SAM7/pwm_lld.c deleted file mode 100644 index 7d4060427..000000000 --- a/os/hal/platforms/AT91SAM7/pwm_lld.c +++ /dev/null @@ -1,467 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- This file has been contributed by:
- Andrew Hannam aka inmarket.
-*/
-
-/**
- * @file AT91SAM7/pwm_lld.c
- * @brief AT91SAM7 PWM Driver subsystem low level driver source.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#ifdef UNUSED
-#elif defined(__GNUC__)
-# define UNUSED(x) UNUSED_ ## x __attribute__((unused))
-#elif defined(__LCLINT__)
-# define UNUSED(x) /*@unused@*/ x
-#else
-# define UNUSED(x) x
-#endif
-
-#define PWMC_M ((AT91S_PWMC *)AT91C_PWMC_MR)
-
-#define PWM_MCK_MASK 0x0F00
-#define PWM_MCK_SHIFT 8
-
-typedef struct pindef {
- uint32_t portpin; /* Set to 0 if this pin combination is invalid */
- AT91S_PIO *pio;
- AT91_REG *perab;
-} pindef_t;
-
-typedef struct pwmpindefs {
- pindef_t pin[3];
-} pwmpindefs_t;
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \
- (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP1 = {{
- { AT91C_PA0_PWM0 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
- { AT91C_PA11_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- { AT91C_PA23_PWM0, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- }};
-#endif
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP2 = {{
- { AT91C_PA1_PWM1 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
- { AT91C_PA12_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- { AT91C_PA24_PWM1, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- }};
-#endif
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP3 = {{
- { AT91C_PA2_PWM2 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_ASR },
- { AT91C_PA13_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- { AT91C_PA25_PWM2, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- }};
-#endif
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP4 = {{
- { AT91C_PA7_PWM3 , AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- { AT91C_PA14_PWM3, AT91C_BASE_PIOA, &AT91C_BASE_PIOA->PIO_BSR },
- { 0, 0, 0 },
- }};
-#endif
-
-#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512)
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP1 = {{
- { AT91C_PB19_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
- { AT91C_PB27_PWM0, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
- { 0, 0, 0 },
- }};
-#endif
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP2 = {{
- { AT91C_PB20_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
- { AT91C_PB28_PWM1, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
- { 0, 0, 0 },
- }};
-#endif
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP3 = {{
- { AT91C_PB21_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
- { AT91C_PB29_PWM2, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
- { 0, 0, 0 },
- }};
-#endif
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-static const pwmpindefs_t PWMP4 = {{
- { AT91C_PB22_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_ASR },
- { AT91C_PB30_PWM3, AT91C_BASE_PIOB, &AT91C_BASE_PIOB->PIO_BSR },
- { 0, 0, 0 },
- }};
-#endif
-
-#else
- #error "PWM pins not defined for this SAM7 version"
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief Common IRQ handler.
- */
-static void pwm_lld_serve_interrupt(void) {
- uint32_t isr;
-
- isr = PWMC_M->PWMC_ISR;
-#if PWM_USE_PWM1
- if ((isr & 1) && PWMD1.config->channels[0].callback)
- PWMD1.config->channels[0].callback(&PWMD1);
-#endif
-#if PWM_USE_PWM2
- if ((isr & 2) && PWMD2.config->channels[0].callback)
- PWMD2.config->channels[0].callback(&PWMD2);
-#endif
-#if PWM_USE_PWM3
- if ((isr & 4) && PWMD3.config->channels[0].callback)
- PWMD3.config->channels[0].callback(&PWMD3);
-#endif
-#if PWM_USE_PWM4
- if ((isr & 8) && PWMD4.config->channels[0].callback)
- PWMD4.config->channels[0].callback(&PWMD4);
-#endif
-}
-
-CH_IRQ_HANDLER(PWMIrqHandler) {
- CH_IRQ_PROLOGUE();
- pwm_lld_serve_interrupt();
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
-
- /* Driver initialization.*/
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
- pwmObjectInit(&PWMD1);
- PWMD1.chbit = 1;
- PWMD1.reg = AT91C_BASE_PWMC_CH0;
- PWMD1.pins = &PWMP1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
- pwmObjectInit(&PWMD2);
- PWMD2.chbit = 2;
- PWMD2.reg = AT91C_BASE_PWMC_CH1;
- PWMD2.pins = &PWMP2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
- pwmObjectInit(&PWMD3);
- PWMD3.chbit = 4;
- PWMD3.reg = AT91C_BASE_PWMC_CH2;
- PWMD3.pins = &PWMP3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
- pwmObjectInit(&PWMD4);
- PWMD4.chbit = 8;
- PWMD4.reg = AT91C_BASE_PWMC_CH3;
- PWMD4.pins = &PWMP4;
-#endif
-
- /* Turn on PWM in the power management controller */
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_PWMC);
-
- /* Setup interrupt handler */
- PWMC_M->PWMC_IDR = 0xFFFFFFFF;
- AIC_ConfigureIT(AT91C_ID_PWMC,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_PWM_PRIORITY,
- PWMIrqHandler);
- AIC_EnableIT(AT91C_ID_PWMC);
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
- uint32_t mode, mr, div, pre;
-
- /* Steps:
- 1. Turn the IO pin to a PWM output
- 2. Configuration of Clock if DIVA or DIVB used
- 3. Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
- 4. Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
- 5. Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
- 6. Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in
- PWM_CPRDx Register is possible while the channel is disabled. After validation of the
- channel, the user must use PWM_CUPDx Register to update PWM_CPRDx
- 7. Enable Interrupts (Writing CHIDx in the PWM_IER register)
- */
-
- /* Make sure it is off first */
- pwm_lld_disable_channel(pwmp, 0);
-
- /* Configuration.*/
- mode = pwmp->config->channels[0].mode;
-
- /* Step 1 */
- if (mode & PWM_OUTPUT_PIN1) {
- pwmp->pins->pin[0].perab[0] = pwmp->pins->pin[0].portpin; /* Select A or B peripheral */
- pwmp->pins->pin[0].pio->PIO_PDR = pwmp->pins->pin[0].portpin; /* Turn PIO into PWM output */
- pwmp->pins->pin[0].pio->PIO_MDDR = pwmp->pins->pin[0].portpin; /* Turn off PIO multi-drive */
- if (mode & PWM_DISABLEPULLUP_PIN1)
- pwmp->pins->pin[0].pio->PIO_PPUDR = pwmp->pins->pin[0].portpin; /* Turn off PIO pullup */
- else
- pwmp->pins->pin[0].pio->PIO_PPUER = pwmp->pins->pin[0].portpin; /* Turn on PIO pullup */
- }
- if (mode & PWM_OUTPUT_PIN2) {
- pwmp->pins->pin[1].perab[0] = pwmp->pins->pin[1].portpin;
- pwmp->pins->pin[1].pio->PIO_PDR = pwmp->pins->pin[1].portpin;
- pwmp->pins->pin[1].pio->PIO_MDDR = pwmp->pins->pin[1].portpin;
- if (mode & PWM_DISABLEPULLUP_PIN2)
- pwmp->pins->pin[1].pio->PIO_PPUDR = pwmp->pins->pin[1].portpin;
- else
- pwmp->pins->pin[1].pio->PIO_PPUER = pwmp->pins->pin[1].portpin;
- }
- if ((mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin) {
- pwmp->pins->pin[2].perab[0] = pwmp->pins->pin[2].portpin;
- pwmp->pins->pin[2].pio->PIO_PDR = pwmp->pins->pin[2].portpin;
- pwmp->pins->pin[2].pio->PIO_MDDR = pwmp->pins->pin[2].portpin;
- if (mode & PWM_DISABLEPULLUP_PIN3)
- pwmp->pins->pin[2].pio->PIO_PPUDR = pwmp->pins->pin[2].portpin;
- else
- pwmp->pins->pin[2].pio->PIO_PPUER = pwmp->pins->pin[2].portpin;
- }
-
- /* Step 2 */
- if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKA) {
- if (!pwmp->config->frequency) {
- /* As slow as we go */
- PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (10 << 8) | (255 << 0);
- } else if (pwmp->config->frequency > MCK) {
- /* Just use MCLK */
- mode &= ~PWM_MCK_MASK;
- } else {
- div = MCK / pwmp->config->frequency;
- if (mode & PWM_OUTPUT_CENTER) div >>= 1;
- for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1;
- if (div > 255) div = 255;
- PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0xFFFF0000) | (pre << 8) | (div << 0);
- }
- } else if ((mode & PWM_MCK_MASK) == PWM_MCK_DIV_CLKB) {
- if (!pwmp->config->frequency) {
- /* As slow as we go */
- PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (10 << 24) | (255 << 16);
- } else if (pwmp->config->frequency > MCK) {
- /* Just use MCLK */
- mode &= ~PWM_MCK_MASK;
- } else {
- div = MCK / pwmp->config->frequency;
- if (mode & PWM_OUTPUT_CENTER) div >>= 1;
- for(pre = 0; div > 255 && pre < 10; pre++) div >>= 1;
- if (div > 255) div = 255;
- PWMC_M->PWMC_MR = (PWMC_M->PWMC_MR & 0x0000FFFF) | (pre << 24) | (div << 16);
- }
- }
-
- /* Step 3 -> 5 */
- mr = (mode & PWM_MCK_MASK) >> PWM_MCK_SHIFT;
- if (mode & PWM_OUTPUT_CENTER) mr |= AT91C_PWMC_CALG;
- if (mode & PWM_OUTPUT_ACTIVE_HIGH) mr |= AT91C_PWMC_CPOL;
- pwmp->reg->PWMC_CMR = mr;
-
- /* Step 6 */
- pwmp->reg->PWMC_CPRDR = pwmp->period;
-
- /* Step 7 */
- if (pwmp->config->channels[0].callback)
- PWMC_M->PWMC_IER = pwmp->chbit;
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
- /* Make sure it is off */
- pwm_lld_disable_channel(pwmp, 0);
-
- /* Turn the pin back to a PIO pin - we have forgotten pull-up and multi-drive state for the pin though */
- if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN1)
- pwmp->pins->pin[0].pio->PIO_PER = pwmp->pins->pin[0].portpin;
- if (pwmp->config->channels[0].mode & PWM_OUTPUT_PIN2)
- pwmp->pins->pin[1].pio->PIO_PER = pwmp->pins->pin[1].portpin;
- if ((pwmp->config->channels[0].mode & PWM_OUTPUT_PIN3) && pwmp->pins->pin[2].portpin)
- pwmp->pins->pin[2].pio->PIO_PER = pwmp->pins->pin[2].portpin;
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
- pwmp->period = period;
-
- if (PWMC_M->PWMC_SR & pwmp->chbit) {
- pwmp->reg->PWMC_CMR |= AT91C_PWMC_CPD;
- pwmp->reg->PWMC_CUPDR = period;
- } else {
- pwmp->reg->PWMC_CPRDR = period;
- }
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t UNUSED(channel),
- pwmcnt_t width) {
- /*
- 6. Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register).
- Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of
- the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx.
- 7. Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
- */
-
- /* Step 6 */
- if (PWMC_M->PWMC_SR & pwmp->chbit) {
- pwmp->reg->PWMC_CMR &= ~AT91C_PWMC_CPD;
- pwmp->reg->PWMC_CUPDR = width;
- } else {
- pwmp->reg->PWMC_CDTYR = width;
- PWMC_M->PWMC_ENA = pwmp->chbit;
- }
-
- /* Step 7 */
- PWMC_M->PWMC_ENA = pwmp->chbit;
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t UNUSED(channel)) {
- PWMC_M->PWMC_IDR = pwmp->chbit;
- PWMC_M->PWMC_DIS = pwmp->chbit;
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/pwm_lld.h b/os/hal/platforms/AT91SAM7/pwm_lld.h deleted file mode 100644 index cb1a830ff..000000000 --- a/os/hal/platforms/AT91SAM7/pwm_lld.h +++ /dev/null @@ -1,284 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-/*
- This file has been contributed by:
- Andrew Hannam aka inmarket.
-*/
-/**
- * @file AT91SAM7/pwm_lld.h
- * @brief AT91SAM7 PWM Driver subsystem low level driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 1
-
-/**
- * @brief PWM device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_PWM_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_PWM_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 4)
-#endif
-
-/**
- * @brief PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM1) || defined(__DOXYGEN__)
-#define PWM_USE_PWM1 TRUE
-#endif
-
-/**
- * @brief PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM2) || defined(__DOXYGEN__)
-#define PWM_USE_PWM2 TRUE
-#endif
-
-/**
- * @brief PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM3) || defined(__DOXYGEN__)
-#define PWM_USE_PWM3 TRUE
-#endif
-
-/**
- * @brief PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(PWM_USE_PWM4) || defined(__DOXYGEN__)
-#define PWM_USE_PWM4 TRUE
-#endif
-
-/**
- * @brief PWM left (count up) logic
- */
-#define PWM_OUTPUT_LEFT 0x00000000
-
-/**
- * @brief PWM center (count up-down) logic. Gives symetric waveform
- */
-#define PWM_OUTPUT_CENTER 0x00000010
-
-/**
- * @brief PWM Master Clock = MCK / 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, CLKA or CLKB. CLKA or CLKB uses the frequency field
- */
-#define PWM_MCK_DIV_1 0x00000000
-#define PWM_MCK_DIV_2 0x00000100
-#define PWM_MCK_DIV_4 0x00000200
-#define PWM_MCK_DIV_8 0x00000300
-#define PWM_MCK_DIV_16 0x00000400
-#define PWM_MCK_DIV_32 0x00000500
-#define PWM_MCK_DIV_64 0x00000600
-#define PWM_MCK_DIV_128 0x00000700
-#define PWM_MCK_DIV_256 0x00000800
-#define PWM_MCK_DIV_512 0x00000900
-#define PWM_MCK_DIV_1024 0x00000A00
-#define PWM_MCK_DIV_CLKA 0x00000B00
-#define PWM_MCK_DIV_CLKB 0x00000C00
-
-/**
- * @brief Which PWM output pins to turn on. PIN1 is the lowest numbered pin, PIN2 next lowest, and then on some packages PIN3.
- */
-#define PWM_OUTPUT_PIN1 0x00001000
-#define PWM_OUTPUT_PIN2 0x00002000
-#define PWM_OUTPUT_PIN3 0x00004000
-
-/**
- * @brief Which PWM output pins should have pullups disabled.
- */
-#define PWM_DISABLEPULLUP_PIN1 0x00010000
-#define PWM_DISABLEPULLUP_PIN2 0x00020000
-#define PWM_DISABLEPULLUP_PIN3 0x00040000
-
- /*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief PWM counter type.
- */
-typedef uint16_t pwmcnt_t;
-
-/**
- * @brief PWM driver channel configuration structure.
- * @note Some architectures may not be able to support the channel mode
- * or the callback, in this case the fields are ignored.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
-} PWMConfig;
-
-/**
- * @brief Structure representing an PWM driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
-
- /* End of the mandatory fields.*/
-
- /**
- * @brief The PWM internal channel number as a bit mask (1, 2, 4 or 8).
- */
- uint32_t chbit;
- /**
- * @brief Pointer to the PWMCx registers block.
- */
- AT91S_PWMC_CH *reg;
- /**
- * @brief Pointer to the output pins descriptor.
- */
- const struct pwmpindefs *pins;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if PWM_USE_PWM1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if PWM_USE_PWM2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if PWM_USE_PWM3 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if PWM_USE_PWM4 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/serial_lld.c b/os/hal/platforms/AT91SAM7/serial_lld.c deleted file mode 100644 index e586a6342..000000000 --- a/os/hal/platforms/AT91SAM7/serial_lld.c +++ /dev/null @@ -1,444 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/serial_lld.c
- * @brief AT91SAM7 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \
- (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
-
-#define SAM7_USART0_RX AT91C_PA5_RXD0
-#define SAM7_USART0_TX AT91C_PA6_TXD0
-#define SAM7_USART1_RX AT91C_PA21_RXD1
-#define SAM7_USART1_TX AT91C_PA22_TXD1
-#define SAM7_DBGU_RX AT91C_PA9_DRXD
-#define SAM7_DBGU_TX AT91C_PA10_DTXD
-
-#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
- (SAM7_PLATFORM == SAM7X512)
-
-#define SAM7_USART0_RX AT91C_PA0_RXD0
-#define SAM7_USART0_TX AT91C_PA1_TXD0
-#define SAM7_USART1_RX AT91C_PA5_RXD1
-#define SAM7_USART1_TX AT91C_PA6_TXD1
-#define SAM7_DBGU_RX AT91C_PA27_DRXD
-#define SAM7_DBGU_TX AT91C_PA28_DTXD
-
-#elif (SAM7_PLATFORM == SAM7A3)
-#define SAM7_USART0_RX AT91C_PA2_RXD0
-#define SAM7_USART0_TX AT91C_PA3_TXD0
-#define SAM7_USART1_RX AT91C_PA7_RXD1
-#define SAM7_USART1_TX AT91C_PA8_TXD1
-#define SAM7_USART2_RX AT91C_PA9_RXD2
-#define SAM7_USART2_TX AT91C_PA10_TXD2
-#define SAM7_DBGU_RX AT91C_PA30_DRXD
-#define SAM7_DBGU_TX AT91C_PA31_DTXD
-
-#else
-#error "serial lines not defined for this SAM7 version"
-#endif /* HAL_USE_SERIAL */
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-/** @brief USART0 serial driver identifier.*/
-SerialDriver SD1;
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-/** @brief USART1 serial driver identifier.*/
-SerialDriver SD2;
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-/** @brief USART2 serial driver identifier.*/
-SerialDriver SD3;
-#endif
-#endif
-
-#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__)
-/** @brief DBGU_UART serial driver identifier.*/
-SerialDriver SDDBG;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config = {
- SERIAL_DEFAULT_BITRATE,
- AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
- AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief USART initialization.
- *
- * @param[in] sdp communication channel associated to the USART
- * @param[in] config the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
- AT91PS_USART u = sdp->usart;
-
- /* Disables IRQ sources and stop operations.*/
- u->US_IDR = 0xFFFFFFFF;
- u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA;
-
- /* New parameters setup.*/
- if (config->sc_mr & AT91C_US_OVER)
- u->US_BRGR = MCK / (config->sc_speed * 8);
- else
- u->US_BRGR = MCK / (config->sc_speed * 16);
- u->US_MR = config->sc_mr;
- u->US_RTOR = 0;
- u->US_TTGR = 0;
-
- /* Enables operations and IRQ sources.*/
- u->US_CR = AT91C_US_RXEN | AT91C_US_TXEN | AT91C_US_DTREN | AT91C_US_RTSEN;
- u->US_IER = AT91C_US_RXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE |
- AT91C_US_RXBRK;
-}
-
-/**
- * @brief USART de-initialization.
- *
- * @param[in] u pointer to an USART I/O block
- */
-static void usart_deinit(AT91PS_USART u) {
-
- /* Disables IRQ sources and stop operations.*/
- u->US_IDR = 0xFFFFFFFF;
- u->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RSTSTA;
- u->US_MR = 0;
- u->US_RTOR = 0;
- u->US_TTGR = 0;
-}
-
-/**
- * @brief Error handling routine.
- *
- * @param[in] err USART CSR register value
- * @param[in] sdp communication channel associated to the USART
- */
-static void set_error(SerialDriver *sdp, AT91_REG csr) {
- flagsmask_t sts = 0;
-
- if (csr & AT91C_US_OVRE)
- sts |= SD_OVERRUN_ERROR;
- if (csr & AT91C_US_PARE)
- sts |= SD_PARITY_ERROR;
- if (csr & AT91C_US_FRAME)
- sts |= SD_FRAMING_ERROR;
- if (csr & AT91C_US_RXBRK)
- sts |= SD_BREAK_DETECTED;
- chSysLockFromIsr();
- chnAddFlagsI(sdp, sts);
- chSysUnlockFromIsr();
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-#if !USE_SAM7_DBGU_UART
-static
-#endif
-/**
- * @brief Common IRQ handler.
- *
- * @param[in] sdp communication channel associated to the USART
- */
-void sd_lld_serve_interrupt(SerialDriver *sdp) {
- uint32_t csr;
- AT91PS_USART u = sdp->usart;
-
- csr = u->US_CSR;
- if (csr & AT91C_US_RXRDY) {
- chSysLockFromIsr();
- sdIncomingDataI(sdp, u->US_RHR);
- chSysUnlockFromIsr();
- }
- if ((u->US_IMR & AT91C_US_TXRDY) && (csr & AT91C_US_TXRDY)) {
- msg_t b;
-
- chSysLockFromIsr();
- b = chOQGetI(&sdp->oqueue);
- if (b < Q_OK) {
- chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
- u->US_IDR = AT91C_US_TXRDY;
- }
- else
- u->US_THR = b;
- chSysUnlockFromIsr();
- }
- csr &= (AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK);
- if (csr != 0) {
- set_error(sdp, csr);
- u->US_CR = AT91C_US_RSTSTA;
- }
- AT91C_BASE_AIC->AIC_EOICR = 0;
-}
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
- (void)qp;
- AT91C_BASE_US0->US_IER = AT91C_US_TXRDY;
-}
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
- (void)qp;
- AT91C_BASE_US1->US_IER = AT91C_US_TXRDY;
-}
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-static void notify3(GenericQueue *qp) {
-
- (void)qp;
- AT91C_BASE_US2->US_IER = AT91C_US_TXRDY;
-}
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-#if USE_SAM7_DBGU_UART || defined(__DOXYGEN__)
-static void notify_dbg(GenericQueue *qp) {
-
- (void)qp;
- AT91C_BASE_DBGU->DBGU_IER = AT91C_US_TXRDY;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 || defined(__DOXYGEN__)
-/**
- * @brief USART0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART0IrqHandler) {
-
- CH_IRQ_PROLOGUE();
- sd_lld_serve_interrupt(&SD1);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if USE_SAM7_USART1 || defined(__DOXYGEN__)
-/**
- * @brief USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART1IrqHandler) {
-
- CH_IRQ_PROLOGUE();
- sd_lld_serve_interrupt(&SD2);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 || defined(__DOXYGEN__)
-/**
- * @brief USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART2IrqHandler) {
-
- CH_IRQ_PROLOGUE();
- sd_lld_serve_interrupt(&SD3);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/* note - DBGU_UART IRQ is the SysIrq in board.c
- since it's not vectored separately by the AIC.*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if USE_SAM7_USART0
- sdObjectInit(&SD1, NULL, notify1);
- SD1.usart = AT91C_BASE_US0;
- AT91C_BASE_PIOA->PIO_PDR = SAM7_USART0_RX | SAM7_USART0_TX;
- AT91C_BASE_PIOA->PIO_ASR = SAM7_USART0_RX | SAM7_USART0_TX;
- AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART0_RX | SAM7_USART0_TX;
- AIC_ConfigureIT(AT91C_ID_US0,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART0_PRIORITY,
- USART0IrqHandler);
-#endif
-
-#if USE_SAM7_USART1
- sdObjectInit(&SD2, NULL, notify2);
- SD2.usart = AT91C_BASE_US1;
- AT91C_BASE_PIOA->PIO_PDR = SAM7_USART1_RX | SAM7_USART1_TX;
- AT91C_BASE_PIOA->PIO_ASR = SAM7_USART1_RX | SAM7_USART1_TX;
- AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART1_RX | SAM7_USART1_TX;
- AIC_ConfigureIT(AT91C_ID_US1,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART1_PRIORITY,
- USART1IrqHandler);
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2
- sdObjectInit(&SD3, NULL, notify3);
- SD3.usart = AT91C_BASE_US2;
- AT91C_BASE_PIOA->PIO_PDR = SAM7_USART2_RX | SAM7_USART2_TX;
- AT91C_BASE_PIOA->PIO_ASR = SAM7_USART2_RX | SAM7_USART2_TX;
- AT91C_BASE_PIOA->PIO_PPUDR = SAM7_USART2_RX | SAM7_USART2_TX;
- AIC_ConfigureIT(AT91C_ID_US2,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | SAM7_USART2_PRIORITY,
- USART2IrqHandler);
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-#if USE_SAM7_DBGU_UART
- sdObjectInit(&SDDBG, NULL, notify_dbg);
- /* this is a little cheap, but OK for now since there's enough overlap
- between dbgu and usart register maps. it means we can reuse all the
- same usart interrupt handling and config that already exists.*/
- SDDBG.usart = (AT91PS_USART)AT91C_BASE_DBGU;
- AT91C_BASE_PIOA->PIO_PDR = SAM7_DBGU_RX | SAM7_DBGU_TX;
- AT91C_BASE_PIOA->PIO_ASR = SAM7_DBGU_RX | SAM7_DBGU_TX;
- AT91C_BASE_PIOA->PIO_PPUDR = SAM7_DBGU_RX | SAM7_DBGU_TX;
-#endif
-}
-
-/**
- * @brief Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- * @param[in] config the architecture-dependent serial driver configuration.
- * If this parameter is set to @p NULL then a default
- * configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
- if (config == NULL)
- config = &default_config;
-
- if (sdp->state == SD_STOP) {
-#if USE_SAM7_USART0
- if (&SD1 == sdp) {
- /* Starts the clock and clears possible sources of immediate interrupts.*/
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US0);
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_US0);
- }
-#endif
-#if USE_SAM7_USART1
- if (&SD2 == sdp) {
- /* Starts the clock and clears possible sources of immediate interrupts.*/
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US1);
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_US1);
- }
-#endif
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2
- if (&SD3 == sdp) {
- /* Starts the clock and clears possible sources of immediate interrupts.*/
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_US2);
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_US2);
- }
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
- /* Note - no explicit start for SD3 (DBGU_UART) since it's not included
- in the AIC or PMC.*/
- }
- usart_init(sdp, config);
-}
-
-/**
- * @brief Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- * interrupt vector.
- *
- * @param[in] sdp pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
- if (sdp->state == SD_READY) {
- usart_deinit(sdp->usart);
-#if USE_SAM7_USART0
- if (&SD1 == sdp) {
- AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US0);
- AIC_DisableIT(AT91C_ID_US0);
- return;
- }
-#endif
-#if USE_SAM7_USART1
- if (&SD2 == sdp) {
- AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_US1);
- AIC_DisableIT(AT91C_ID_US1);
- return;
- }
-#endif
-#if USE_SAM7_DBGU_UART
- if (&SDDBG == sdp) {
- AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF;
- return;
- }
-#endif
- }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/serial_lld.h b/os/hal/platforms/AT91SAM7/serial_lld.h deleted file mode 100644 index 9b25b2be3..000000000 --- a/os/hal/platforms/AT91SAM7/serial_lld.h +++ /dev/null @@ -1,191 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/serial_lld.h
- * @brief AT91SAM7 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief UART0 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART0) || defined(__DOXYGEN__)
-#define USE_SAM7_USART0 TRUE
-#endif
-
-/**
- * @brief UART1 driver enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART1) || defined(__DOXYGEN__)
-#define USE_SAM7_USART1 TRUE
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief UART2 driver enable switch.
- * @details If set to @p TRUE the support for USART3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(USE_SAM7_USART2) || defined(__DOXYGEN__)
-#define USE_SAM7_USART2 TRUE
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/**
- * @brief DBGU UART driver enable switch.
- * @details If set to @p TRUE the support for the DBGU UART is included.
- * @note The default is @p TRUE.
- */
-#if !defined(USE_SAM7_DBGU_UART) || defined(__DOXYGEN__)
-#define USE_SAM7_DBGU_UART TRUE
-#endif
-
-/**
- * @brief UART1 interrupt priority level setting.
- */
-#if !defined(SAM7_USART0_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/**
- * @brief UART2 interrupt priority level setting.
- */
-#if !defined(SAM7_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-#if (SAM7_PLATFORM == SAM7A3)
-/**
- * @brief UART2 interrupt priority level setting.
- */
-#if !defined(SAM7_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_USART2_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-#endif /* (SAM7_PLATFORM == SAM7A3) */
-
-/**
- * @brief DBGU_UART interrupt priority level setting.
- */
-#if !defined(SAM7_DBGU_UART_PRIORITY) || defined(__DOXYGEN__)
-#define SAM7_DBGU_UART_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 2)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief AT91SAM7 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- * in order to configure and start a serial driver operations.
- */
-typedef struct {
- /**
- * @brief Bit rate.
- * @details This is written to the US_BRGR register of the appropriate AT91S_USART
- */
- uint32_t sc_speed;
- /**
- * @brief Initialization value for the MR register.
- * @details This is written to the US_MR register of the appropriate AT91S_USART
- */
- uint32_t sc_mr;
-} SerialConfig;
-
-/**
- * @brief @p SerialDriver specific data.
- */
-#define _serial_driver_data \
- _base_asynchronous_channel_data \
- /* Driver state.*/ \
- sdstate_t state; \
- /* Input queue.*/ \
- InputQueue iqueue; \
- /* Output queue.*/ \
- OutputQueue oqueue; \
- /* Input circular buffer.*/ \
- uint8_t ib[SERIAL_BUFFERS_SIZE]; \
- /* Output circular buffer.*/ \
- uint8_t ob[SERIAL_BUFFERS_SIZE]; \
- /* End of the mandatory fields.*/ \
- /* Pointer to the USART registers block.*/ \
- AT91PS_USART usart;
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if USE_SAM7_USART0 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if USE_SAM7_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-#if (SAM7_PLATFORM == SAM7A3)
-#if USE_SAM7_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD3;
-#endif
-#endif
-#if USE_SAM7_DBGU_UART
-extern SerialDriver SDDBG;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void sd_lld_init(void);
- void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
- void sd_lld_stop(SerialDriver *sdp);
-#if USE_SAM7_DBGU_UART
- void sd_lld_serve_interrupt(SerialDriver *sdp);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/spi_lld.c b/os/hal/platforms/AT91SAM7/spi_lld.c deleted file mode 100644 index a2ffcfd2e..000000000 --- a/os/hal/platforms/AT91SAM7/spi_lld.c +++ /dev/null @@ -1,397 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/spi_lld.c
- * @brief AT91SAM7 low level SPI driver code.
- *
- * @addtogroup SPI
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/** @brief SPI1 driver identifier.*/
-SPIDriver SPID1;
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/** @brief SPI2 driver identifier.*/
-SPIDriver SPID2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Idle line value.
- * @details This thing's DMA apparently does not allow to *not* increment
- * the memory pointer so a buffer filled with ones is required
- * somewhere.
- * @note This buffer size also limits the maximum transfer size, 512B,
- * for @p spiReceive() and @p spiIgnore(). @p spiSend() and
- * @p spiExchange are not affected.
- */
-static const uint16_t idle_buf[] = {
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
- 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF
-};
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief Initializes a SPI device.
- */
-static void spi_init(AT91PS_SPI spi) {
-
- /* Software reset must be written twice (errata for revision B parts).*/
- spi->SPI_CR = AT91C_SPI_SWRST;
- spi->SPI_CR = AT91C_SPI_SWRST;
- spi->SPI_RCR = 0;
- spi->SPI_RNCR = 0;
- spi->SPI_TCR = 0;
- spi->SPI_TNCR = 0;
- spi->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
- spi->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS;
-}
-
-#if defined(__GNUC__)
-__attribute__((noinline))
-#endif
-/**
- * @brief Shared interrupt handling code.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- */
-static void spi_lld_serve_interrupt(SPIDriver *spip) {
- uint32_t sr = spip->spi->SPI_SR;
-
- if ((sr & AT91C_SPI_ENDRX) != 0) {
- (void)spip->spi->SPI_RDR; /* Clears eventual overflow.*/
- spip->spi->SPI_PTCR = AT91C_PDC_RXTDIS |
- AT91C_PDC_TXTDIS; /* PDC disabled. */
- spip->spi->SPI_IDR = AT91C_SPI_ENDRX; /* Interrupt disabled. */
- spip->spi->SPI_CR = AT91C_SPI_SPIDIS; /* SPI disabled. */
- /* Portable SPI ISR code defined in the high level driver, note, it is
- a macro.*/
- _spi_isr_code(spip);
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 || defined(__DOXYGEN__)
-/**
- * @brief SPI0 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPI0IrqHandler) {
-
- CH_IRQ_PROLOGUE();
- spi_lld_serve_interrupt(&SPID1);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 || defined(__DOXYGEN__)
-/**
- * @brief SPI1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPI1IrqHandler) {
-
- CH_IRQ_PROLOGUE();
- spi_lld_serve_interrupt(&SPID2);
- AT91C_BASE_AIC->AIC_EOICR = 0;
- CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level SPI driver initialization.
- *
- * @notapi
- */
-void spi_lld_init(void) {
-
-#if AT91SAM7_SPI_USE_SPI0
- spiObjectInit(&SPID1);
- SPID1.spi = AT91C_BASE_SPI0;
- spi_init(AT91C_BASE_SPI0);
- AT91C_BASE_PIOA->PIO_PDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
- AT91C_BASE_PIOA->PIO_ASR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
- AT91C_BASE_PIOA->PIO_PPUDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
- AIC_ConfigureIT(AT91C_ID_SPI0,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI0_PRIORITY,
- SPI0IrqHandler);
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1
- spiObjectInit(&SPID2);
- SPID2.spi = AT91C_BASE_SPI1;
- spi_init(AT91C_BASE_SPI1);
- AT91C_BASE_PIOA->PIO_PDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
- AT91C_BASE_PIOA->PIO_BSR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
- AT91C_BASE_PIOA->PIO_PPUDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
- AIC_ConfigureIT(AT91C_ID_SPI1,
- AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI1_PRIORITY,
- SPI1IrqHandler);
-#endif
-}
-
-/**
- * @brief Configures and activates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_start(SPIDriver *spip) {
-
- if (spip->state == SPI_STOP) {
-#if AT91SAM7_SPI_USE_SPI0
- if (&SPID1 == spip) {
- /* Clock activation.*/
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI0);
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_SPI0);
- }
-#endif
-#if AT91SAM7_SPI_USE_SPI1
- if (&SPID2 == spip) {
- /* Clock activation.*/
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SPI1);
- /* Enables associated interrupt vector.*/
- AIC_EnableIT(AT91C_ID_SPI1);
- }
-#endif
- }
- /* Configuration.*/
- spip->spi->SPI_CSR[0] = spip->config->csr;
-}
-
-/**
- * @brief Deactivates the SPI peripheral.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_stop(SPIDriver *spip) {
-
- if (spip->state != SPI_STOP) {
-#if AT91SAM7_SPI_USE_SPI0
- if (&SPID1 == spip) {
- AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI0);
- AIC_DisableIT(AT91C_ID_SPI0);
- }
-#endif
-#if AT91SAM7_SPI_USE_SPI1
- if (&SPID1 == spip) {
- AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_SPI1);
- AIC_DisableIT(AT91C_ID_SPI0);
- }
-#endif
- }
-}
-
-/**
- * @brief Asserts the slave select signal and prepares for transfers.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_select(SPIDriver *spip) {
-
- palClearPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Deasserts the slave select signal.
- * @details The previously selected peripheral is unselected.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- *
- * @notapi
- */
-void spi_lld_unselect(SPIDriver *spip) {
-
- palSetPad(spip->config->ssport, spip->config->sspad);
-}
-
-/**
- * @brief Ignores data on the SPI bus.
- * @details This function transmits a series of idle words on the SPI bus and
- * ignores the received data. This function can be invoked even
- * when a slave select signal has not been yet asserted.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be ignored
- *
- * @notapi
- */
-void spi_lld_ignore(SPIDriver *spip, size_t n) {
-
- spip->spi->SPI_TCR = n;
- spip->spi->SPI_RCR = n;
- spip->spi->SPI_TPR = (AT91_REG)idle_buf;
- spip->spi->SPI_RPR = (AT91_REG)idle_buf;
- spip->spi->SPI_IER = AT91C_SPI_ENDRX;
- spip->spi->SPI_CR = AT91C_SPI_SPIEN;
- spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief Exchanges data on the SPI bus.
- * @details This function performs a simultaneous transmit/receive operation.
- * @note The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to be exchanged
- * @param[in] txbuf the pointer to the transmit buffer
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf) {
-
- spip->spi->SPI_TCR = n;
- spip->spi->SPI_RCR = n;
- spip->spi->SPI_TPR = (AT91_REG)txbuf;
- spip->spi->SPI_RPR = (AT91_REG)rxbuf;
- spip->spi->SPI_IER = AT91C_SPI_ENDRX;
- spip->spi->SPI_CR = AT91C_SPI_SPIEN;
- spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief Sends data over the SPI bus.
- * @note The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to send
- * @param[in] txbuf the pointer to the transmit buffer
- *
- * @notapi
- */
-void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
-
- spip->spi->SPI_TCR = n;
- spip->spi->SPI_RCR = n;
- spip->spi->SPI_TPR = (AT91_REG)txbuf;
- spip->spi->SPI_RPR = (AT91_REG)idle_buf;
- spip->spi->SPI_IER = AT91C_SPI_ENDRX;
- spip->spi->SPI_CR = AT91C_SPI_SPIEN;
- spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief Receives data from the SPI bus.
- * @note The buffers are organized as uint8_t arrays.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] n number of words to receive
- * @param[out] rxbuf the pointer to the receive buffer
- *
- * @notapi
- */
-void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
-
- spip->spi->SPI_TCR = n;
- spip->spi->SPI_RCR = n;
- spip->spi->SPI_TPR = (AT91_REG)idle_buf;
- spip->spi->SPI_RPR = (AT91_REG)rxbuf;
- spip->spi->SPI_IER = AT91C_SPI_ENDRX;
- spip->spi->SPI_CR = AT91C_SPI_SPIEN;
- spip->spi->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
-}
-
-/**
- * @brief Exchanges one frame using a polled wait.
- * @details This synchronous function exchanges one frame using a polled
- * synchronization method. This function is useful when exchanging
- * small amount of data on high speed channels, usually in this
- * situation is much more efficient just wait for completion using
- * polling than suspending the thread waiting for an interrupt.
- *
- * @param[in] spip pointer to the @p SPIDriver object
- * @param[in] frame the data frame to send over the SPI bus
- * @return The received data frame from the SPI bus.
- */
-uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
-
- spip->spi->SPI_CR = AT91C_SPI_SPIEN;
- spip->spi->SPI_TDR = frame;
- while ((spip->spi->SPI_SR & AT91C_SPI_RDRF) == 0)
- ;
- return spip->spi->SPI_RDR;
-}
-
-#endif /* HAL_USE_SPI */
-
-/** @} */
diff --git a/os/hal/platforms/AT91SAM7/spi_lld.h b/os/hal/platforms/AT91SAM7/spi_lld.h deleted file mode 100644 index fda7adbbf..000000000 --- a/os/hal/platforms/AT91SAM7/spi_lld.h +++ /dev/null @@ -1,219 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file AT91SAM7/spi_lld.h
- * @brief AT91SAM7 low level SPI driver header.
- *
- * @addtogroup SPI
- * @{
- */
-
-#ifndef _SPI_LLD_H_
-#define _SPI_LLD_H_
-
-#if HAL_USE_SPI || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Device compatibility.. */
-/*===========================================================================*/
-
-#if defined (AT91C_BASE_SPI)
-#define AT91C_BASE_SPI0 AT91C_BASE_SPI
-#define AT91C_ID_SPI0 AT91C_ID_SPI
-
-#define SPI0_MISO (1 << 12)
-#define SPI0_MOSI (1 << 13)
-#define SPI0_SCK (1 << 14)
-#else
-#define SPI0_MISO (1 << 16)
-#define SPI0_MOSI (1 << 17)
-#define SPI0_SCK (1 << 18)
-
-#define SPI1_MISO (1 << 24)
-#define SPI1_MOSI (1 << 23)
-#define SPI1_SCK (1 << 22)
-#endif
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @brief SPID1 enable switch (SPI0 device).
- * @details If set to @p TRUE the support for SPI0 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(AT91SAM7_SPI_USE_SPI0) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI_USE_SPI0 TRUE
-#endif
-
-/**
- * @brief SPID2 enable switch (SPI1 device).
- * @details If set to @p TRUE the support for SPI1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(AT91SAM7_SPI_USE_SPI1) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI_USE_SPI1 TRUE
-#endif
-
-/**
- * @brief SPI0 device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_SPI0_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI0_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1)
-#endif
-
-/**
- * @brief SPI1 device interrupt priority level setting.
- */
-#if !defined(AT91SAM7_SPI1_PRIORITY) || defined(__DOXYGEN__)
-#define AT91SAM7_SPI1_PRIORITY (AT91C_AIC_PRIOR_HIGHEST - 1)
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if defined (AT91C_BASE_SPI) && AT91SAM7_SPI_USE_SPI1
-#error "SPI1 not present"
-#endif
-
-#if !AT91SAM7_SPI_USE_SPI0 && !AT91SAM7_SPI_USE_SPI1
-#error "SPI driver activated but no SPI peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief Type of a structure representing an SPI driver.
- */
-typedef struct SPIDriver SPIDriver;
-
-/**
- * @brief SPI notification callback type.
- *
- * @param[in] spip pointer to the @p SPIDriver object triggering the
- * callback
- */
-typedef void (*spicallback_t)(SPIDriver *spip);
-
-/**
- * @brief Driver configuration structure.
- */
-typedef struct {
- /**
- * @brief Operation complete callback or @p NULL.
- */
- spicallback_t end_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief The chip select line port.
- */
- ioportid_t ssport;
- /**
- * @brief The chip select line pad number.
- */
- uint16_t sspad;
- /**
- * @brief SPI Chip Select Register initialization data.
- */
- uint32_t csr;
-} SPIConfig;
-
-/**
- * @brief Structure representing a SPI driver.
- */
-struct SPIDriver {
- /**
- * @brief Driver state.
- */
- spistate_t state;
- /**
- * @brief Current configuration data.
- */
- const SPIConfig *config;
-#if SPI_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- Thread *thread;
-#endif /* SPI_USE_WAIT */
-#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the bus.
- */
- Mutex mutex;
-#elif CH_CFG_USE_SEMAPHORES
- Semaphore semaphore;
-#endif
-#endif /* SPI_USE_MUTUAL_EXCLUSION */
-#if defined(SPI_DRIVER_EXT_FIELDS)
- SPI_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the SPIx registers block.
- */
- AT91PS_SPI spi;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if AT91SAM7_SPI_USE_SPI0 && !defined(__DOXYGEN__)
-extern SPIDriver SPID1;
-#endif
-
-#if AT91SAM7_SPI_USE_SPI1 && !defined(__DOXYGEN__)
-extern SPIDriver SPID2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void spi_lld_init(void);
- void spi_lld_start(SPIDriver *spip);
- void spi_lld_stop(SPIDriver *spip);
- void spi_lld_select(SPIDriver *spip);
- void spi_lld_unselect(SPIDriver *spip);
- void spi_lld_ignore(SPIDriver *spip, size_t n);
- void spi_lld_exchange(SPIDriver *spip, size_t n,
- const void *txbuf, void *rxbuf);
- void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
- void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
- uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SPI */
-
-#endif /* _SPI_LLD_H_ */
-
-/** @} */
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