git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7810 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 75 insertions, 10 deletions

diff --git a/os/hal/osal/nil/osal.h b/os/hal/osal/nil/osal.h
index 0c3541efd..c20e7ef15 100644
--- a/os/hal/osal/nil/osal.h
+++ b/os/hal/osal/nil/osal.h
@@ -109,6 +109,21 @@
 #endif

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            CORTEX_PRIORITY_LEVELS

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#define OSAL_IRQ_MAXIMUM_PRIORITY           CORTEX_MAX_KERNEL_PRIORITY

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -278,6 +293,11 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

diff --git a/os/hal/osal/os-less/ARMCMx/osal.c b/os/hal/osal/os-less/ARMCMx/osal.c
index 213fd18bd..6273bb874 100644
--- a/os/hal/osal/os-less/ARMCMx/osal.c
+++ b/os/hal/osal/os-less/ARMCMx/osal.c
@@ -368,7 +368,7 @@ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
 

   osalDbgCheck(tqp != NULL);

 

-  (void)time;

+  (void)timeout;

 

   return MSG_OK;

 }

diff --git a/os/hal/osal/os-less/ARMCMx/osal.h b/os/hal/osal/os-less/ARMCMx/osal.h
index 9d65be2f3..bb030c4f5 100644
--- a/os/hal/osal/os-less/ARMCMx/osal.h
+++ b/os/hal/osal/os-less/ARMCMx/osal.h
@@ -99,6 +99,25 @@
 #define OSAL_ST_MODE                        OSAL_ST_MODE_PERIODIC

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            (1U << CORTEX_PRIORITY_BITS)

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#if (CORTEX_MODEL == 0) || defined(__DOXYGEN__)

+#define OSAL_IRQ_MAXIMUM_PRIORITY           0

+#else

+#define OSAL_IRQ_MAXIMUM_PRIORITY           1

+#endif

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -334,6 +353,12 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n)                                       \

+  (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

@@ -510,10 +535,10 @@ static inline void osalSysEnable(void) {
  */

 static inline void osalSysLock(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __disable_irq();

 #else

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

 }

 

@@ -525,7 +550,7 @@ static inline void osalSysLock(void) {
  */

 static inline void osalSysUnlock(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __enable_irq();

 #else

   __set_BASEPRI(0);

@@ -540,10 +565,10 @@ static inline void osalSysUnlock(void) {
  */

 static inline void osalSysLockFromISR(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __disable_irq();

 #else

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

 }

 

@@ -555,7 +580,7 @@ static inline void osalSysLockFromISR(void) {
  */

 static inline void osalSysUnlockFromISR(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __enable_irq();

 #else

   __set_BASEPRI(0);

@@ -578,12 +603,12 @@ static inline void osalSysUnlockFromISR(void) {
 static inline syssts_t osalSysGetStatusAndLockX(void)  {

   syssts_t sts;

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   sts = (syssts_t)__get_PRIMASK();

   __disable_irq();

 #else

   sts = (syssts_t)__get_BASEPRI();

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

   return sts;

 }

@@ -599,7 +624,7 @@ static inline syssts_t osalSysGetStatusAndLockX(void)  {
  */

 static inline void osalSysRestoreStatusX(syssts_t sts) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   if ((sts & (syssts_t)1) == (syssts_t)0) {

     __enable_irq();

   }

diff --git a/os/hal/osal/rt/osal.h b/os/hal/osal/rt/osal.h
index e48b1b2a5..0eff06a24 100644
--- a/os/hal/osal/rt/osal.h
+++ b/os/hal/osal/rt/osal.h
@@ -105,6 +105,21 @@
 #endif

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            CORTEX_PRIORITY_LEVELS

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#define OSAL_IRQ_MAXIMUM_PRIORITY           CORTEX_MAX_KERNEL_PRIORITY

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -270,6 +285,11 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */