git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7810 35acf78f-673a-0410-8e92-d51de3d6d3f4

19 files changed, 146 insertions, 100 deletions

diff --git a/os/common/ports/ARMCMx/devices/K20x/cmparams.h b/os/common/ports/ARMCMx/devices/K20x/cmparams.h
index ae4b5843b..5ae9dada6 100644
--- a/os/common/ports/ARMCMx/devices/K20x/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/K20x/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M4

+#define CORTEX_MODEL            4

 

 /**

  * @brief   Systick unit presence.

@@ -67,6 +67,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "mk20d5.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

 #error "CMSIS __NVIC_PRIO_BITS mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/KL2x/cmparams.h b/os/common/ports/ARMCMx/devices/KL2x/cmparams.h
index f1a5b36ef..6da2fed0e 100644
--- a/os/common/ports/ARMCMx/devices/KL2x/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/KL2x/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M0PLUS

+#define CORTEX_MODEL            0

 

 /**

  * @brief   Systick unit presence.

@@ -67,6 +67,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "kl25z.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

 #error "CMSIS __NVIC_PRIO_BITS mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
index 8e44e2029..2744a6f72 100644
--- a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M0

+#define CORTEX_MODEL            0

 

 /**

  * @brief   Floating Point unit presence.

@@ -74,6 +74,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32f0xx.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

 #error "CMSIS __NVIC_PRIO_BITS mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
index 30d81bcc9..9f91938ff 100644
--- a/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32F1xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M3

+#define CORTEX_MODEL            3

 

 /**

  * @brief   Floating Point unit presence.

@@ -65,8 +65,8 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32f10x.h"

 

-#if !CORTEX_HAS_FPU != !__FPU_PRESENT

-#error "CMSIS __FPU_PRESENT mismatch"

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

 #endif

 

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

diff --git a/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
index 12f2b31f4..bcf0c6f32 100644
--- a/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M4

+#define CORTEX_MODEL            4

 

 /**

  * @brief   Floating Point unit presence.

@@ -74,6 +74,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32f3xx.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_HAS_FPU != __FPU_PRESENT

 #error "CMSIS __FPU_PRESENT mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
index 0f8b090b7..59951b5ae 100644
--- a/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32F4xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M4

+#define CORTEX_MODEL            4

 

 /**

  * @brief   Floating Point unit presence.

@@ -74,6 +74,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32f4xx.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_HAS_FPU != __FPU_PRESENT

 #error "CMSIS __FPU_PRESENT mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h
index 2d227d1ef..850793a0f 100644
--- a/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32L0xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M0PLUS

+#define CORTEX_MODEL            0

 

 /**

  * @brief   Floating Point unit presence.

@@ -71,6 +71,10 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32l0xx.h"

 

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

+#endif

+

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

 #error "CMSIS __NVIC_PRIO_BITS mismatch"

 #endif

diff --git a/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
index 2e3062f4a..2c52fef39 100644
--- a/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32L1xx/cmparams.h
@@ -34,7 +34,7 @@
 /**

  * @brief   Cortex core model.

  */

-#define CORTEX_MODEL            CORTEX_M3

+#define CORTEX_MODEL            3

 

 /**

  * @brief   Floating Point unit presence.

@@ -69,8 +69,8 @@
    assembler source files. We verify that the info matches instead.*/

 #include "stm32l1xx.h"

 

-#if !CORTEX_HAS_FPU != !__FPU_PRESENT

-#error "CMSIS __FPU_PRESENT mismatch"

+#if CORTEX_MODEL != __CORTEX_M

+#error "CMSIS __CORTEX_M mismatch"

 #endif

 

 #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS

diff --git a/os/hal/osal/nil/osal.h b/os/hal/osal/nil/osal.h
index 0c3541efd..c20e7ef15 100644
--- a/os/hal/osal/nil/osal.h
+++ b/os/hal/osal/nil/osal.h
@@ -109,6 +109,21 @@
 #endif

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            CORTEX_PRIORITY_LEVELS

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#define OSAL_IRQ_MAXIMUM_PRIORITY           CORTEX_MAX_KERNEL_PRIORITY

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -278,6 +293,11 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

diff --git a/os/hal/osal/os-less/ARMCMx/osal.c b/os/hal/osal/os-less/ARMCMx/osal.c
index 213fd18bd..6273bb874 100644
--- a/os/hal/osal/os-less/ARMCMx/osal.c
+++ b/os/hal/osal/os-less/ARMCMx/osal.c
@@ -368,7 +368,7 @@ msg_t osalThreadEnqueueTimeoutS(threads_queue_t *tqp, systime_t timeout) {
 

   osalDbgCheck(tqp != NULL);

 

-  (void)time;

+  (void)timeout;

 

   return MSG_OK;

 }

diff --git a/os/hal/osal/os-less/ARMCMx/osal.h b/os/hal/osal/os-less/ARMCMx/osal.h
index 9d65be2f3..bb030c4f5 100644
--- a/os/hal/osal/os-less/ARMCMx/osal.h
+++ b/os/hal/osal/os-less/ARMCMx/osal.h
@@ -99,6 +99,25 @@
 #define OSAL_ST_MODE                        OSAL_ST_MODE_PERIODIC

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            (1U << CORTEX_PRIORITY_BITS)

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#if (CORTEX_MODEL == 0) || defined(__DOXYGEN__)

+#define OSAL_IRQ_MAXIMUM_PRIORITY           0

+#else

+#define OSAL_IRQ_MAXIMUM_PRIORITY           1

+#endif

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -334,6 +353,12 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n)                                       \

+  (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

@@ -510,10 +535,10 @@ static inline void osalSysEnable(void) {
  */

 static inline void osalSysLock(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __disable_irq();

 #else

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

 }

 

@@ -525,7 +550,7 @@ static inline void osalSysLock(void) {
  */

 static inline void osalSysUnlock(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __enable_irq();

 #else

   __set_BASEPRI(0);

@@ -540,10 +565,10 @@ static inline void osalSysUnlock(void) {
  */

 static inline void osalSysLockFromISR(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __disable_irq();

 #else

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

 }

 

@@ -555,7 +580,7 @@ static inline void osalSysLockFromISR(void) {
  */

 static inline void osalSysUnlockFromISR(void) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   __enable_irq();

 #else

   __set_BASEPRI(0);

@@ -578,12 +603,12 @@ static inline void osalSysUnlockFromISR(void) {
 static inline syssts_t osalSysGetStatusAndLockX(void)  {

   syssts_t sts;

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   sts = (syssts_t)__get_PRIMASK();

   __disable_irq();

 #else

   sts = (syssts_t)__get_BASEPRI();

-  __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

+  __set_BASEPRI(OSAL_IRQ_MAXIMUM_PRIORITY);

 #endif

   return sts;

 }

@@ -599,7 +624,7 @@ static inline syssts_t osalSysGetStatusAndLockX(void)  {
  */

 static inline void osalSysRestoreStatusX(syssts_t sts) {

 

-#if CORTEX_MODEL == CORTEX_M0

+#if CORTEX_MODEL == 0

   if ((sts & (syssts_t)1) == (syssts_t)0) {

     __enable_irq();

   }

diff --git a/os/hal/osal/rt/osal.h b/os/hal/osal/rt/osal.h
index e48b1b2a5..0eff06a24 100644
--- a/os/hal/osal/rt/osal.h
+++ b/os/hal/osal/rt/osal.h
@@ -105,6 +105,21 @@
 #endif

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            CORTEX_PRIORITY_LEVELS

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#define OSAL_IRQ_MAXIMUM_PRIORITY           CORTEX_MAX_KERNEL_PRIORITY

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -270,6 +285,11 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n) CORTEX_IS_VALID_KERNEL_PRIORITY(n)

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

diff --git a/os/hal/templates/osal/osal.h b/os/hal/templates/osal/osal.h
index f31501b79..1eb9ec5de 100644
--- a/os/hal/templates/osal/osal.h
+++ b/os/hal/templates/osal/osal.h
@@ -96,6 +96,21 @@
 #define OSAL_ST_MODE                        OSAL_ST_MODE_PERIODIC

 /** @} */

 

+/**

+ * @name    IRQ-related constants

+ * @{

+ */

+/**

+ * @brief   Total priority levels.

+ */

+#define OSAL_IRQ_PRIORITY_LEVELS            16U

+

+/**

+ * @brief   Highest IRQ priority for HAL drivers.

+ */

+#define OSAL_IRQ_MAXIMUM_PRIORITY           0U

+/** @} */

+

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -273,6 +288,12 @@ typedef struct {
  * @{

  */

 /**

+ * @brief   Priority level verification macro.

+ */

+#define OSAL_IRQ_IS_VALID_PRIORITY(n)                                       \

+  (((n) >= OSAL_IRQ_MAXIMUM_PRIORITY) && ((n) < OSAL_IRQ_PRIORITY_LEVELS))

+

+/**

  * @brief   IRQ prologue code.

  * @details This macro must be inserted at the start of all IRQ handlers.

  */

diff --git a/os/nil/ports/ARMCMx/nilcore.h b/os/nil/ports/ARMCMx/nilcore.h
index d2777aeee..dd5756cf3 100644
--- a/os/nil/ports/ARMCMx/nilcore.h
+++ b/os/nil/ports/ARMCMx/nilcore.h
@@ -66,17 +66,6 @@
 

 /** @} */

 

-/**

- * @name    Cortex-M variants

- * @{

- */

-#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */

-#define CORTEX_M0PLUS                   1   /**< @brief Cortex-M0+ variant. */

-#define CORTEX_M1                       10  /**< @brief Cortex-M1 variant.  */

-#define CORTEX_M3                       30  /**< @brief Cortex-M3 variant.  */

-#define CORTEX_M4                       40  /**< @brief Cortex-M4 variant.  */

-/** @} */

-

 /* Inclusion of the Cortex-Mx implementation specific parameters.*/

 #include "cmparams.h"

 

@@ -98,27 +87,6 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-/* The following code is not processed when the file is included from an

-   asm module.*/

-#if !defined(_FROM_ASM_)

-

-/*

- * Inclusion of the appropriate CMSIS header for the selected device.

- */

-#if CORTEX_MODEL == CORTEX_M0

-#include "core_cm0.h"

-#elif CORTEX_MODEL == CORTEX_M0PLUS

-#include "core_cm0plus.h"

-#elif CORTEX_MODEL == CORTEX_M3

-#include "core_cm3.h"

-#elif CORTEX_MODEL == CORTEX_M4

-#include "core_cm4.h"

-#else

-#error "unknown or unsupported Cortex-M model"

-#endif

-

-#endif /* !defined(_FROM_ASM_) */

-

 /*===========================================================================*/

 /* Module data structures and types.                                         */

 /*===========================================================================*/

@@ -211,10 +179,9 @@ struct port_intctx {};
 /*===========================================================================*/

 

 /* Includes the sub-architecture-specific part.*/

-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) ||       \

-    (CORTEX_MODEL == CORTEX_M1)

+#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1)

 #include "nilcore_v6m.h"

-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

+#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)

 #include "nilcore_v7m.h"

 #endif

 

diff --git a/os/nil/ports/ARMCMx/nilcore_v6m.h b/os/nil/ports/ARMCMx/nilcore_v6m.h
index a03e3c900..3a500d2b0 100644
--- a/os/nil/ports/ARMCMx/nilcore_v6m.h
+++ b/os/nil/ports/ARMCMx/nilcore_v6m.h
@@ -99,7 +99,8 @@
  * @name    Architecture and Compiler

  * @{

  */

-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)

+#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) ||        \

+    defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the specific ARM architecture.

  */

@@ -115,7 +116,7 @@
  */

 #define PORT_CORE_VARIANT_NAME          "Cortex-M0"

 

-#elif (CORTEX_MODEL == CORTEX_M0PLUS)

+#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT)

 #define PORT_ARCHITECTURE_ARM_v6M

 #define PORT_ARCHITECTURE_NAME          "ARMv6-M"

 #define PORT_CORE_VARIANT_NAME          "Cortex-M0+"

diff --git a/os/nil/ports/ARMCMx/nilcore_v7m.h b/os/nil/ports/ARMCMx/nilcore_v7m.h
index 603ff8d7a..4e7829d2d 100644
--- a/os/nil/ports/ARMCMx/nilcore_v7m.h
+++ b/os/nil/ports/ARMCMx/nilcore_v7m.h
@@ -139,7 +139,7 @@
  * @name    Architecture and Compiler

  * @{

  */

-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

+#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the specific ARM architecture.

  */

@@ -155,7 +155,7 @@
  */

 #define PORT_CORE_VARIANT_NAME          "Cortex-M3"

 

-#elif (CORTEX_MODEL == CORTEX_M4)

+#elif (CORTEX_MODEL == 4)

 #define PORT_ARCHITECTURE_ARM_v7ME

 #define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

 #if CORTEX_USE_FPU

diff --git a/os/rt/ports/ARMCMx/chcore.h b/os/rt/ports/ARMCMx/chcore.h
index 23f33a6f8..abf0b4596 100644
--- a/os/rt/ports/ARMCMx/chcore.h
+++ b/os/rt/ports/ARMCMx/chcore.h
@@ -66,17 +66,6 @@
 

 /** @} */

 

-/**

- * @name    Cortex-M variants

- * @{

- */

-#define CORTEX_M0                       0   /**< @brief Cortex-M0 variant.  */

-#define CORTEX_M0PLUS                   1   /**< @brief Cortex-M0+ variant. */

-#define CORTEX_M1                       10  /**< @brief Cortex-M1 variant.  */

-#define CORTEX_M3                       30  /**< @brief Cortex-M3 variant.  */

-#define CORTEX_M4                       40  /**< @brief Cortex-M4 variant.  */

-/** @} */

-

 /* Inclusion of the Cortex-Mx implementation specific parameters.*/

 #include "cmparams.h"

 

@@ -98,27 +87,6 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-/* The following code is not processed when the file is included from an

-   asm module.*/

-#if !defined(_FROM_ASM_)

-

-/*

- * Inclusion of the appropriate CMSIS header for the selected device.

- */

-#if CORTEX_MODEL == CORTEX_M0

-#include "core_cm0.h"

-#elif CORTEX_MODEL == CORTEX_M0PLUS

-#include "core_cm0plus.h"

-#elif CORTEX_MODEL == CORTEX_M3

-#include "core_cm3.h"

-#elif CORTEX_MODEL == CORTEX_M4

-#include "core_cm4.h"

-#else

-#error "unknown or unsupported Cortex-M model"

-#endif

-

-#endif /* !defined(_FROM_ASM_) */

-

 /*===========================================================================*/

 /* Module data structures and types.                                         */

 /*===========================================================================*/

@@ -221,10 +189,9 @@ struct context {
 /*===========================================================================*/

 

 /* Includes the sub-architecture-specific part.*/

-#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M0PLUS) ||       \

-    (CORTEX_MODEL == CORTEX_M1)

+#if (CORTEX_MODEL == 0) || (CORTEX_MODEL == 1)

 #include "chcore_v6m.h"

-#elif (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4)

+#elif (CORTEX_MODEL == 3) || (CORTEX_MODEL == 4)

 #include "chcore_v7m.h"

 #endif

 

diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h
index bd9ab4781..c8361a549 100644
--- a/os/rt/ports/ARMCMx/chcore_v6m.h
+++ b/os/rt/ports/ARMCMx/chcore_v6m.h
@@ -99,7 +99,8 @@
  * @name    Architecture and Compiler

  * @{

  */

-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)

+#if ((CORTEX_MODEL == 0) && !defined(__CORE_CM0PLUS_H_DEPENDANT)) ||        \

+    defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the specific ARM architecture.

  */

@@ -115,7 +116,7 @@
  */

 #define PORT_CORE_VARIANT_NAME          "Cortex-M0"

 

-#elif (CORTEX_MODEL == CORTEX_M0PLUS)

+#elif (CORTEX_MODEL == 0) && defined(__CORE_CM0PLUS_H_DEPENDANT)

 #define PORT_ARCHITECTURE_ARM_v6M

 #define PORT_ARCHITECTURE_NAME          "ARMv6-M"

 #define PORT_CORE_VARIANT_NAME          "Cortex-M0+"

diff --git a/os/rt/ports/ARMCMx/chcore_v7m.h b/os/rt/ports/ARMCMx/chcore_v7m.h
index 12d46c738..b437a8fad 100644
--- a/os/rt/ports/ARMCMx/chcore_v7m.h
+++ b/os/rt/ports/ARMCMx/chcore_v7m.h
@@ -139,7 +139,7 @@
  * @name    Architecture and Compiler

  * @{

  */

-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

+#if (CORTEX_MODEL == 3) || defined(__DOXYGEN__)

 /**

  * @brief   Macro defining the specific ARM architecture.

  */

@@ -155,7 +155,7 @@
  */

 #define PORT_CORE_VARIANT_NAME          "Cortex-M3"

 

-#elif (CORTEX_MODEL == CORTEX_M4)

+#elif (CORTEX_MODEL == 4)

 #define PORT_ARCHITECTURE_ARM_v7ME

 #define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

 #if CORTEX_USE_FPU