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| author | edolomb <none@example.com> | 2018-01-10 09:31:05 +0000 |
|---|---|---|
| committer | edolomb <none@example.com> | 2018-01-10 09:31:05 +0000 |
| commit | 0da6de11ee208137162df9206b3b5731e2980d28 (patch) | |
| tree | d88c933bde3d154e6e02029b1d7f6d45c49ce1a6 /os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S | |
| parent | e669bfa7e66f92f65f8f4c66e7eaf4b505b435f6 (diff) | |
| download | ChibiOS-0da6de11ee208137162df9206b3b5731e2980d28.tar.gz ChibiOS-0da6de11ee208137162df9206b3b5731e2980d28.tar.bz2 ChibiOS-0da6de11ee208137162df9206b3b5731e2980d28.zip | |
Enabled ARM cycle counter
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11246 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S')
| -rw-r--r-- | os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S index 0ba357a0e..f8050f8c6 100644 --- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S +++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S @@ -86,6 +86,15 @@ Boot_Handler: ldr r1, =SFR_L2CC_HRAMC str r0, [r1] /* + * Enabling Cycle counter + */ + mrc p15, 0, r0, c9, c12, 0 // read PMCR register + orr r0, r0, #(0x1) // set E bit 0 to enable counter + mcr p15, 0, r0, c9, c12, 0 // write r0 + mrc p15, 0, r0, c9, c12, 1 // read PMCNTENSET register + orr r0, r0, #(0x1 << 31) // set bit 31 to enable counter + mcr p15, 0, r0, c9, c12, 1 // write r0 + /* * Configure the intial catching of the interrupts */ ldr r0, =SCR_RESET_VAL // IRQ and ABT to monitor in secure mode |