From 0da6de11ee208137162df9206b3b5731e2980d28 Mon Sep 17 00:00:00 2001 From: edolomb Date: Wed, 10 Jan 2018 09:31:05 +0000 Subject: Enabled ARM cycle counter git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11246 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S') diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S index 0ba357a0e..f8050f8c6 100644 --- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S +++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/boot.S @@ -85,6 +85,15 @@ Boot_Handler: bic r0, r0, #0x1 ldr r1, =SFR_L2CC_HRAMC str r0, [r1] + /* + * Enabling Cycle counter + */ + mrc p15, 0, r0, c9, c12, 0 // read PMCR register + orr r0, r0, #(0x1) // set E bit 0 to enable counter + mcr p15, 0, r0, c9, c12, 0 // write r0 + mrc p15, 0, r0, c9, c12, 1 // read PMCNTENSET register + orr r0, r0, #(0x1 << 31) // set bit 31 to enable counter + mcr p15, 0, r0, c9, c12, 1 // write r0 /* * Configure the intial catching of the interrupts */ -- cgit v1.2.3