git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5849 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 247 insertions, 36 deletions

diff --git a/demos/PPC-SPC560P-GCC/mcuconf.h b/demos/PPC-SPC560P-GCC/mcuconf.h
index f5e52b7f7..f30b63d8a 100644
--- a/demos/PPC-SPC560P-GCC/mcuconf.h
+++ b/demos/PPC-SPC560P-GCC/mcuconf.h
@@ -23,6 +23,8 @@
  *

  * IRQ priorities:

  * 1...15       Lowest...Highest.

+ * DMA priorities:

+ * 0...15       Highest...Lowest.

  */

 

 #define SPC560Pxx_MCUCONF

@@ -148,6 +150,15 @@
 #define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()

 

 /*

+ * EDMA driver settings.

+ */

+#define SPC5_EDMA_CR_SETTING                0

+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_ERROR_IRQ_PRIO            2

+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

+

+/*

  * SERIAL driver system settings.

  */

 #define SPC5_SERIAL_USE_LINFLEX0            TRUE

@@ -162,3 +173,83 @@
                                              SPC5_ME_PCTL_LP(2))

 #define SPC5_SERIAL_LINFLEX1_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \

                                              SPC5_ME_PCTL_LP(0))

+

+/*

+ * SPI driver system settings.

+ */

+#define SPC5_SPI_USE_DSPI0                  TRUE

+#define SPC5_SPI_USE_DSPI1                  TRUE

+#define SPC5_SPI_USE_DSPI2                  TRUE

+#define SPC5_SPI_USE_DSPI3                  TRUE

+#define SPC5_SPI_USE_DSPI4                  FALSE

+#define SPC5_SPI_DSPI0_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI2_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI3_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI4_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI0_IRQ_PRIO             10

+#define SPC5_SPI_DSPI1_IRQ_PRIO             10

+#define SPC5_SPI_DSPI2_IRQ_PRIO             10

+#define SPC5_SPI_DSPI3_IRQ_PRIO             10

+#define SPC5_SPI_DSPI4_IRQ_PRIO             10

+#define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()

+#define SPC5_SPI_DSPI0_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI0_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI1_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI1_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI2_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI2_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI3_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI3_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI4_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI4_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

diff --git a/demos/PPC-SPC563M-GCC/mcuconf.h b/demos/PPC-SPC563M-GCC/mcuconf.h
index 28a5790f5..76898ad35 100644
--- a/demos/PPC-SPC563M-GCC/mcuconf.h
+++ b/demos/PPC-SPC563M-GCC/mcuconf.h
@@ -58,10 +58,6 @@
   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

 #define SPC5_EDMA_GROUP1_PRIORITIES                                         \

   0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

-#define SPC5_EDMA_GROUP2_PRIORITIES                                         \

-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

-#define SPC5_EDMA_GROUP3_PRIORITIES                                         \

-  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

 #define SPC5_EDMA_ERROR_IRQ_PRIO            2

 #define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

 

diff --git a/demos/PPC-SPC564A-GCC/Makefile b/demos/PPC-SPC564A-GCC/Makefile
index d79a29ab1..9b51a6845 100644
--- a/demos/PPC-SPC564A-GCC/Makefile
+++ b/demos/PPC-SPC564A-GCC/Makefile
@@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk
 include $(CHIBIOS)/test/test.mk

 

 # Define linker script file here

-LDSCRIPT= $(PORTLD)/SPC564A80.ld

+LDSCRIPT= $(PORTLD)/SPC564A70.ld

 

 # C sources here.

 CSRC = $(PORTSRC) \

diff --git a/demos/PPC-SPC564A-GCC/mcuconf.h b/demos/PPC-SPC564A-GCC/mcuconf.h
index 0683912f9..dc54d3d88 100644
--- a/demos/PPC-SPC564A-GCC/mcuconf.h
+++ b/demos/PPC-SPC564A-GCC/mcuconf.h
@@ -23,6 +23,8 @@
  *

  * IRQ priorities:

  * 1...15       Lowest...Highest.

+ * DMA priorities:

+ * 0...15       Highest...Lowest.

  */

 

 #define SPC564Axx_MCUCONF

@@ -45,6 +47,25 @@
                                              BIUCR_BFEN)

 

 /*

+ * EDMA driver settings.

+ */

+#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \

+                                             EDMA_CR_GRP2PRI(2) |           \

+                                             EDMA_CR_GRP1PRI(1) |           \

+                                             EDMA_CR_GRP0PRI(0) |           \

+                                             EDMA_CR_ERGA)

+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_GROUP1_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_GROUP2_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_GROUP3_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_ERROR_IRQ_PRIO            2

+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

+

+/*

  * ADC driver settings.

  */

 #define SPC5_ADC_USE_ADC0_Q0                FALSE

@@ -53,12 +74,6 @@
 #define SPC5_ADC_USE_ADC1_Q3                FALSE

 #define SPC5_ADC_USE_ADC1_Q4                FALSE

 #define SPC5_ADC_USE_ADC1_Q5                FALSE

-#define SPC5_ADC_FIFO0_DMA_PRIO             12

-#define SPC5_ADC_FIFO1_DMA_PRIO             12

-#define SPC5_ADC_FIFO2_DMA_PRIO             12

-#define SPC5_ADC_FIFO3_DMA_PRIO             12

-#define SPC5_ADC_FIFO4_DMA_PRIO             12

-#define SPC5_ADC_FIFO5_DMA_PRIO             12

 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         12

 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         12

 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         12

@@ -88,9 +103,9 @@
 /*

  * SPI driver system settings.

  */

-#define SPC5_SPI_USE_DSPI1                  TRUE

-#define SPC5_SPI_USE_DSPI2                  TRUE

-#define SPC5_SPI_USE_DSPI3                  TRUE

+#define SPC5_SPI_USE_DSPI1                  FALSE

+#define SPC5_SPI_USE_DSPI2                  FALSE

+#define SPC5_SPI_USE_DSPI3                  FALSE

 #define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \

                                              SPC5_MCR_PCSIS1 |              \

                                              SPC5_MCR_PCSIS2 |              \

@@ -115,9 +130,6 @@
                                              SPC5_MCR_PCSIS5 |              \

                                              SPC5_MCR_PCSIS6 |              \

                                              SPC5_MCR_PCSIS7)

-#define SPC5_SPI_DSPI1_DMA_PRIO             10

-#define SPC5_SPI_DSPI2_DMA_PRIO             10

-#define SPC5_SPI_DSPI3_DMA_PRIO             10

 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10

 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10

 #define SPC5_SPI_DSPI3_DMA_IRQ_PRIO         10

diff --git a/demos/PPC-SPC56EL-GCC/mcuconf.h b/demos/PPC-SPC56EL-GCC/mcuconf.h
index 96f8c6b86..f90a80578 100644
--- a/demos/PPC-SPC56EL-GCC/mcuconf.h
+++ b/demos/PPC-SPC56EL-GCC/mcuconf.h
@@ -23,6 +23,8 @@
  *

  * IRQ priorities:

  * 1...15       Lowest...Highest.

+ * DMA priorities:

+ * 0...15       Highest...Lowest.

  */

 

 #define SPC56ELxx_MCUCONF

@@ -41,9 +43,9 @@
 #define SPC5_FMPLL1_IDF_VALUE               5

 #define SPC5_FMPLL1_NDIV_VALUE              60

 #define SPC5_FMPLL1_ODF                     SPC5_FMPLL_ODF_DIV4

-#define SPC5_SYSCLK_DIVIDER_VALUE           1

+#define SPC5_SYSCLK_DIVIDER_VALUE           2

 #define SPC5_AUX0CLK_SRC                    SPC5_CGM_SS_FMPLL1

-#define SPC5_MCONTROL_DIVIDER_VALUE         2

+#define SPC5_MCONTROL_DIVIDER_VALUE         15

 #define SPC5_SWG_DIVIDER_VALUE              2

 #define SPC5_AUX1CLK_SRC                    SPC5_CGM_SS_FMPLL1

 #define SPC5_FLEXRAY_DIVIDER_VALUE          2

@@ -104,18 +106,6 @@
                                              SPC5_ME_MC_PLL1ON |            \

                                              SPC5_ME_MC_FLAON_NORMAL |      \

                                              SPC5_ME_MC_MVRON)

-#define SPC5_ME_RUN_PC0_BITS                0

-#define SPC5_ME_RUN_PC1_BITS                (SPC5_ME_RUN_PC_SAFE |          \

-                                             SPC5_ME_RUN_PC_DRUN |          \

-                                             SPC5_ME_RUN_PC_RUN0 |          \

-                                             SPC5_ME_RUN_PC_RUN1 |          \

-                                             SPC5_ME_RUN_PC_RUN2 |          \

-                                             SPC5_ME_RUN_PC_RUN3)

-#define SPC5_ME_RUN_PC2_BITS                (SPC5_ME_RUN_PC_DRUN |          \

-                                             SPC5_ME_RUN_PC_RUN0 |          \

-                                             SPC5_ME_RUN_PC_RUN1 |          \

-                                             SPC5_ME_RUN_PC_RUN2 |          \

-                                             SPC5_ME_RUN_PC_RUN3)

 #define SPC5_ME_RUN_PC3_BITS                (SPC5_ME_RUN_PC_RUN0 |          \

                                              SPC5_ME_RUN_PC_RUN1 |          \

                                              SPC5_ME_RUN_PC_RUN2 |          \

@@ -136,11 +126,6 @@
                                              SPC5_ME_RUN_PC_RUN1 |          \

                                              SPC5_ME_RUN_PC_RUN2 |          \

                                              SPC5_ME_RUN_PC_RUN3)

-#define SPC5_ME_LP_PC0_BITS                 0

-#define SPC5_ME_LP_PC1_BITS                 (SPC5_ME_LP_PC_HALT0 |          \

-                                             SPC5_ME_LP_PC_STOP0)

-#define SPC5_ME_LP_PC2_BITS                 (SPC5_ME_LP_PC_HALT0)

-#define SPC5_ME_LP_PC3_BITS                 (SPC5_ME_LP_PC_STOP0)

 #define SPC5_ME_LP_PC4_BITS                 (SPC5_ME_LP_PC_HALT0 |          \

                                              SPC5_ME_LP_PC_STOP0)

 #define SPC5_ME_LP_PC5_BITS                 (SPC5_ME_LP_PC_HALT0 |          \

@@ -152,6 +137,15 @@
 #define SPC5_CLOCK_FAILURE_HOOK()           chSysHalt()

 

 /*

+ * EDMA driver settings.

+ */

+#define SPC5_EDMA_CR_SETTING                0

+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#define SPC5_EDMA_ERROR_IRQ_PRIO            2

+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

+

+/*

  * SERIAL driver system settings.

  */

 #define SPC5_SERIAL_USE_LINFLEX0            TRUE

@@ -166,3 +160,121 @@
                                              SPC5_ME_PCTL_LP(2))

 #define SPC5_SERIAL_LINFLEX1_STOP_PCTL      (SPC5_ME_PCTL_RUN(0) |          \

                                              SPC5_ME_PCTL_LP(0))

+

+/*

+ * PWM driver system settings.

+ */

+#define SPC5_PWM_USE_SMOD0                  FALSE

+#define SPC5_PWM_USE_SMOD1                  FALSE

+#define SPC5_PWM_USE_SMOD2                  FALSE

+#define SPC5_PWM_USE_SMOD3                  FALSE

+#define SPC5_PWM_SMOD0_PRIORITY             7

+#define SPC5_PWM_SMOD1_PRIORITY             7

+#define SPC5_PWM_SMOD2_PRIORITY             7

+#define SPC5_PWM_SMOD3_PRIORITY             7

+#define SPC5_PWM_FLEXPWM0_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_PWM_FLEXPWM0_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+

+#define SPC5_PWM_USE_SMOD4                  FALSE

+#define SPC5_PWM_USE_SMOD5                  FALSE

+#define SPC5_PWM_USE_SMOD6                  FALSE

+#define SPC5_PWM_USE_SMOD7                  FALSE

+#define SPC5_PWM_SMOD4_PRIORITY             7

+#define SPC5_PWM_SMOD5_PRIORITY             7

+#define SPC5_PWM_SMOD6_PRIORITY             7

+#define SPC5_PWM_SMOD7_PRIORITY             7

+#define SPC5_PWM_FLEXPWM1_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_PWM_FLEXPWM1_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+

+/*

+ * ICU driver system settings.

+ */

+#define SPC5_ICU_USE_SMOD0                  FALSE

+#define SPC5_ICU_USE_SMOD1                  FALSE

+#define SPC5_ICU_USE_SMOD2                  FALSE

+#define SPC5_ICU_USE_SMOD3                  FALSE

+#define SPC5_ICU_USE_SMOD4                  FALSE

+#define SPC5_ICU_USE_SMOD5                  FALSE

+#define SPC5_ICU_ETIMER0_PRIORITY           7

+#define SPC5_ICU_ETIMER0_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_ICU_ETIMER0_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+

+#define SPC5_ICU_USE_SMOD6                  FALSE

+#define SPC5_ICU_USE_SMOD7                  FALSE

+#define SPC5_ICU_USE_SMOD8                  FALSE

+#define SPC5_ICU_USE_SMOD9                  FALSE

+#define SPC5_ICU_USE_SMOD10                 FALSE

+#define SPC5_ICU_USE_SMOD11                 FALSE

+#define SPC5_ICU_ETIMER1_PRIORITY           7

+#define SPC5_ICU_ETIMER1_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_ICU_ETIMER1_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+

+#define SPC5_ICU_USE_SMOD12                 FALSE

+#define SPC5_ICU_USE_SMOD13                 FALSE

+#define SPC5_ICU_USE_SMOD14                 FALSE

+#define SPC5_ICU_USE_SMOD15                 FALSE

+#define SPC5_ICU_USE_SMOD16                 FALSE

+#define SPC5_ICU_USE_SMOD17                 FALSE

+#define SPC5_ICU_ETIMER2_PRIORITY           7

+#define SPC5_ICU_ETIMER2_START_PCTL         (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_ICU_ETIMER2_STOP_PCTL          (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+

+/*

+ * SPI driver system settings.

+ */

+#define SPC5_SPI_USE_DSPI0                  FALSE

+#define SPC5_SPI_USE_DSPI1                  FALSE

+#define SPC5_SPI_USE_DSPI2                  FALSE

+#define SPC5_SPI_DSPI0_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI1_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI2_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         10

+#define SPC5_SPI_DSPI0_IRQ_PRIO             10

+#define SPC5_SPI_DSPI1_IRQ_PRIO             10

+#define SPC5_SPI_DSPI2_IRQ_PRIO             10

+#define SPC5_SPI_DMA_ERROR_HOOK(spip)       chSysHalt()

+#define SPC5_SPI_DSPI0_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI0_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI1_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI1_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))

+#define SPC5_SPI_DSPI2_START_PCTL           (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#define SPC5_SPI_DSPI2_STOP_PCTL            (SPC5_ME_PCTL_RUN(0) |          \

+                                             SPC5_ME_PCTL_LP(0))