WSPI changes for compatibiity. Initial implementation for STM32 over QuadSPI, not complete.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12313 110e8d01-0319-4d1e-a829-52ad28d1bb01

4 files changed, 610 insertions, 67 deletions

diff --git a/os/hal/include/hal_wspi.h b/os/hal/include/hal_wspi.h
index 8ba4be5ff..65f1fe9b0 100644
--- a/os/hal/include/hal_wspi.h
+++ b/os/hal/include/hal_wspi.h
@@ -31,72 +31,6 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

-/**

- * @name    Transfer options

- * @note    The Low Level Driver should undef those modes that are not

- *          supported. The LLD can also define additional modes or reorder

- *          the bit masks in a more convenient way for the underlying

- *          implementation. It is important however to maintain the same

- *          name for the same functionality.

- * @{

- */

-#define WSPI_CFG_INSTRUCTION_MODE_MASK          (7LU << 0LU)

-#define WSPI_CFG_INSTRUCTION_MODE_NONE          (0LU << 0LU)

-#define WSPI_CFG_INSTRUCTION_MODE_ONE_LINES     (1LU << 0LU)

-#define WSPI_CFG_INSTRUCTION_MODE_TWO_LINES     (2LU << 0LU)

-#define WSPI_CFG_INSTRUCTION_MODE_FOUR_LINES    (3LU << 0LU)

-#define WSPI_CFG_INSTRUCTION_MODE_EIGHT_LINES   (4LU << 0LU)

-

-#define WSPI_CFG_INSTRUCTION_DDR                (1LU << 3LU)

-

-#define WSPI_CFG_INSTRUCTION_SIZE_MASK          (3LU << 4LU)

-#define WSPI_CFG_INSTRUCTION_SIZE_8             (0LU << 4LU)

-#define WSPI_CFG_INSTRUCTION_SIZE_16            (1LU << 4LU)

-#define WSPI_CFG_INSTRUCTION_SIZE_24            (2LU << 4LU)

-#define WSPI_CFG_INSTRUCTION_SIZE_32            (3LU << 4LU)

-

-#define WSPI_CFG_ADDR_MODE_MASK                 (7LU << 8LU)

-#define WSPI_CFG_ADDR_MODE_NONE                 (0LU << 8LU)

-#define WSPI_CFG_ADDR_MODE_ONE_LINE             (1LU << 8LU)

-#define WSPI_CFG_ADDR_MODE_TWO_LINES            (2LU << 8LU)

-#define WSPI_CFG_ADDR_MODE_FOUR_LINES           (3LU << 8LU)

-#define WSPI_CFG_ADDR_MODE_EIGHT_LINES          (4LU << 8LU)

-

-#define WSPI_CFG_ADDR_DDR                       (1LU << 11LU)

-

-#define WSPI_CFG_ADDR_SIZE_MASK                 (3LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_8                    (0LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_16                   (1LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_24                   (2LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_32                   (3LU << 12LU)

-

-#define WSPI_CFG_ALT_MODE_MASK                  (7LU << 16LU)

-#define WSPI_CFG_ALT_MODE_NONE                  (0LU << 16LU)

-#define WSPI_CFG_ALT_MODE_ONE_LINE              (1LU << 16LU)

-#define WSPI_CFG_ALT_MODE_TWO_LINES             (2LU << 16LU)

-#define WSPI_CFG_ALT_MODE_FOUR_LINES            (3LU << 16LU)

-#define WSPI_CFG_ALT_MODE_EIGHT_LINES           (4LU << 16LU)

-

-#define WSPI_CFG_ALT_DDR                        (1LU << 19LU)

-

-#define WSPI_CFG_ALT_SIZE_MASK                  (3LU << 20LU)

-#define WSPI_CFG_ALT_SIZE_8                     (0LU << 20LU)

-#define WSPI_CFG_ALT_SIZE_16                    (1LU << 20LU)

-#define WSPI_CFG_ALT_SIZE_24                    (2LU << 20LU)

-#define WSPI_CFG_ALT_SIZE_32                    (3LU << 20LU)

-

-#define WSPI_CFG_DATA_MODE_MASK                 (7LU << 24LU)

-#define WSPI_CFG_DATA_MODE_NONE                 (0LU << 24LU)

-#define WSPI_CFG_DATA_MODE_ONE_LINE             (1LU << 24LU)

-#define WSPI_CFG_DATA_MODE_TWO_LINES            (2LU << 24LU)

-#define WSPI_CFG_DATA_MODE_FOUR_LINES           (3LU << 24LU)

-#define WSPI_CFG_DATA_MODE_EIGHT_LINES          (4LU << 24LU)

-

-#define WSPI_CFG_DATA_DDR                       (1LU << 27LU)

-

-#define WSPI_CFG_SIOO                           (1LU << 31LU)

-/** @} */

-

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -192,10 +126,81 @@ typedef struct {
 #error "low level does not define WSPI_SUPPORTS_MEMMAP"

 #endif

 

+#if !defined(WSPI_DEFAULT_CFG_MASKS)

+#error "low level does not define WSPI_DEFAULT_CFG_MASKS"

+#endif

+

 /*===========================================================================*/

 /* Driver macros.                                                            */

 /*===========================================================================*/

 

+#if (WSPI_DEFAULT_CFG_MASKS == TRUE) || defined(__DOXYGEN__)

+/**

+ * @name    Transfer options

+ * @note    The low level driver has the option to override the following

+ *          definitions and use its own ones. In must take care to use

+ *          the same name for the same function or compatibility is not

+ *          ensured.

+ * @{

+ */

+#define WSPI_CFG_INSTRUCTION_MODE_MASK          (7LU << 0LU)

+#define WSPI_CFG_INSTRUCTION_MODE_NONE          (0LU << 0LU)

+#define WSPI_CFG_INSTRUCTION_MODE_ONE_LINES     (1LU << 0LU)

+#define WSPI_CFG_INSTRUCTION_MODE_TWO_LINES     (2LU << 0LU)

+#define WSPI_CFG_INSTRUCTION_MODE_FOUR_LINES    (3LU << 0LU)

+#define WSPI_CFG_INSTRUCTION_MODE_EIGHT_LINES   (4LU << 0LU)

+

+#define WSPI_CFG_INSTRUCTION_DDR                (1LU << 3LU)

+

+#define WSPI_CFG_INSTRUCTION_SIZE_MASK          (3LU << 4LU)

+#define WSPI_CFG_INSTRUCTION_SIZE_8             (0LU << 4LU)

+#define WSPI_CFG_INSTRUCTION_SIZE_16            (1LU << 4LU)

+#define WSPI_CFG_INSTRUCTION_SIZE_24            (2LU << 4LU)

+#define WSPI_CFG_INSTRUCTION_SIZE_32            (3LU << 4LU)

+

+#define WSPI_CFG_ADDR_MODE_MASK                 (7LU << 8LU)

+#define WSPI_CFG_ADDR_MODE_NONE                 (0LU << 8LU)

+#define WSPI_CFG_ADDR_MODE_ONE_LINE             (1LU << 8LU)

+#define WSPI_CFG_ADDR_MODE_TWO_LINES            (2LU << 8LU)

+#define WSPI_CFG_ADDR_MODE_FOUR_LINES           (3LU << 8LU)

+#define WSPI_CFG_ADDR_MODE_EIGHT_LINES          (4LU << 8LU)

+

+#define WSPI_CFG_ADDR_DDR                       (1LU << 11LU)

+

+#define WSPI_CFG_ADDR_SIZE_MASK                 (3LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_8                    (0LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_16                   (1LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_24                   (2LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_32                   (3LU << 12LU)

+

+#define WSPI_CFG_ALT_MODE_MASK                  (7LU << 16LU)

+#define WSPI_CFG_ALT_MODE_NONE                  (0LU << 16LU)

+#define WSPI_CFG_ALT_MODE_ONE_LINE              (1LU << 16LU)

+#define WSPI_CFG_ALT_MODE_TWO_LINES             (2LU << 16LU)

+#define WSPI_CFG_ALT_MODE_FOUR_LINES            (3LU << 16LU)

+#define WSPI_CFG_ALT_MODE_EIGHT_LINES           (4LU << 16LU)

+

+#define WSPI_CFG_ALT_DDR                        (1LU << 19LU)

+

+#define WSPI_CFG_ALT_SIZE_MASK                  (3LU << 20LU)

+#define WSPI_CFG_ALT_SIZE_8                     (0LU << 20LU)

+#define WSPI_CFG_ALT_SIZE_16                    (1LU << 20LU)

+#define WSPI_CFG_ALT_SIZE_24                    (2LU << 20LU)

+#define WSPI_CFG_ALT_SIZE_32                    (3LU << 20LU)

+

+#define WSPI_CFG_DATA_MODE_MASK                 (7LU << 24LU)

+#define WSPI_CFG_DATA_MODE_NONE                 (0LU << 24LU)

+#define WSPI_CFG_DATA_MODE_ONE_LINE             (1LU << 24LU)

+#define WSPI_CFG_DATA_MODE_TWO_LINES            (2LU << 24LU)

+#define WSPI_CFG_DATA_MODE_FOUR_LINES           (3LU << 24LU)

+#define WSPI_CFG_DATA_MODE_EIGHT_LINES          (4LU << 24LU)

+

+#define WSPI_CFG_DATA_DDR                       (1LU << 27LU)

+

+#define WSPI_CFG_SIOO                           (1LU << 31LU)

+/** @} */

+#endif /* WSPI_USE_DEFAULT_CFG_MASKS == TRUE */

+

 /**

  * @name    Macro Functions

  * @{

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
new file mode 100644
index 000000000..233caa67a
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
@@ -0,0 +1,208 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_wspi_lld.c

+ * @brief   PLATFORM WSPI subsystem low level driver source.

+ *

+ * @addtogroup WSPI

+ * @{

+ */

+

+#include "hal.h"

+

+#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/** @brief WSPID1 driver identifier.*/

+#if (PLATFORM_WSPI_USE_WSPI1 == TRUE) || defined(__DOXYGEN__)

+WSPIDriver WSPID1;

+#endif

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level WSPI driver initialization.

+ *

+ * @notapi

+ */

+void wspi_lld_init(void) {

+

+#if PLATFORM_WSPI_USE_WSPI1

+  wspiObjectInit(&WSPID1);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the WSPI peripheral.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ *

+ * @notapi

+ */

+void wspi_lld_start(WSPIDriver *wspip) {

+

+  /* If in stopped state then full initialization.*/

+  if (wspip->state == WSPI_STOP) {

+#if PLATFORM_WSPI_USE_WSPI1

+    if (&WSPID1 == wspip) {

+    }

+#endif

+

+    /* Common initializations.*/

+  }

+

+  /* WSPI setup and enable.*/

+}

+

+/**

+ * @brief   Deactivates the WSPI peripheral.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ *

+ * @notapi

+ */

+void wspi_lld_stop(WSPIDriver *wspip) {

+

+  /* If in ready state then disables WSPI.*/

+  if (wspip->state == WSPI_READY) {

+

+    /* WSPI disable.*/

+

+    /* Stopping involved clocks.*/

+#if PLATFORM_WSPI_USE_WSPI1

+    if (&WSPID1 == wspip) {

+    }

+#endif

+  }

+}

+

+/**

+ * @brief   Sends a command without data phase.

+ * @post    At the end of the operation the configured callback is invoked.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ * @param[in] cmdp      pointer to the command descriptor

+ *

+ * @notapi

+ */

+void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {

+

+  (void)wspip;

+  (void)cmdp;

+}

+

+/**

+ * @brief   Sends a command with data over the WSPI bus.

+ * @post    At the end of the operation the configured callback is invoked.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ * @param[in] cmdp      pointer to the command descriptor

+ * @param[in] n         number of bytes to send

+ * @param[in] txbuf     the pointer to the transmit buffer

+ *

+ * @notapi

+ */

+void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,

+                   size_t n, const uint8_t *txbuf) {

+

+  (void)wspip;

+  (void)cmdp;

+  (void)n;

+  (void)txbuf;

+}

+

+/**

+ * @brief   Sends a command then receives data over the WSPI bus.

+ * @post    At the end of the operation the configured callback is invoked.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ * @param[in] cmdp      pointer to the command descriptor

+ * @param[in] n         number of bytes to send

+ * @param[out] rxbuf    the pointer to the receive buffer

+ *

+ * @notapi

+ */

+void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,

+                      size_t n, uint8_t *rxbuf) {

+

+  (void)wspip;

+  (void)cmdp;

+  (void)n;

+  (void)rxbuf;

+}

+

+#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__)

+/**

+ * @brief   Maps in memory space a WSPI flash device.

+ * @pre     The memory flash device must be initialized appropriately

+ *          before mapping it in memory space.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ * @param[in] cmdp      pointer to the command descriptor

+ * @param[out] addrp    pointer to the memory start address of the mapped

+ *                      flash or @p NULL

+ *

+ * @notapi

+ */

+void wspi_lld_map_flash(WSPIDriver *wspip,

+                        const wspi_command_t *cmdp,

+                        uint8_t **addrp) {

+

+  (void)wspip;

+  (void)cmdp;

+  (void)addrp;

+}

+

+/**

+ * @brief   Unmaps from memory space a WSPI flash device.

+ * @post    The memory flash device must be re-initialized for normal

+ *          commands exchange.

+ *

+ * @param[in] wspip     pointer to the @p WSPIDriver object

+ *

+ * @notapi

+ */

+void wspi_lld_unmap_flash(WSPIDriver *wspip) {

+

+  (void)wspip;

+}

+#endif /* WSPI_SUPPORTS_MEMMAP == TRUE */

+

+#endif /* HAL_USE_WSPI */

+

+/** @} */

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
new file mode 100644
index 000000000..456b0308d
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
@@ -0,0 +1,329 @@
+/*

+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    hal_wspi_lld.h

+ * @brief   PLATFORM WSPI subsystem low level driver header.

+ *

+ * @addtogroup WSPI

+ * @{

+ */

+

+#ifndef HAL_WSPI_LLD_H

+#define HAL_WSPI_LLD_H

+

+#if (HAL_USE_WSPI == TRUE) || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+/**

+ * @name    WSPI implementation capabilities

+ * @{

+ */

+#define WSPI_SUPPORTS_MEMMAP                TRUE

+#define WSPI_DEFAULT_CFG_MASKS              FALSE

+/** @} */

+

+/**

+ * @name    Transfer options

+ * @note    The low level driver has the option to override the following

+ *          definitions and use its own ones. In must take care to use

+ *          the same name for the same function or compatibility is not

+ *          ensured.

+ * @note    There are the following limitations in this implementation:

+ *          - Eight lines are not supported.

+ *          - DDR mode is only supported for the whole command, separate

+ *            masks are defined but all define the same bit.

+ *          - Only 8 bits instructions are supported.

+ *          .

+ * @{

+ */

+#define WSPI_CFG_INSTRUCTION_MODE_MASK          (3LU << 8LU)

+#define WSPI_CFG_INSTRUCTION_MODE_NONE          (0LU << 8LU)

+#define WSPI_CFG_INSTRUCTION_MODE_ONE_LINES     (1LU << 8LU)

+#define WSPI_CFG_INSTRUCTION_MODE_TWO_LINES     (2LU << 8LU)

+#define WSPI_CFG_INSTRUCTION_MODE_FOUR_LINES    (3LU << 8LU)

+

+#define WSPI_CFG_INSTRUCTION_DDR                (1LU << 31LU)

+

+#define WSPI_CFG_INSTRUCTION_SIZE_MASK          0LU

+#define WSPI_CFG_INSTRUCTION_SIZE_8             0LU

+

+#define WSPI_CFG_ADDR_MODE_MASK                 (3LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_NONE                 (0LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_ONE_LINE             (1LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_TWO_LINES            (2LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_FOUR_LINES           (3LU << 10LU)

+

+#define WSPI_CFG_ADDR_DDR                       (1LU << 31LU)

+

+#define WSPI_CFG_ADDR_SIZE_MASK                 (3LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_8                    (0LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_16                   (1LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_24                   (2LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_32                   (3LU << 12LU)

+

+#define WSPI_CFG_ALT_MODE_MASK                  (3LU << 14LU)

+#define WSPI_CFG_ALT_MODE_NONE                  (0LU << 14LU)

+#define WSPI_CFG_ALT_MODE_ONE_LINE              (1LU << 14LU)

+#define WSPI_CFG_ALT_MODE_TWO_LINES             (2LU << 14LU)

+#define WSPI_CFG_ALT_MODE_FOUR_LINES            (3LU << 14LU)

+

+#define WSPI_CFG_ALT_DDR                        (1LU << 31LU)

+

+#define WSPI_CFG_ALT_SIZE_MASK                  (3LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_8                     (0LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_16                    (1LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_24                    (2LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_32                    (3LU << 16LU)

+

+#define WSPI_CFG_DATA_MODE_MASK                 (3LU << 24LU)

+#define WSPI_CFG_DATA_MODE_NONE                 (0LU << 24LU)

+#define WSPI_CFG_DATA_MODE_ONE_LINE             (1LU << 24LU)

+#define WSPI_CFG_DATA_MODE_TWO_LINES            (2LU << 24LU)

+#define WSPI_CFG_DATA_MODE_FOUR_LINES           (3LU << 24LU)

+

+#define WSPI_CFG_DATA_DDR                       (1LU << 31LU)

+

+#define WSPI_CFG_SIOO                           (1LU << 28LU)

+/** @} */

+

+/**

+ * @name    DCR register options

+ * @{

+ */

+#define STM32_DCR_CK_MODE                   (1U << 0U)

+#define STM32_DCR_CSHT_MASK                 (7U << 8U)

+#define STM32_DCR_CSHT(n)                   ((n) << 8U)

+#define STM32_DCR_FSIZE_MASK                (31U << 16U)

+#define STM32_DCR_FSIZE(n)                  ((n) << 16U)

+/** @} */

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @name    Configuration options

+ * @{

+ */

+/**

+ * @brief   WSPID1 driver enable switch.

+ * @details If set to @p TRUE the support for QUADSPI1 is included.

+ * @note    The default is @p FALSE.

+ */

+#if !defined(STM32_WSPI_USE_QUADSPI1) || defined(__DOXYGEN__)

+#define STM32_WSPI_USE_QUADSPI1             FALSE

+#endif

+

+/**

+ * @brief   QUADSPI1 prescaler setting.

+ * @note    This is the prescaler divider value 1..256. The maximum frequency

+ *          varies depending on the STM32 model and operating conditions,

+ *          find the details in the data sheet.

+ */

+#if !defined(STM32_WSPI_QUADSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)

+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1

+#endif

+

+/**

+ * @brief   QUADSPI1 interrupt priority level setting.

+ */

+#if !defined(STM32_WSPI_QUADSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_WSPI_QUADSPI1_IRQ_PRIORITY    10

+#endif

+

+/**

+ * @brief   QUADSPI1 DMA priority (0..3|lowest..highest).

+ */

+#if !defined(STM32_WSPI_QUADSPI1_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_WSPI_QUADSPI1_DMA_PRIORITY    1

+#endif

+

+/**

+ * @brief   QUADSPI1 DMA interrupt priority level setting.

+ */

+#if !defined(STM32_WSPI_QUADSPI1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_WSPI_QUADSPI1_DMA_IRQ_PRIORITY 10

+#endif

+

+/**

+ * @brief   QUADSPI DMA error hook.

+ */

+#if !defined(STM32_WSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

+#define STM32_WSPI_DMA_ERROR_HOOK(qspip)    osalSysHalt("DMA failure")

+#endif

+

+/**

+ * @brief   Enables a workaround for a STM32L476 QUADSPI errata.

+ * @details The document DM00111498 states: "QUADSPI_BK1_IO1 is always an

+ *          input when the command is sent in dual or quad SPI mode".

+ *          This workaround makes commands without address or data phases

+ *          to be sent as alternate bytes.

+ */

+#if !defined(STM32_USE_STM32_D1_WORKAROUND) || defined(__DOXYGEN__)

+#define STM32_USE_STM32_D1_WORKAROUND       TRUE

+#endif

+/** @} */

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+#if STM32_WSPI_USE_QUADSPI1 && !STM32_HAS_QUADSPI1

+#error "QUADSPI1 not present in the selected device"

+#endif

+

+#if !STM32_WSPI_USE_QUADSPI1

+#error "WSPI driver activated but no QUADSPI peripheral assigned"

+#endif

+

+#if STM32_WSPI_USE_QUADSPI1 &&                                              \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_QUADSPI1_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to QUADSPI1"

+#endif

+

+#if STM32_WSPI_USE_QUADSPI1 &&                                              \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_WSPI_QUADSPI1_DMA_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to QUADSPI1 DMA"

+#endif

+

+#if STM32_WSPI_USE_QUADSPI1 &&                                              \

+    !STM32_DMA_IS_VALID_PRIORITY(STM32_WSPI_QUADSPI1_DMA_PRIORITY)

+#error "Invalid DMA priority assigned to QUADSPI1"

+#endif

+

+#if (STM32_WSPI_QUADSPI1_PRESCALER_VALUE < 1) ||                            \

+    (STM32_WSPI_QUADSPI1_PRESCALER_VALUE > 256)

+#error "STM32_WSPI_QUADSPI1_PRESCALER_VALUE not within 1..256"

+#endif

+

+/* Check on the presence of the DMA streams settings in mcuconf.h.*/

+#if STM32_WSPI_USE_QUADSPI1 && !defined(STM32_WSPI_QUADSPI1_DMA_STREAM)

+#error "QUADSPI1 DMA stream not defined"

+#endif

+

+/* Check on the validity of the assigned DMA channels.*/

+#if STM32_WSPI_USE_QUADSPI1 &&                                                   \

+    !STM32_DMA_IS_VALID_ID(STM32_WSPI_QUADSPI1_DMA_STREAM, STM32_QUADSPI1_DMA_MSK)

+#error "invalid DMA stream associated to QUADSPI1"

+#endif

+

+#if !defined(STM32_DMA_REQUIRED)

+#define STM32_DMA_REQUIRED

+#endif

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Driver configuration structure.

+ */

+struct hal_wspi_config {

+  /**

+   * @brief   Operation complete callback or @p NULL.

+   */

+  wspicallback_t             end_cb;

+  /* End of the mandatory fields.*/

+  /**

+   * @brief   DCR register initialization data.

+   */

+  uint32_t                  dcr;

+};

+

+/**

+ * @brief   Structure representing an WSPI driver.

+ */

+struct hal_wspi_driver {

+  /**

+   * @brief   Driver state.

+   */

+  wspistate_t               state;

+  /**

+   * @brief   Current configuration data.

+   */

+  const WSPIConfig          *config;

+#if (WSPI_USE_WAIT == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief   Waiting thread.

+   */

+  thread_reference_t        thread;

+#endif /* WSPI_USE_WAIT */

+#if (WSPI_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)

+  /**

+   * @brief   Mutex protecting the peripheral.

+   */

+  mutex_t                   mutex;

+#endif /* WSPI_USE_MUTUAL_EXCLUSION */

+#if defined(WSPI_DRIVER_EXT_FIELDS)

+  WSPI_DRIVER_EXT_FIELDS

+#endif

+  /* End of the mandatory fields.*/

+  /**

+   * @brief   Pointer to the QUADSPIx registers block.

+   */

+  QUADSPI_TypeDef           *qspi;

+  /**

+   * @brief   QUADSPI DMA stream.

+   */

+  const stm32_dma_stream_t  *dma;

+  /**

+   * @brief   QUADSPI DMA mode bit mask.

+   */

+  uint32_t                  dmamode;

+};

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+

+#if (STM32_WSPI_USE_QUADSPI1 == TRUE) && !defined(__DOXYGEN__)

+extern WSPIDriver WSPID1;

+#endif

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void wspi_lld_init(void);

+  void wspi_lld_start(WSPIDriver *wspip);

+  void wspi_lld_stop(WSPIDriver *wspip);

+  void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp);

+  void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,

+                     size_t n, const uint8_t *txbuf);

+  void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,

+                        size_t n, uint8_t *rxbuf);

+#if WSPI_SUPPORTS_MEMMAP == TRUE

+  void wspi_lld_map_flash(WSPIDriver *wspip,

+                          const wspi_command_t *cmdp,

+                          uint8_t **addrp);

+  void wspi_lld_unmap_flash(WSPIDriver *wspip);

+#endif

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_WSPI */

+

+#endif /* HAL_WSPI_LLD_H */

+

+/** @} */

diff --git a/os/hal/templates/hal_wspi_lld.h b/os/hal/templates/hal_wspi_lld.h
index 9b3a1550d..6c54d43b7 100644
--- a/os/hal/templates/hal_wspi_lld.h
+++ b/os/hal/templates/hal_wspi_lld.h
@@ -32,10 +32,11 @@
 /*===========================================================================*/

 

 /**

- * @name    WSPI capabilities

+ * @name    WSPI implementation capabilities

  * @{

  */

 #define WSPI_SUPPORTS_MEMMAP                TRUE

+#define WSPI_DEFAULT_CFG_MASKS              TRUE

 /** @} */

 

 /*===========================================================================*/